source: ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_trigger_proc/w3_warplab_trigger_proc_init.m

Last change on this file was 4830, checked in by welsh, 7 years ago

Version 1.07.g - Output delays are now 16 bit for all outputs. Moved trigger input enables to register in IOB.

File size: 7.1 KB
Line 
1% ------------------------------------------------------------------------
2%  Initial Register Values
3% ------------------------------------------------------------------------
4
5simulation = false;
6
7% ------------------------------------------------------------------------
8% Trigger Input Configuration Register:
9%   Basic register format:
10%       [31]   - Reset
11%       [30]   - Debounce
12%       [29:5] - Reserved
13%       [4:0]  - Input Delay
14%   This register is replicated for each of the trigger inputs.  There are
15%   a number of reserved bits per trigger input in case the input delay
16%   needs to be increased in the future.
17%
18%   Input Trigger order:
19%       0 - Ethernet A
20%             NOTE:  Debounce bit is used as a SW trigger
21%                    Bit 29 is used as a HW / SW select
22%       1 - Energy Detection
23%             NOTE:  Debounce bit is not supported
24%                    Delay is not supported
25%       2 - AGC
26%             NOTE:  Debounce bit is not supported
27%       3 - Software Trigger
28%             NOTE:  Debounce bit is used as a SW trigger
29%                    Delay is not supported
30%       4 - Debug Input Pin 0
31%       5 - Debug Input Pin 1
32%       6 - Debug Input Pin 2
33%       7 - Debug Input Pin 3
34%       8 - Ethernet B
35%             NOTE:  Debounce bit is used as a SW trigger
36%                    Bit 29 is used as a HW / SW select
37%         
38%
39if (simulation)
40    TRIG_IN_CONF_0 = hex2dec('80000000');    % HW path is selected
41    TRIG_IN_CONF_1 = hex2dec('80000000');
42    TRIG_IN_CONF_2 = hex2dec('80000000');
43    TRIG_IN_CONF_3 = hex2dec('80000000');
44    TRIG_IN_CONF_4 = hex2dec('00000000');    % Enable Input pin 0; No debounce; No delay
45    TRIG_IN_CONF_5 = hex2dec('C0000000');    % Debounce enabled
46    TRIG_IN_CONF_6 = hex2dec('C0000000');    % Debounce enabled
47    TRIG_IN_CONF_7 = hex2dec('C0000000');    % Debounce enabled
48    TRIG_IN_CONF_8 = hex2dec('80000000');    % HW path is selected
49else
50    TRIG_IN_CONF_0 = hex2dec('80000000');    % HW path is selected
51    TRIG_IN_CONF_1 = hex2dec('80000000');
52    TRIG_IN_CONF_2 = hex2dec('80000000');
53    TRIG_IN_CONF_3 = hex2dec('80000000');
54    TRIG_IN_CONF_4 = hex2dec('C0000000');    % Debounce enabled
55    TRIG_IN_CONF_5 = hex2dec('C0000000');    % Debounce enabled
56    TRIG_IN_CONF_6 = hex2dec('C0000000');    % Debounce enabled
57    TRIG_IN_CONF_7 = hex2dec('C0000000');    % Debounce enabled
58    TRIG_IN_CONF_8 = hex2dec('80000000');    % HW path is selected
59end
60
61% ------------------------------------------------------------------------
62% Trigger Output Configuration Register:
63%   Register format:
64%       CONF_0:
65%           [31:25] - Reserved
66%           [24]    - Output OR use trigger input 8
67%           [23]    - Output OR use trigger input 7
68%           [22]    - Output OR use trigger input 6
69%           [21]    - Output OR use trigger input 5
70%           [20]    - Output OR use trigger input 4
71%           [19]    - Output OR use trigger input 3
72%           [18]    - Output OR use trigger input 2
73%           [17]    - Output OR use trigger input 1
74%           [16]    - Output OR use trigger input 0
75%           [15: 9] - Reserved
76%           [ 8]    - Output AND use trigger input 8
77%           [ 7]    - Output AND use trigger input 7
78%           [ 6]    - Output AND use trigger input 6
79%           [ 5]    - Output AND use trigger input 5
80%           [ 4]    - Output AND use trigger input 4
81%           [ 3]    - Output AND use trigger input 3
82%           [ 2]    - Output AND use trigger input 2
83%           [ 1]    - Output AND use trigger input 1
84%           [ 0]    - Output AND use trigger input 0
85%       CONF_1:
86%           [31]    - Disable
87%           [30]    - Bypass trigger output pulse extender
88%           [29:16] - Reserved
89%           [15: 0] - Output Delay
90%   These two registers are replicated for each of the trigger outputs.
91%
92%   Output Trigger order (connected in MHS file):
93%       0 - Buffer trigger input
94%       1 - AGC packet in
95%       2 - Debug Output Pin 0
96%       3 - Debug Output Pin 1
97%       4 - Debug Output Pin 2
98%       5 - Debug Output Pin 3
99%
100if (simulation)
101    TRIG_OUT_5_CONF_0 = hex2dec('00000000');
102    TRIG_OUT_5_CONF_1 = hex2dec('80000000');
103
104    TRIG_OUT_4_CONF_0 = hex2dec('00000000');
105    TRIG_OUT_4_CONF_1 = hex2dec('80000000');
106
107    TRIG_OUT_3_CONF_0 = hex2dec('00000000');
108    TRIG_OUT_3_CONF_1 = hex2dec('80000000');
109
110    TRIG_OUT_2_CONF_0 = hex2dec('00100000');    % Enable output based on trigger input pin 0; No delay
111    TRIG_OUT_2_CONF_1 = hex2dec('00000000');
112
113    TRIG_OUT_1_CONF_0 = hex2dec('00000000');
114    TRIG_OUT_1_CONF_1 = hex2dec('80000000');
115
116    TRIG_OUT_0_CONF_0 = hex2dec('00000000');
117    TRIG_OUT_0_CONF_1 = hex2dec('80000000');
118else
119    TRIG_OUT_5_CONF_0 = hex2dec('00000000');
120    TRIG_OUT_5_CONF_1 = hex2dec('80000000');
121
122    TRIG_OUT_4_CONF_0 = hex2dec('00000000');
123    TRIG_OUT_4_CONF_1 = hex2dec('80000000');
124
125    TRIG_OUT_3_CONF_0 = hex2dec('00000000');
126    TRIG_OUT_3_CONF_1 = hex2dec('80000000');
127
128    TRIG_OUT_2_CONF_0 = hex2dec('00000000');
129    TRIG_OUT_2_CONF_1 = hex2dec('80000000');
130
131    TRIG_OUT_1_CONF_0 = hex2dec('00000000');
132    TRIG_OUT_1_CONF_1 = hex2dec('80000000');
133
134    TRIG_OUT_0_CONF_0 = hex2dec('00000000');
135    TRIG_OUT_0_CONF_1 = hex2dec('80000000');
136end
137
138% ------------------------------------------------------------------------
139% RSSI Packet Detection Configuration Register
140%   Register format:
141%       [31]    - Packet detect reset
142%       [30: 4] - Reserved
143%       [ 3]    - Packet detect mask RF D
144%       [ 2]    - Packet detect mask RF C
145%       [ 1]    - Packet detect mask RF B
146%       [ 0]    - Packet detect mask RF A
147%
148if (simulation)
149    RSSI_PKT_DET_CONFIG = hex2dec('00000000');
150else
151    RSSI_PKT_DET_CONFIG = hex2dec('00000000');
152end
153
154% ------------------------------------------------------------------------
155% RSSI Packet Detection Threshold Register
156%   Register format:
157%       [31:16] - Packet detect energy threshold busy
158%       [15: 0] - Packet detect energy threshold idle
159%
160if (simulation)
161    RSSI_PKT_DET_THRESHOLDS = hex2dec('00000000');
162else
163    RSSI_PKT_DET_THRESHOLDS = hex2dec('00000000');
164end
165
166% ------------------------------------------------------------------------
167% RSSI Packet Detection Duration Register
168%   Register format:
169%       [31:21] - Reserved
170%       [20:16] - Packet detect RSSI average length
171%       [15: 8] - Packet detect duration busy
172%       [ 7: 0] - Packet detect duration idle
173%
174if (simulation)
175    RSSI_PKT_DET_DURATIONS = hex2dec('00000000');
176else
177    RSSI_PKT_DET_DURATIONS = hex2dec('00000000');
178end
179
180% ------------------------------------------------------------------------
181% Ethernet Trigger Memories
182%
183if (simulation)
184    PKT_OPS_0      = hex2dec('00000000');
185    PKT_TEMPLATE_0 = hex2dec('00000000');
186
187    PKT_OPS_1      = hex2dec('00000000');
188    PKT_TEMPLATE_1 = hex2dec('00000000');
189else
190    PKT_OPS_0      = hex2dec('00000000');
191    PKT_TEMPLATE_0 = hex2dec('00000000');
192
193    PKT_OPS_1      = hex2dec('00000000');
194    PKT_TEMPLATE_1 = hex2dec('00000000');
195end
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