| 1 | % ------------------------------------------------------------------------ |
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| 2 | % Initial Register Values |
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| 3 | % ------------------------------------------------------------------------ |
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| 4 | |
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| 5 | simulation = false; |
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| 6 | |
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| 7 | % ------------------------------------------------------------------------ |
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| 8 | % Trigger Input Configuration Register: |
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| 9 | % Basic register format: |
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| 10 | % [31] - Reset |
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| 11 | % [30] - Debounce |
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| 12 | % [29:5] - Reserved |
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| 13 | % [4:0] - Input Delay |
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| 14 | % This register is replicated for each of the trigger inputs. There are |
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| 15 | % a number of reserved bits per trigger input in case the input delay |
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| 16 | % needs to be increased in the future. |
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| 17 | % |
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| 18 | % Input Trigger order: |
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| 19 | % 0 - Ethernet A |
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| 20 | % NOTE: Debounce bit is used as a SW trigger |
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| 21 | % Bit 29 is used as a HW / SW select |
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| 22 | % 1 - Energy Detection |
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| 23 | % NOTE: Debounce bit is not supported |
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| 24 | % Delay is not supported |
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| 25 | % 2 - AGC |
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| 26 | % NOTE: Debounce bit is not supported |
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| 27 | % 3 - Software Trigger |
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| 28 | % NOTE: Debounce bit is used as a SW trigger |
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| 29 | % Delay is not supported |
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| 30 | % 4 - Debug Input Pin 0 |
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| 31 | % 5 - Debug Input Pin 1 |
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| 32 | % 6 - Debug Input Pin 2 |
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| 33 | % 7 - Debug Input Pin 3 |
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| 34 | % 8 - Ethernet B |
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| 35 | % NOTE: Debounce bit is used as a SW trigger |
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| 36 | % Bit 29 is used as a HW / SW select |
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| 37 | % |
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| 38 | % |
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| 39 | if (simulation) |
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| 40 | TRIG_IN_CONF_0 = hex2dec('80000000'); % HW path is selected |
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| 41 | TRIG_IN_CONF_1 = hex2dec('80000000'); |
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| 42 | TRIG_IN_CONF_2 = hex2dec('80000000'); |
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| 43 | TRIG_IN_CONF_3 = hex2dec('80000000'); |
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| 44 | TRIG_IN_CONF_4 = hex2dec('00000000'); % Enable Input pin 0; No debounce; No delay |
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| 45 | TRIG_IN_CONF_5 = hex2dec('C0000000'); % Debounce enabled |
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| 46 | TRIG_IN_CONF_6 = hex2dec('C0000000'); % Debounce enabled |
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| 47 | TRIG_IN_CONF_7 = hex2dec('C0000000'); % Debounce enabled |
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| 48 | TRIG_IN_CONF_8 = hex2dec('80000000'); % HW path is selected |
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| 49 | else |
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| 50 | TRIG_IN_CONF_0 = hex2dec('80000000'); % HW path is selected |
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| 51 | TRIG_IN_CONF_1 = hex2dec('80000000'); |
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| 52 | TRIG_IN_CONF_2 = hex2dec('80000000'); |
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| 53 | TRIG_IN_CONF_3 = hex2dec('80000000'); |
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| 54 | TRIG_IN_CONF_4 = hex2dec('C0000000'); % Debounce enabled |
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| 55 | TRIG_IN_CONF_5 = hex2dec('C0000000'); % Debounce enabled |
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| 56 | TRIG_IN_CONF_6 = hex2dec('C0000000'); % Debounce enabled |
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| 57 | TRIG_IN_CONF_7 = hex2dec('C0000000'); % Debounce enabled |
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| 58 | TRIG_IN_CONF_8 = hex2dec('80000000'); % HW path is selected |
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| 59 | end |
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| 60 | |
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| 61 | % ------------------------------------------------------------------------ |
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| 62 | % Trigger Output Configuration Register: |
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| 63 | % Register format: |
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| 64 | % CONF_0: |
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| 65 | % [31:25] - Reserved |
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| 66 | % [24] - Output OR use trigger input 8 |
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| 67 | % [23] - Output OR use trigger input 7 |
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| 68 | % [22] - Output OR use trigger input 6 |
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| 69 | % [21] - Output OR use trigger input 5 |
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| 70 | % [20] - Output OR use trigger input 4 |
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| 71 | % [19] - Output OR use trigger input 3 |
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| 72 | % [18] - Output OR use trigger input 2 |
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| 73 | % [17] - Output OR use trigger input 1 |
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| 74 | % [16] - Output OR use trigger input 0 |
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| 75 | % [15: 9] - Reserved |
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| 76 | % [ 8] - Output AND use trigger input 8 |
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| 77 | % [ 7] - Output AND use trigger input 7 |
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| 78 | % [ 6] - Output AND use trigger input 6 |
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| 79 | % [ 5] - Output AND use trigger input 5 |
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| 80 | % [ 4] - Output AND use trigger input 4 |
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| 81 | % [ 3] - Output AND use trigger input 3 |
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| 82 | % [ 2] - Output AND use trigger input 2 |
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| 83 | % [ 1] - Output AND use trigger input 1 |
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| 84 | % [ 0] - Output AND use trigger input 0 |
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| 85 | % CONF_1: |
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| 86 | % [31] - Disable |
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| 87 | % [30] - Bypass trigger output pulse extender |
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| 88 | % [29:16] - Reserved |
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| 89 | % [15: 0] - Output Delay |
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| 90 | % These two registers are replicated for each of the trigger outputs. |
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| 91 | % |
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| 92 | % Output Trigger order (connected in MHS file): |
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| 93 | % 0 - Buffer trigger input |
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| 94 | % 1 - AGC packet in |
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| 95 | % 2 - Debug Output Pin 0 |
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| 96 | % 3 - Debug Output Pin 1 |
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| 97 | % 4 - Debug Output Pin 2 |
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| 98 | % 5 - Debug Output Pin 3 |
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| 99 | % |
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| 100 | if (simulation) |
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| 101 | TRIG_OUT_5_CONF_0 = hex2dec('00000000'); |
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| 102 | TRIG_OUT_5_CONF_1 = hex2dec('80000000'); |
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| 103 | |
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| 104 | TRIG_OUT_4_CONF_0 = hex2dec('00000000'); |
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| 105 | TRIG_OUT_4_CONF_1 = hex2dec('80000000'); |
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| 106 | |
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| 107 | TRIG_OUT_3_CONF_0 = hex2dec('00000000'); |
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| 108 | TRIG_OUT_3_CONF_1 = hex2dec('80000000'); |
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| 109 | |
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| 110 | TRIG_OUT_2_CONF_0 = hex2dec('00100000'); % Enable output based on trigger input pin 0; No delay |
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| 111 | TRIG_OUT_2_CONF_1 = hex2dec('00000000'); |
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| 112 | |
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| 113 | TRIG_OUT_1_CONF_0 = hex2dec('00000000'); |
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| 114 | TRIG_OUT_1_CONF_1 = hex2dec('80000000'); |
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| 115 | |
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| 116 | TRIG_OUT_0_CONF_0 = hex2dec('00000000'); |
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| 117 | TRIG_OUT_0_CONF_1 = hex2dec('80000000'); |
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| 118 | else |
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| 119 | TRIG_OUT_5_CONF_0 = hex2dec('00000000'); |
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| 120 | TRIG_OUT_5_CONF_1 = hex2dec('80000000'); |
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| 121 | |
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| 122 | TRIG_OUT_4_CONF_0 = hex2dec('00000000'); |
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| 123 | TRIG_OUT_4_CONF_1 = hex2dec('80000000'); |
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| 124 | |
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| 125 | TRIG_OUT_3_CONF_0 = hex2dec('00000000'); |
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| 126 | TRIG_OUT_3_CONF_1 = hex2dec('80000000'); |
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| 127 | |
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| 128 | TRIG_OUT_2_CONF_0 = hex2dec('00000000'); |
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| 129 | TRIG_OUT_2_CONF_1 = hex2dec('80000000'); |
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| 130 | |
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| 131 | TRIG_OUT_1_CONF_0 = hex2dec('00000000'); |
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| 132 | TRIG_OUT_1_CONF_1 = hex2dec('80000000'); |
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| 133 | |
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| 134 | TRIG_OUT_0_CONF_0 = hex2dec('00000000'); |
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| 135 | TRIG_OUT_0_CONF_1 = hex2dec('80000000'); |
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| 136 | end |
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| 137 | |
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| 138 | % ------------------------------------------------------------------------ |
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| 139 | % RSSI Packet Detection Configuration Register |
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| 140 | % Register format: |
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| 141 | % [31] - Packet detect reset |
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| 142 | % [30: 4] - Reserved |
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| 143 | % [ 3] - Packet detect mask RF D |
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| 144 | % [ 2] - Packet detect mask RF C |
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| 145 | % [ 1] - Packet detect mask RF B |
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| 146 | % [ 0] - Packet detect mask RF A |
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| 147 | % |
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| 148 | if (simulation) |
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| 149 | RSSI_PKT_DET_CONFIG = hex2dec('00000000'); |
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| 150 | else |
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| 151 | RSSI_PKT_DET_CONFIG = hex2dec('00000000'); |
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| 152 | end |
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| 153 | |
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| 154 | % ------------------------------------------------------------------------ |
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| 155 | % RSSI Packet Detection Threshold Register |
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| 156 | % Register format: |
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| 157 | % [31:16] - Packet detect energy threshold busy |
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| 158 | % [15: 0] - Packet detect energy threshold idle |
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| 159 | % |
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| 160 | if (simulation) |
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| 161 | RSSI_PKT_DET_THRESHOLDS = hex2dec('00000000'); |
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| 162 | else |
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| 163 | RSSI_PKT_DET_THRESHOLDS = hex2dec('00000000'); |
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| 164 | end |
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| 165 | |
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| 166 | % ------------------------------------------------------------------------ |
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| 167 | % RSSI Packet Detection Duration Register |
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| 168 | % Register format: |
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| 169 | % [31:21] - Reserved |
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| 170 | % [20:16] - Packet detect RSSI average length |
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| 171 | % [15: 8] - Packet detect duration busy |
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| 172 | % [ 7: 0] - Packet detect duration idle |
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| 173 | % |
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| 174 | if (simulation) |
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| 175 | RSSI_PKT_DET_DURATIONS = hex2dec('00000000'); |
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| 176 | else |
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| 177 | RSSI_PKT_DET_DURATIONS = hex2dec('00000000'); |
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| 178 | end |
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| 179 | |
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| 180 | % ------------------------------------------------------------------------ |
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| 181 | % Ethernet Trigger Memories |
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| 182 | % |
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| 183 | if (simulation) |
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| 184 | PKT_OPS_0 = hex2dec('00000000'); |
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| 185 | PKT_TEMPLATE_0 = hex2dec('00000000'); |
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| 186 | |
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| 187 | PKT_OPS_1 = hex2dec('00000000'); |
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| 188 | PKT_TEMPLATE_1 = hex2dec('00000000'); |
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| 189 | else |
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| 190 | PKT_OPS_0 = hex2dec('00000000'); |
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| 191 | PKT_TEMPLATE_0 = hex2dec('00000000'); |
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| 192 | |
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| 193 | PKT_OPS_1 = hex2dec('00000000'); |
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| 194 | PKT_TEMPLATE_1 = hex2dec('00000000'); |
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| 195 | end |
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