source:
ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference
| Name | Size | Rev | Age | Author | Last Change |
|---|---|---|---|---|---|
| ../ | |||||
| w3 | 4830 | 9 years | welsh | Version 1.07.g - Output delays are now 16 bit for all outputs. Moved … | |
| w2 | 4469 | 10 years | welsh | Version 1.04.b - Increased available AGC delay to (216 - 1) cycles. | |
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