1 |
|
---|
2 | # ##############################################################################
|
---|
3 | # WARPLab Reference Design
|
---|
4 | # XPS Hardware Specification (system.mhs)
|
---|
5 | # Copyright 2013 Mango Communications
|
---|
6 | # Distributed under the WARP license (http://warpproject.org/license)
|
---|
7 | # Target Board: Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 2.2 / Radio 1.4 / Clock 1.1
|
---|
8 | # WARPLab version: 7.5.0
|
---|
9 | # Family: virtex4
|
---|
10 | # Device: XC4VFX100
|
---|
11 | # Package: FF1517
|
---|
12 | # Speed Grade: -11
|
---|
13 | # Processor number: 1
|
---|
14 | # Processor 1: ppc405_0
|
---|
15 | # Processor clock frequency: 160.0
|
---|
16 | # Bus clock frequency: 80.0
|
---|
17 | # Debug Interface: FPGA JTAG
|
---|
18 | # ##############################################################################
|
---|
19 | PARAMETER VERSION = 2.1.0
|
---|
20 |
|
---|
21 |
|
---|
22 | # ##############################################################################
|
---|
23 | # Top Level Ports
|
---|
24 | # ##############################################################################
|
---|
25 | PORT UserIO_LEDs = UserIO_LEDs, DIR = O, VEC = [0:7]
|
---|
26 | PORT UserIO_IOEx_SDA = UserIO_IOEx_SDA, DIR = O
|
---|
27 | PORT UserIO_IOEx_SCL = UserIO_IOEx_SCL, DIR = O
|
---|
28 | PORT UserIO_PB = UserIO_PB, DIR = I, VEC = [0:3]
|
---|
29 | PORT UserIO_DIPSW = UserIO_DIPSW, DIR = I, VEC = [0:3]
|
---|
30 | PORT rs232_db9_RX = rs232_db9_RX, DIR = I
|
---|
31 | PORT rs232_db9_TX = rs232_db9_TX, DIR = O
|
---|
32 | PORT rs232_usb_RX = rs232_usb_RX, DIR = I
|
---|
33 | PORT rs232_usb_TX = rs232_usb_TX, DIR = O
|
---|
34 | PORT ETH_TemacPhy_RST_n = ETH_TemacPhy_RST_n, DIR = O
|
---|
35 | PORT ETH_MII_TX_CLK = ETH_MII_TX_CLK, DIR = I
|
---|
36 | PORT ETH_GMII_TXD = ETH_GMII_TXD, DIR = O, VEC = [7:0]
|
---|
37 | PORT ETH_GMII_TX_EN = ETH_GMII_TX_EN, DIR = O
|
---|
38 | PORT ETH_GMII_TX_ER = ETH_GMII_TX_ER, DIR = O
|
---|
39 | PORT ETH_GMII_TX_CLK = ETH_GMII_TX_CLK, DIR = O
|
---|
40 | PORT ETH_GMII_RXD = ETH_GMII_RXD, DIR = I, VEC = [7:0]
|
---|
41 | PORT ETH_GMII_RX_DV = ETH_GMII_RX_DV, DIR = I
|
---|
42 | PORT ETH_GMII_RX_ER = ETH_GMII_RX_ER, DIR = I
|
---|
43 | PORT ETH_GMII_RX_CLK = ETH_GMII_RX_CLK, DIR = I
|
---|
44 | PORT ETH_MDC = ETH_MDC, DIR = O
|
---|
45 | PORT ETH_MDIO = ETH_MDIO, DIR = IO
|
---|
46 | # Clock board config
|
---|
47 | PORT clk_board_config_sys_clk = clk_board_config_sys_clk, DIR = I
|
---|
48 | PORT clk_board_config_radio_dat_out = clk_board_config_radio_dat_out, DIR = O
|
---|
49 | PORT clk_board_config_radio_csb_out = clk_board_config_radio_csb_out, DIR = O
|
---|
50 | PORT clk_board_config_radio_en_out = clk_board_config_radio_en_out, DIR = O
|
---|
51 | PORT clk_board_config_radio_clk_out = clk_board_config_radio_clk_out, DIR = O
|
---|
52 | PORT clk_board_config_logic_dat_out = clk_board_config_logic_dat_out, DIR = O
|
---|
53 | PORT clk_board_config_logic_csb_out = clk_board_config_logic_csb_out, DIR = O
|
---|
54 | PORT clk_board_config_logic_en_out = clk_board_config_logic_en_out, DIR = O
|
---|
55 | PORT clk_board_config_logic_clk_out = clk_board_config_logic_clk_out, DIR = O
|
---|
56 | # RFA transceiver and front-end (daughtercard slot 2)
|
---|
57 | PORT RFA_TxEn = RFA_TxEn, DIR = O
|
---|
58 | PORT RFA_RxEn = RFA_RxEn, DIR = O
|
---|
59 | PORT RFA_RxHP = RFA_RxHP, DIR = O
|
---|
60 | PORT RFA_SHDN = RFA_SHDN, DIR = O
|
---|
61 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK, DIR = O
|
---|
62 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI, DIR = O
|
---|
63 | PORT RFA_SPI_CSn = RFA_SPI_CSn, DIR = O
|
---|
64 | PORT RFA_B = RFA_B, DIR = O, VEC = [0:6]
|
---|
65 | PORT RFA_LD = RFA_LD, DIR = I
|
---|
66 | PORT RFA_PAEn_24 = RFA_PAEn_24, DIR = O
|
---|
67 | PORT RFA_PAEn_5 = RFA_PAEn_5, DIR = O
|
---|
68 | PORT RFA_AntSw = RFA_AntSw, DIR = O, VEC = [0:1]
|
---|
69 | # R G Y
|
---|
70 | PORT RFA_LEDs = 0b0 & RFA_statLED_Tx & RFA_statLED_Rx, DIR = O, VEC = [0:2]
|
---|
71 | PORT RFA_DIPSW = RFA_DIPSW, DIR = I, VEC = [0:3]
|
---|
72 | # RFB transceiver and front-end (daughtercard slot 3)
|
---|
73 | PORT RFB_TxEn = RFB_TxEn, DIR = O
|
---|
74 | PORT RFB_RxEn = RFB_RxEn, DIR = O
|
---|
75 | PORT RFB_RxHP = RFB_RxHP, DIR = O
|
---|
76 | PORT RFB_SHDN = RFB_SHDN, DIR = O
|
---|
77 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK, DIR = O
|
---|
78 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI, DIR = O
|
---|
79 | PORT RFB_SPI_CSn = RFB_SPI_CSn, DIR = O
|
---|
80 | PORT RFB_B = RFB_B, DIR = O, VEC = [0:6]
|
---|
81 | PORT RFB_LD = RFB_LD, DIR = I
|
---|
82 | PORT RFB_PAEn_24 = RFB_PAEn_24, DIR = O
|
---|
83 | PORT RFB_PAEn_5 = RFB_PAEn_5, DIR = O
|
---|
84 | PORT RFB_AntSw = RFB_AntSw, DIR = O, VEC = [0:1]
|
---|
85 | PORT RFB_LEDs = 0b0 & RFB_statLED_Tx & RFB_statLED_Rx, DIR = O, VEC = [0:2]
|
---|
86 | PORT RFB_DIPSW = RFB_DIPSW, DIR = I, VEC = [0:3]
|
---|
87 | # RSSI ADCs
|
---|
88 | PORT RFA_RSSI_ADC_D = RFA_RSSI_ADC_D, DIR = I, VEC = [9:0]
|
---|
89 | PORT RFA_RSSI_ADC_CLK = RFA_RSSI_ADC_CLK, DIR = O
|
---|
90 | PORT RFA_RSSI_ADC_CLAMP = RFA_RSSI_ADC_CLAMP, DIR = O
|
---|
91 | PORT RFA_RSSI_ADC_HIZ = RFA_RSSI_ADC_HIZ, DIR = O
|
---|
92 | PORT RFA_RSSI_ADC_SLEEP = RFA_RSSI_ADC_SLEEP, DIR = O
|
---|
93 | PORT RFB_RSSI_ADC_D = RFB_RSSI_ADC_D, DIR = I, VEC = [9:0]
|
---|
94 | PORT RFB_RSSI_ADC_CLK = RFB_RSSI_ADC_CLK, DIR = O
|
---|
95 | PORT RFB_RSSI_ADC_CLAMP = RFB_RSSI_ADC_CLAMP, DIR = O
|
---|
96 | PORT RFB_RSSI_ADC_HIZ = RFB_RSSI_ADC_HIZ, DIR = O
|
---|
97 | PORT RFB_RSSI_ADC_SLEEP = RFB_RSSI_ADC_SLEEP, DIR = O
|
---|
98 | # I/Q ADCs/DACs
|
---|
99 | PORT RFA_DAC_I = RFA_DAC_I, DIR = O, VEC = [15:0]
|
---|
100 | PORT RFA_DAC_Q = RFA_DAC_Q, DIR = O, VEC = [15:0]
|
---|
101 | PORT RFA_DAC_SPI_CSn = RFA_DAC_SPI_CSn, DIR = O
|
---|
102 | PORT RFA_DAC_SPI_SCLK = RFA_DAC_SPI_SCLK, DIR = O
|
---|
103 | PORT RFA_DAC_SPI_MOSI = RFA_DAC_SPI_MOSI, DIR = O
|
---|
104 | PORT RFA_DAC_SPI_MISO = RFA_DAC_SPI_MISO, DIR = I
|
---|
105 | PORT RFA_DAC_RESET = RFA_DAC_RESET, DIR = O
|
---|
106 | PORT RFA_DAC_PLLLOCK = RFA_DAC_PLLLOCK, DIR = I
|
---|
107 | PORT RFA_RX_ADC_I = RFA_RX_ADC_I, DIR = I, VEC = [13:0]
|
---|
108 | PORT RFA_RX_ADC_Q = RFA_RX_ADC_Q, DIR = I, VEC = [13:0]
|
---|
109 | PORT RFA_RX_ADC_I_OTR = RFA_RX_ADC_I_OTR, DIR = I
|
---|
110 | PORT RFA_RX_ADC_Q_OTR = RFA_RX_ADC_Q_OTR, DIR = I
|
---|
111 | PORT RFA_RX_ADC_DCS = RFA_RX_ADC_DCS, DIR = O
|
---|
112 | PORT RFA_RX_ADC_DFS = RFA_RX_ADC_DFS, DIR = O
|
---|
113 | PORT RFA_RX_ADC_I_PWDN = RFA_RX_ADC_PWDN, DIR = O
|
---|
114 | PORT RFA_RX_ADC_Q_PWDN = RFA_RX_ADC_PWDN, DIR = O
|
---|
115 | PORT RFB_DAC_I = RFB_DAC_I, DIR = O, VEC = [15:0]
|
---|
116 | PORT RFB_DAC_Q = RFB_DAC_Q, DIR = O, VEC = [15:0]
|
---|
117 | PORT RFB_DAC_SPI_CSn = RFB_DAC_SPI_CSn, DIR = O
|
---|
118 | PORT RFB_DAC_SPI_SCLK = RFB_DAC_SPI_SCLK, DIR = O
|
---|
119 | PORT RFB_DAC_SPI_MOSI = RFB_DAC_SPI_MOSI, DIR = O
|
---|
120 | PORT RFB_DAC_SPI_MISO = RFB_DAC_SPI_MISO, DIR = I
|
---|
121 | PORT RFB_DAC_RESET = RFB_DAC_RESET, DIR = O
|
---|
122 | PORT RFB_DAC_PLLLOCK = RFB_DAC_PLLLOCK, DIR = I
|
---|
123 | PORT RFB_RX_ADC_I = RFB_RX_ADC_I, DIR = I, VEC = [13:0]
|
---|
124 | PORT RFB_RX_ADC_Q = RFB_RX_ADC_Q, DIR = I, VEC = [13:0]
|
---|
125 | PORT RFB_RX_ADC_I_OTR = RFB_RX_ADC_I_OTR, DIR = I
|
---|
126 | PORT RFB_RX_ADC_Q_OTR = RFB_RX_ADC_Q_OTR, DIR = I
|
---|
127 | PORT RFB_RX_ADC_DCS = RFB_RX_ADC_DCS, DIR = O
|
---|
128 | PORT RFB_RX_ADC_DFS = RFB_RX_ADC_DFS, DIR = O
|
---|
129 | PORT RFB_RX_ADC_I_PWDN = RFB_RX_ADC_PWDN, DIR = O
|
---|
130 | PORT RFB_RX_ADC_Q_PWDN = RFB_RX_ADC_PWDN, DIR = O
|
---|
131 | # EEPROM I/O
|
---|
132 | PORT RFA_EEPROM_IO = RFA_EEPROM_IO, DIR = IO
|
---|
133 | PORT RFB_EEPROM_IO = RFB_EEPROM_IO, DIR = IO
|
---|
134 | PORT FPGA_EEPROM_IO = FPGA_EEPROM_IO, DIR = IO
|
---|
135 | # Clock & Reset
|
---|
136 | PORT clk_1_sys_clk = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000
|
---|
137 | PORT rst_1_sys_rst = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
|
---|
138 | # Digital I/O header
|
---|
139 | PORT debughdr = debug_capture_running & debug_transmit_running, DIR = O, VEC = [1:0]
|
---|
140 | PORT debug_sw_gpio = debug_sw_gpio, DIR = IO, VEC = [1:0]
|
---|
141 | PORT trigger_in = trig_0_in & trig_1_in & trig_2_in & trig_3_in, DIR = I, VEC = [0:3]
|
---|
142 | PORT trigger_0_out = trig_2_0_out & trig_3_0_out & trig_4_0_out & trig_5_0_out, DIR = O, VEC = [0:3]
|
---|
143 | PORT trigger_1_out = trig_2_1_out & trig_3_1_out & trig_4_1_out & trig_5_1_out, DIR = O, VEC = [0:3]
|
---|
144 |
|
---|
145 |
|
---|
146 | # Optional Debug Header functionality
|
---|
147 | # To switch to 6 SW GPIO pins on the Debug Header:
|
---|
148 | # - Change above debug_sw_gpio line to:
|
---|
149 | # PORT debug_sw_gpio = debug_sw_gpio, DIR = IO, VEC = [5:0]
|
---|
150 | # - Modify the xps_gpio instance and change C_GPIO_WIDTH to 6 GPIOs
|
---|
151 | # - Comment out trigger_1_out
|
---|
152 | # - Modify the system.ucf file to use the debug_sw_gpio pins instead of the trigger_1_out pins
|
---|
153 | # ##############################################################################
|
---|
154 | # Processor
|
---|
155 | # ##############################################################################
|
---|
156 | BEGIN ppc405_virtex4
|
---|
157 | PARAMETER INSTANCE = ppc405_0
|
---|
158 | PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
|
---|
159 | PARAMETER C_IDCR_BASEADDR = 0b0100000000
|
---|
160 | PARAMETER C_IDCR_HIGHADDR = 0b0111111111
|
---|
161 | PARAMETER HW_VER = 2.01.b
|
---|
162 | BUS_INTERFACE DPLB0 = plb
|
---|
163 | BUS_INTERFACE IPLB0 = plb
|
---|
164 | BUS_INTERFACE DSOCM = ppc405_0_docm
|
---|
165 | BUS_INTERFACE ISOCM = ppc405_0_iocm
|
---|
166 | BUS_INTERFACE JTAGPPC = ppc405_0_jtagppc_bus
|
---|
167 | BUS_INTERFACE RESETPPC = ppc_reset_bus
|
---|
168 | PORT CPMC405CLOCK = clk_160_0000MHzDCM0
|
---|
169 | END
|
---|
170 |
|
---|
171 | BEGIN isocm_v10
|
---|
172 | PARAMETER INSTANCE = ppc405_0_iocm
|
---|
173 | PARAMETER C_ISCNTLVALUE = 0xa3
|
---|
174 | PARAMETER HW_VER = 2.00.b
|
---|
175 | PORT ISOCM_Clk = clk_80_0000MHzDCM0
|
---|
176 | PORT SYS_Rst = sys_bus_reset
|
---|
177 | END
|
---|
178 |
|
---|
179 | BEGIN isbram_if_cntlr
|
---|
180 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr
|
---|
181 | PARAMETER HW_VER = 3.00.c
|
---|
182 | PARAMETER C_BASEADDR = 0xffff0000
|
---|
183 | PARAMETER C_HIGHADDR = 0xffffffff
|
---|
184 | BUS_INTERFACE ISOCM = ppc405_0_iocm
|
---|
185 | BUS_INTERFACE DCR_WRITE_PORT = ppc405_0_iocm_cntlr_porta
|
---|
186 | BUS_INTERFACE INSTRN_READ_PORT = ppc405_0_iocm_cntlr_portb
|
---|
187 | END
|
---|
188 |
|
---|
189 | BEGIN bram_block
|
---|
190 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr_bram
|
---|
191 | PARAMETER HW_VER = 1.00.a
|
---|
192 | BUS_INTERFACE PORTA = ppc405_0_iocm_cntlr_porta
|
---|
193 | BUS_INTERFACE PORTB = ppc405_0_iocm_cntlr_portb
|
---|
194 | END
|
---|
195 |
|
---|
196 | BEGIN dsocm_v10
|
---|
197 | PARAMETER INSTANCE = ppc405_0_docm
|
---|
198 | PARAMETER C_DSCNTLVALUE = 0xa3
|
---|
199 | PARAMETER HW_VER = 2.00.b
|
---|
200 | PORT DSOCM_Clk = clk_80_0000MHzDCM0
|
---|
201 | PORT SYS_Rst = sys_bus_reset
|
---|
202 | END
|
---|
203 |
|
---|
204 | BEGIN dsbram_if_cntlr
|
---|
205 | PARAMETER INSTANCE = ppc405_0_docm_cntlr
|
---|
206 | PARAMETER HW_VER = 3.00.c
|
---|
207 | PARAMETER C_BASEADDR = 0x40110000
|
---|
208 | PARAMETER C_HIGHADDR = 0x4011ffff
|
---|
209 | BUS_INTERFACE DSOCM = ppc405_0_docm
|
---|
210 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
|
---|
211 | END
|
---|
212 |
|
---|
213 | BEGIN bram_block
|
---|
214 | PARAMETER INSTANCE = ppc405_0_docm_cntlr_bram
|
---|
215 | PARAMETER HW_VER = 1.00.a
|
---|
216 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
|
---|
217 | END
|
---|
218 |
|
---|
219 | # ##############################################################################
|
---|
220 | # Clock / Reset / Debug
|
---|
221 | # ##############################################################################
|
---|
222 | BEGIN clock_generator
|
---|
223 | PARAMETER INSTANCE = clock_generator_0
|
---|
224 | PARAMETER C_CLKIN_FREQ = 40000000
|
---|
225 | PARAMETER C_CLKOUT0_FREQ = 125000000
|
---|
226 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
227 | PARAMETER C_CLKOUT0_GROUP = NONE
|
---|
228 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
229 | PARAMETER C_CLKOUT1_FREQ = 160000000
|
---|
230 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
231 | PARAMETER C_CLKOUT1_GROUP = DCM0
|
---|
232 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
233 | PARAMETER C_CLKOUT2_FREQ = 200000000
|
---|
234 | PARAMETER C_CLKOUT2_PHASE = 0
|
---|
235 | PARAMETER C_CLKOUT2_GROUP = NONE
|
---|
236 | PARAMETER C_CLKOUT2_BUF = TRUE
|
---|
237 | PARAMETER C_CLKOUT3_FREQ = 40000000
|
---|
238 | PARAMETER C_CLKOUT3_PHASE = 0
|
---|
239 | PARAMETER C_CLKOUT3_GROUP = NONE
|
---|
240 | PARAMETER C_CLKOUT3_BUF = TRUE
|
---|
241 | PARAMETER C_CLKOUT4_FREQ = 80000000
|
---|
242 | PARAMETER C_CLKOUT4_PHASE = 0
|
---|
243 | PARAMETER C_CLKOUT4_GROUP = DCM0
|
---|
244 | PARAMETER C_CLKOUT4_BUF = TRUE
|
---|
245 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
246 | PARAMETER HW_VER = 4.03.a
|
---|
247 | PORT CLKIN = CLK_S
|
---|
248 | PORT CLKOUT0 = clk_125_0000MHz
|
---|
249 | PORT CLKOUT1 = clk_160_0000MHzDCM0
|
---|
250 | PORT CLKOUT2 = clk_200_0000MHz
|
---|
251 | PORT CLKOUT3 = clk_40_0000MHz
|
---|
252 | PORT CLKOUT4 = clk_80_0000MHzDCM0
|
---|
253 | PORT RST = clk_board_config_config_invalid
|
---|
254 | PORT LOCKED = Dcm_all_locked
|
---|
255 | END
|
---|
256 |
|
---|
257 | BEGIN jtagppc_cntlr
|
---|
258 | PARAMETER INSTANCE = jtagppc_cntlr_inst
|
---|
259 | PARAMETER HW_VER = 2.01.c
|
---|
260 | BUS_INTERFACE JTAGPPC0 = ppc405_0_jtagppc_bus
|
---|
261 | END
|
---|
262 |
|
---|
263 | BEGIN proc_sys_reset
|
---|
264 | PARAMETER INSTANCE = proc_sys_reset_0
|
---|
265 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
266 | PARAMETER HW_VER = 3.00.a
|
---|
267 | BUS_INTERFACE RESETPPC0 = ppc_reset_bus
|
---|
268 | PORT Slowest_sync_clk = clk_40_0000MHz
|
---|
269 | PORT Ext_Reset_In = sys_rst_s
|
---|
270 | PORT Dcm_locked = Dcm_all_locked
|
---|
271 | PORT Bus_Struct_Reset = sys_bus_reset
|
---|
272 | PORT Peripheral_Reset = sys_periph_reset
|
---|
273 | END
|
---|
274 |
|
---|
275 | # ##############################################################################
|
---|
276 | # Interconnect
|
---|
277 | # ##############################################################################
|
---|
278 | BEGIN plb_v46
|
---|
279 | PARAMETER INSTANCE = plb
|
---|
280 | PARAMETER C_DCR_INTFCE = 0
|
---|
281 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
|
---|
282 | PARAMETER HW_VER = 1.05.a
|
---|
283 | PORT PLB_Clk = clk_80_0000MHzDCM0
|
---|
284 | PORT SYS_Rst = sys_bus_reset
|
---|
285 | END
|
---|
286 |
|
---|
287 | # ##############################################################################
|
---|
288 | # Peripherals
|
---|
289 | # ##############################################################################
|
---|
290 | BEGIN xps_central_dma
|
---|
291 | PARAMETER INSTANCE = xps_central_dma_0
|
---|
292 | PARAMETER HW_VER = 2.03.a
|
---|
293 | PARAMETER C_BASEADDR = 0x81000000
|
---|
294 | PARAMETER C_HIGHADDR = 0x8100FFFF
|
---|
295 | BUS_INTERFACE MPLB = plb
|
---|
296 | BUS_INTERFACE SPLB = plb
|
---|
297 | END
|
---|
298 |
|
---|
299 | BEGIN xps_timer
|
---|
300 | PARAMETER INSTANCE = xps_timer_0
|
---|
301 | PARAMETER HW_VER = 1.02.a
|
---|
302 | PARAMETER C_BASEADDR = 0x80100000
|
---|
303 | PARAMETER C_HIGHADDR = 0x8010FFFF
|
---|
304 | BUS_INTERFACE SPLB = plb
|
---|
305 | END
|
---|
306 |
|
---|
307 | BEGIN xps_gpio
|
---|
308 | PARAMETER INSTANCE = xps_gpio_0
|
---|
309 | PARAMETER HW_VER = 2.00.a
|
---|
310 | # PARAMETER C_GPIO_WIDTH = 6
|
---|
311 | PARAMETER C_GPIO_WIDTH = 2
|
---|
312 | PARAMETER C_BASEADDR = 0x80000000
|
---|
313 | PARAMETER C_HIGHADDR = 0x8000FFFF
|
---|
314 | BUS_INTERFACE SPLB = plb
|
---|
315 | PORT GPIO_IO_O = debug_sw_gpio
|
---|
316 | END
|
---|
317 |
|
---|
318 | BEGIN xps_uartlite
|
---|
319 | PARAMETER INSTANCE = rs232_db9
|
---|
320 | PARAMETER C_BAUDRATE = 57600
|
---|
321 | PARAMETER C_DATA_BITS = 8
|
---|
322 | PARAMETER C_USE_PARITY = 0
|
---|
323 | PARAMETER C_ODD_PARITY = 0
|
---|
324 | PARAMETER HW_VER = 1.02.a
|
---|
325 | PARAMETER C_BASEADDR = 0x80300000
|
---|
326 | PARAMETER C_HIGHADDR = 0x8030FFFF
|
---|
327 | BUS_INTERFACE SPLB = plb
|
---|
328 | PORT RX = rs232_db9_RX
|
---|
329 | PORT TX = rs232_db9_TX
|
---|
330 | END
|
---|
331 |
|
---|
332 | BEGIN xps_uartlite
|
---|
333 | PARAMETER INSTANCE = rs232_usb
|
---|
334 | PARAMETER C_BAUDRATE = 57600
|
---|
335 | PARAMETER C_DATA_BITS = 8
|
---|
336 | PARAMETER C_USE_PARITY = 0
|
---|
337 | PARAMETER C_ODD_PARITY = 0
|
---|
338 | PARAMETER HW_VER = 1.02.a
|
---|
339 | PARAMETER C_BASEADDR = 0x80200000
|
---|
340 | PARAMETER C_HIGHADDR = 0x8020FFFF
|
---|
341 | BUS_INTERFACE SPLB = plb
|
---|
342 | PORT RX = rs232_usb_RX
|
---|
343 | PORT TX = rs232_usb_TX
|
---|
344 | END
|
---|
345 |
|
---|
346 | BEGIN xps_bram_if_cntlr
|
---|
347 | PARAMETER INSTANCE = xps_bram_if_cntlr_1
|
---|
348 | PARAMETER C_SPLB_NATIVE_DWIDTH = 64
|
---|
349 | PARAMETER HW_VER = 1.00.b
|
---|
350 | PARAMETER C_BASEADDR = 0x00000000
|
---|
351 | PARAMETER C_HIGHADDR = 0x0000ffff
|
---|
352 | BUS_INTERFACE SPLB = plb
|
---|
353 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
---|
354 | END
|
---|
355 |
|
---|
356 | BEGIN bram_block
|
---|
357 | PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
|
---|
358 | PARAMETER HW_VER = 1.00.a
|
---|
359 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
---|
360 | END
|
---|
361 |
|
---|
362 | # ##############################################################################
|
---|
363 | # Ethernet
|
---|
364 | # ##############################################################################
|
---|
365 | BEGIN xps_ll_temac
|
---|
366 | PARAMETER INSTANCE = ETH_A_MAC
|
---|
367 | PARAMETER C_NUM_IDELAYCTRL = 2
|
---|
368 | PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y6
|
---|
369 | PARAMETER C_PHY_TYPE = 1
|
---|
370 | PARAMETER C_BUS2CORE_CLK_RATIO = 1
|
---|
371 | PARAMETER C_TEMAC_TYPE = 1
|
---|
372 | PARAMETER HW_VER = 2.03.a
|
---|
373 | PARAMETER C_BASEADDR = 0x82100000
|
---|
374 | PARAMETER C_HIGHADDR = 0x8217FFFF
|
---|
375 | PARAMETER C_TEMAC0_TXFIFO = 2048
|
---|
376 | PARAMETER C_TEMAC0_RXFIFO = 2048
|
---|
377 | PARAMETER C_TEMAC0_TXCSUM = 0
|
---|
378 | PARAMETER C_TEMAC0_RXCSUM = 0
|
---|
379 | BUS_INTERFACE SPLB = plb
|
---|
380 | BUS_INTERFACE LLINK0 = ETH_llink0
|
---|
381 | PORT TemacPhy_RST_n = ETH_TemacPhy_RST_n
|
---|
382 | PORT GTX_CLK_0 = clk_125_0000MHz
|
---|
383 | PORT REFCLK = clk_200_0000MHz
|
---|
384 | PORT LlinkTemac0_CLK = clk_80_0000MHzDCM0
|
---|
385 | PORT MII_TX_CLK_0 = ETH_MII_TX_CLK
|
---|
386 | PORT GMII_TXD_0 = ETH_GMII_TXD
|
---|
387 | PORT GMII_TX_EN_0 = ETH_GMII_TX_EN
|
---|
388 | PORT GMII_TX_ER_0 = ETH_GMII_TX_ER
|
---|
389 | PORT GMII_TX_CLK_0 = ETH_GMII_TX_CLK
|
---|
390 | PORT GMII_RXD_0 = ETH_GMII_RXD
|
---|
391 | PORT GMII_RX_DV_0 = ETH_GMII_RX_DV
|
---|
392 | PORT GMII_RX_ER_0 = ETH_GMII_RX_ER
|
---|
393 | PORT GMII_RX_CLK_0 = ETH_GMII_RX_CLK
|
---|
394 | PORT MDC_0 = ETH_MDC
|
---|
395 | PORT MDIO_0 = ETH_MDIO
|
---|
396 | END
|
---|
397 |
|
---|
398 | BEGIN xps_ll_fifo
|
---|
399 | PARAMETER INSTANCE = ETH_A_FIFO
|
---|
400 | PARAMETER HW_VER = 1.02.a
|
---|
401 | PARAMETER C_BASEADDR = 0x82000000
|
---|
402 | PARAMETER C_HIGHADDR = 0x8200FFFF
|
---|
403 | BUS_INTERFACE SPLB = plb
|
---|
404 | BUS_INTERFACE LLINK = ETH_llink0
|
---|
405 | END
|
---|
406 |
|
---|
407 | # ##############################################################################
|
---|
408 | # Mango Cores
|
---|
409 | # ##############################################################################
|
---|
410 | BEGIN warp_v4_userio
|
---|
411 | PARAMETER INSTANCE = UserIO
|
---|
412 | PARAMETER C_ADDRESS_0 = 0x40
|
---|
413 | PARAMETER C_ADDRESS_1 = 0x42
|
---|
414 | PARAMETER C_I2C_DIVIDER = 0x40
|
---|
415 | PARAMETER HW_VER = 1.00.a
|
---|
416 | PARAMETER C_BASEADDR = 0x80500000
|
---|
417 | PARAMETER C_HIGHADDR = 0x8050FFFF
|
---|
418 | BUS_INTERFACE SPLB = plb
|
---|
419 | PORT LEDs_out = UserIO_LEDs
|
---|
420 | PORT IOEx_SDA = UserIO_IOEx_SDA
|
---|
421 | PORT IOEx_SCL = UserIO_IOEx_SCL
|
---|
422 | PORT PB_in = UserIO_PB
|
---|
423 | PORT DIPSW_in = UserIO_DIPSW
|
---|
424 | END
|
---|
425 |
|
---|
426 | BEGIN clock_board_config
|
---|
427 | PARAMETER INSTANCE = clk_board_config
|
---|
428 | PARAMETER HW_VER = 1.05.a
|
---|
429 | PARAMETER radio_clk_out4_mode = 0x1eff
|
---|
430 | PARAMETER radio_clk_out7_mode = 0x1eff
|
---|
431 | PARAMETER logic_clk_out0_mode = 0x08ff
|
---|
432 | PARAMETER logic_clk_out1_mode = 0x08ff
|
---|
433 | PARAMETER radio_clk_source_sel_mode = 1
|
---|
434 | PARAMETER logic_clk_source_sel_mode = 1
|
---|
435 | PARAMETER fpga_radio_clk_source = 1
|
---|
436 | PARAMETER fpga_logic_clk_source = 1
|
---|
437 | PARAMETER radio_clk_forward_out_mode = 0x08FF
|
---|
438 | PARAMETER logic_clk_forward_out_mode = 0x1EFF
|
---|
439 | PORT sys_clk = clk_board_config_sys_clk
|
---|
440 | PORT sys_rst = net_gnd
|
---|
441 | PORT cfg_radio_dat_out = clk_board_config_radio_dat_out
|
---|
442 | PORT cfg_radio_csb_out = clk_board_config_radio_csb_out
|
---|
443 | PORT cfg_radio_en_out = clk_board_config_radio_en_out
|
---|
444 | PORT cfg_radio_clk_out = clk_board_config_radio_clk_out
|
---|
445 | PORT cfg_logic_dat_out = clk_board_config_logic_dat_out
|
---|
446 | PORT cfg_logic_csb_out = clk_board_config_logic_csb_out
|
---|
447 | PORT cfg_logic_en_out = clk_board_config_logic_en_out
|
---|
448 | PORT cfg_logic_clk_out = clk_board_config_logic_clk_out
|
---|
449 | PORT radio_clk_src_sel = radio2_dipsw_zero
|
---|
450 | PORT logic_clk_src_sel = radio2_dipsw_one
|
---|
451 | PORT config_invalid = clk_board_config_config_invalid
|
---|
452 | END
|
---|
453 |
|
---|
454 | BEGIN util_bus_split
|
---|
455 | PARAMETER INSTANCE = util_bus_split_0
|
---|
456 | PARAMETER HW_VER = 1.00.a
|
---|
457 | PARAMETER C_SIZE_IN = 4
|
---|
458 | PARAMETER C_SPLIT = 2
|
---|
459 | PORT Sig = RFA_DIPSW
|
---|
460 | PORT Out1 = radio2_dipsw_zero & radio2_dipsw_one
|
---|
461 | END
|
---|
462 |
|
---|
463 | BEGIN eeprom_onewire
|
---|
464 | PARAMETER INSTANCE = eeprom_controller
|
---|
465 | PARAMETER HW_VER = 1.10.a
|
---|
466 | PARAMETER C_MEM0_BASEADDR = 0x80400000
|
---|
467 | PARAMETER C_MEM0_HIGHADDR = 0x8040FFFF
|
---|
468 | BUS_INTERFACE SPLB = plb
|
---|
469 | PORT DQ0 = FPGA_EEPROM_IO
|
---|
470 | PORT DQ1 = RFA_EEPROM_IO
|
---|
471 | PORT DQ2 = RFB_EEPROM_IO
|
---|
472 | PORT DQ5_I = net_vcc
|
---|
473 | PORT DQ6_I = net_vcc
|
---|
474 | PORT DQ7_I = net_vcc
|
---|
475 | END
|
---|
476 |
|
---|
477 | BEGIN radio_controller
|
---|
478 | PARAMETER INSTANCE = radio_controller_0
|
---|
479 | PARAMETER HW_VER = 2.00.a
|
---|
480 | PARAMETER C_BASEADDR = 0x85000000
|
---|
481 | PARAMETER C_HIGHADDR = 0x8500FFFF
|
---|
482 | BUS_INTERFACE SPLB = plb
|
---|
483 | # RFA
|
---|
484 | PORT RFA_TxEn = RFA_TxEn
|
---|
485 | PORT RFA_RxEn = RFA_RxEn
|
---|
486 | PORT RFA_RxHP = RFA_RxHP
|
---|
487 | PORT RFA_SHDN = RFA_SHDN
|
---|
488 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK
|
---|
489 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI
|
---|
490 | PORT RFA_SPI_CSn = RFA_SPI_CSn
|
---|
491 | PORT RFA_B = RFA_B
|
---|
492 | PORT RFA_LD = RFA_LD
|
---|
493 | PORT RFA_PAEn_24 = RFA_PAEn_24
|
---|
494 | PORT RFA_PAEn_5 = RFA_PAEn_5
|
---|
495 | PORT RFA_AntSw = RFA_AntSw
|
---|
496 | PORT RFA_DIPSW = RFA_DIPSW
|
---|
497 | PORT RFA_RSSI_ADC_CLAMP = RFA_RSSI_ADC_CLAMP
|
---|
498 | PORT RFA_RSSI_ADC_HIZ = RFA_RSSI_ADC_HIZ
|
---|
499 | PORT RFA_RSSI_ADC_SLEEP = RFA_RSSI_ADC_SLEEP
|
---|
500 | PORT RFA_DAC_SPI_CSn = RFA_DAC_SPI_CSn
|
---|
501 | PORT RFA_DAC_SPI_SCLK = RFA_DAC_SPI_SCLK
|
---|
502 | PORT RFA_DAC_SPI_MOSI = RFA_DAC_SPI_MOSI
|
---|
503 | PORT RFA_DAC_SPI_MISO = RFA_DAC_SPI_MISO
|
---|
504 | PORT RFA_DAC_RESET = RFA_DAC_RESET
|
---|
505 | PORT RFA_DAC_PLLLOCK = RFA_DAC_PLLLOCK
|
---|
506 | PORT RFA_RX_ADC_DCS = RFA_RX_ADC_DCS
|
---|
507 | PORT RFA_RX_ADC_DFS = RFA_RX_ADC_DFS
|
---|
508 | PORT RFA_RX_ADC_PWDN = RFA_RX_ADC_PWDN
|
---|
509 | # RFA - User ports
|
---|
510 | PORT usr_RFA_statLED_Tx = RFA_statLED_Tx
|
---|
511 | PORT usr_RFA_statLED_Rx = RFA_statLED_Rx
|
---|
512 | PORT usr_RFA_RxHP = agc_rxhp_a
|
---|
513 | PORT usr_RFA_RxGainRF = agc_g_rf_a
|
---|
514 | PORT usr_RFA_RxGainBB = agc_g_bb_a
|
---|
515 | # RFB
|
---|
516 | PORT RFB_TxEn = RFB_TxEn
|
---|
517 | PORT RFB_RxEn = RFB_RxEn
|
---|
518 | PORT RFB_RxHP = RFB_RxHP
|
---|
519 | PORT RFB_SHDN = RFB_SHDN
|
---|
520 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK
|
---|
521 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI
|
---|
522 | PORT RFB_SPI_CSn = RFB_SPI_CSn
|
---|
523 | PORT RFB_B = RFB_B
|
---|
524 | PORT RFB_LD = RFB_LD
|
---|
525 | PORT RFB_PAEn_24 = RFB_PAEn_24
|
---|
526 | PORT RFB_PAEn_5 = RFB_PAEn_5
|
---|
527 | PORT RFB_AntSw = RFB_AntSw
|
---|
528 | PORT RFB_DIPSW = RFB_DIPSW
|
---|
529 | PORT RFB_RSSI_ADC_CLAMP = RFB_RSSI_ADC_CLAMP
|
---|
530 | PORT RFB_RSSI_ADC_HIZ = RFB_RSSI_ADC_HIZ
|
---|
531 | PORT RFB_RSSI_ADC_SLEEP = RFB_RSSI_ADC_SLEEP
|
---|
532 | PORT RFB_DAC_SPI_CSn = RFB_DAC_SPI_CSn
|
---|
533 | PORT RFB_DAC_SPI_SCLK = RFB_DAC_SPI_SCLK
|
---|
534 | PORT RFB_DAC_SPI_MOSI = RFB_DAC_SPI_MOSI
|
---|
535 | PORT RFB_DAC_SPI_MISO = RFB_DAC_SPI_MISO
|
---|
536 | PORT RFB_DAC_RESET = RFB_DAC_RESET
|
---|
537 | PORT RFB_DAC_PLLLOCK = RFB_DAC_PLLLOCK
|
---|
538 | PORT RFB_RX_ADC_DCS = RFB_RX_ADC_DCS
|
---|
539 | PORT RFB_RX_ADC_DFS = RFB_RX_ADC_DFS
|
---|
540 | PORT RFB_RX_ADC_PWDN = RFB_RX_ADC_PWDN
|
---|
541 | # RFB - User ports
|
---|
542 | PORT usr_RFB_statLED_Tx = RFB_statLED_Tx
|
---|
543 | PORT usr_RFB_statLED_Rx = RFB_statLED_Rx
|
---|
544 | PORT usr_RFB_RxHP = agc_rxhp_b
|
---|
545 | PORT usr_RFB_RxGainRF = agc_g_rf_b
|
---|
546 | PORT usr_RFB_RxGainBB = agc_g_bb_b
|
---|
547 | END
|
---|
548 |
|
---|
549 | BEGIN radio_bridge
|
---|
550 | PARAMETER INSTANCE = radio_bridge_RFA
|
---|
551 | PARAMETER HW_VER = 2.00.a
|
---|
552 | PORT samp_clock = clk_40_0000MHz
|
---|
553 | PORT radio_ADC_I = RFA_RX_ADC_I
|
---|
554 | PORT radio_ADC_Q = RFA_RX_ADC_Q
|
---|
555 | PORT radio_DAC_I = RFA_DAC_I
|
---|
556 | PORT radio_DAC_Q = RFA_DAC_Q
|
---|
557 | PORT radio_ADC_I_OTR = RFA_RX_ADC_I_OTR
|
---|
558 | PORT radio_ADC_Q_OTR = RFA_RX_ADC_Q_OTR
|
---|
559 | PORT user_ADC_I = warplab_rfa_Rx_I
|
---|
560 | PORT user_ADC_Q = warplab_rfa_Rx_Q
|
---|
561 | PORT user_DAC_I = warplab_rfa_Tx_I
|
---|
562 | PORT user_DAC_Q = warplab_rfa_Tx_Q
|
---|
563 | PORT radio_RSSI_ADC_D = RFA_RSSI_ADC_D
|
---|
564 | PORT radio_RSSI_ADC_CLK = RFA_RSSI_ADC_CLK
|
---|
565 | PORT user_RSSI_ADC_D = warplab_rfa_rssi
|
---|
566 | PORT user_RSSI_ADC_CLK = warplab_rssi_clk
|
---|
567 | END
|
---|
568 |
|
---|
569 | BEGIN radio_bridge
|
---|
570 | PARAMETER INSTANCE = radio_bridge_RFB
|
---|
571 | PARAMETER HW_VER = 2.00.a
|
---|
572 | PORT samp_clock = clk_40_0000MHz
|
---|
573 | PORT radio_ADC_I = RFB_RX_ADC_I
|
---|
574 | PORT radio_ADC_Q = RFB_RX_ADC_Q
|
---|
575 | PORT radio_DAC_I = RFB_DAC_I
|
---|
576 | PORT radio_DAC_Q = RFB_DAC_Q
|
---|
577 | PORT radio_ADC_I_OTR = RFB_RX_ADC_I_OTR
|
---|
578 | PORT radio_ADC_Q_OTR = RFB_RX_ADC_Q_OTR
|
---|
579 | PORT user_ADC_I = warplab_rfb_Rx_I
|
---|
580 | PORT user_ADC_Q = warplab_rfb_Rx_Q
|
---|
581 | PORT user_DAC_I = warplab_rfb_Tx_I
|
---|
582 | PORT user_DAC_Q = warplab_rfb_Tx_Q
|
---|
583 | PORT radio_RSSI_ADC_D = RFB_RSSI_ADC_D
|
---|
584 | PORT radio_RSSI_ADC_CLK = RFB_RSSI_ADC_CLK
|
---|
585 | PORT user_RSSI_ADC_D = warplab_rfb_rssi
|
---|
586 | PORT user_RSSI_ADC_CLK = warplab_rssi_clk
|
---|
587 | END
|
---|
588 |
|
---|
589 | # ##############################################################################
|
---|
590 | # Local Cores
|
---|
591 | # ##############################################################################
|
---|
592 | BEGIN w2_warplab_trigger_proc_plbw
|
---|
593 | PARAMETER INSTANCE = warplab_trigger_proc
|
---|
594 | PARAMETER HW_VER = 1.04.b
|
---|
595 | PARAMETER C_BASEADDR = 0x84000000
|
---|
596 | PARAMETER C_HIGHADDR = 0x8400FFFF
|
---|
597 | BUS_INTERFACE SPLB = plb
|
---|
598 | PORT sysgen_clk = clk_160_0000MHzDCM0
|
---|
599 | PORT agc_done_in = agc_is_done
|
---|
600 | PORT rfa_rssi = warplab_rfa_rssi
|
---|
601 | PORT rfb_rssi = warplab_rfb_rssi
|
---|
602 | PORT rssi_clk = warplab_rssi_clk
|
---|
603 | # Debug header trigger inputs
|
---|
604 | PORT debug_0_in = trig_0_in
|
---|
605 | PORT debug_1_in = trig_1_in
|
---|
606 | PORT debug_2_in = trig_2_in
|
---|
607 | PORT debug_3_in = trig_3_in
|
---|
608 | # Trigger outputs to internal modules
|
---|
609 | PORT trig_0_out = baseband_trigger
|
---|
610 | PORT trig_1_out = agc_start
|
---|
611 | # Trigger outputs to the debug header
|
---|
612 | PORT trig_2_0_out = trig_2_0_out
|
---|
613 | PORT trig_3_0_out = trig_3_0_out
|
---|
614 | PORT trig_4_0_out = trig_4_0_out
|
---|
615 | PORT trig_5_0_out = trig_5_0_out
|
---|
616 | # Replicated trigger outputs to the debug header
|
---|
617 | PORT trig_2_1_out = trig_2_1_out
|
---|
618 | PORT trig_3_1_out = trig_3_1_out
|
---|
619 | PORT trig_4_1_out = trig_4_1_out
|
---|
620 | PORT trig_5_1_out = trig_5_1_out
|
---|
621 | END
|
---|
622 |
|
---|
623 | BEGIN w2_warplab_buffers_plbw
|
---|
624 | PARAMETER INSTANCE = warplab_buffers
|
---|
625 | PARAMETER HW_VER = 3.01.c
|
---|
626 | PARAMETER C_BASEADDR = 0x83000000
|
---|
627 | PARAMETER C_HIGHADDR = 0x833FFFFF
|
---|
628 | BUS_INTERFACE SPLB = plb
|
---|
629 | PORT sysgen_clk = clk_40_0000MHz
|
---|
630 | PORT rssi_adc_clk = warplab_rssi_clk
|
---|
631 | PORT DESIGN_VER = 0x00070501
|
---|
632 | PORT agc_done = agc_is_done
|
---|
633 | # RFA
|
---|
634 | PORT rfa_dac_i = warplab_rfa_Tx_I
|
---|
635 | PORT rfa_dac_q = warplab_rfa_Tx_Q
|
---|
636 | PORT rfa_adc_i = warplab_rfa_Rx_I
|
---|
637 | PORT rfa_adc_q = warplab_rfa_Rx_Q
|
---|
638 | PORT rfa_agc_filt_i = dc_filtered_i_a
|
---|
639 | PORT rfa_agc_filt_q = dc_filtered_q_a
|
---|
640 | PORT rfa_rssi = warplab_rfa_rssi
|
---|
641 | PORT rfa_g_bb = agc_g_bb_a
|
---|
642 | PORT rfa_g_rf = agc_g_rf_a
|
---|
643 | PORT rfa_rxhp = agc_rxhp_a
|
---|
644 | # RFB
|
---|
645 | PORT rfb_dac_i = warplab_rfb_Tx_I
|
---|
646 | PORT rfb_dac_q = warplab_rfb_Tx_Q
|
---|
647 | PORT rfb_adc_i = warplab_rfb_Rx_I
|
---|
648 | PORT rfb_adc_q = warplab_rfb_Rx_Q
|
---|
649 | PORT rfb_agc_filt_i = dc_filtered_i_b
|
---|
650 | PORT rfb_agc_filt_q = dc_filtered_q_b
|
---|
651 | PORT rfb_rssi = warplab_rfb_rssi
|
---|
652 | PORT rfb_g_bb = agc_g_bb_b
|
---|
653 | PORT rfb_g_rf = agc_g_rf_b
|
---|
654 | PORT rfb_rxhp = agc_rxhp_b
|
---|
655 | # Other ports
|
---|
656 | PORT stoptx = net_gnd
|
---|
657 | PORT trigger_in = baseband_trigger
|
---|
658 | PORT capture_running = debug_capture_running
|
---|
659 | PORT transmit_running = debug_transmit_running
|
---|
660 | PORT dram_init_done = net_gnd
|
---|
661 | END
|
---|
662 |
|
---|
663 | BEGIN w2_warplab_agc_plbw
|
---|
664 | PARAMETER INSTANCE = warplab_agc
|
---|
665 | PARAMETER HW_VER = 3.00.b
|
---|
666 | PARAMETER C_BASEADDR = 0x84800000
|
---|
667 | PARAMETER C_HIGHADDR = 0x8480FFFF
|
---|
668 | BUS_INTERFACE SPLB = plb
|
---|
669 | PORT sysgen_clk = clk_80_0000MHzDCM0
|
---|
670 | PORT adc_rx_clk = clk_40_0000MHz
|
---|
671 | PORT agc_run = agc_start
|
---|
672 | PORT agc_done = agc_is_done
|
---|
673 | # RFA
|
---|
674 | PORT rfa_agc_rxhp = agc_rxhp_a
|
---|
675 | PORT rfa_agc_g_bb = agc_g_bb_a
|
---|
676 | PORT rfa_agc_g_rf = agc_g_rf_a
|
---|
677 | PORT rfa_rssi = warplab_rfa_rssi
|
---|
678 | PORT rfa_rx_i_in = warplab_rfa_Rx_I
|
---|
679 | PORT rfa_rx_q_in = warplab_rfa_Rx_Q
|
---|
680 | PORT rfa_rx_i_out = dc_filtered_i_a
|
---|
681 | PORT rfa_rx_q_out = dc_filtered_q_a
|
---|
682 | # RFB
|
---|
683 | PORT rfb_agc_rxhp = agc_rxhp_b
|
---|
684 | PORT rfb_agc_g_bb = agc_g_bb_b
|
---|
685 | PORT rfb_agc_g_rf = agc_g_rf_b
|
---|
686 | PORT rfb_rssi = warplab_rfb_rssi
|
---|
687 | PORT rfb_rx_i_in = warplab_rfb_Rx_I
|
---|
688 | PORT rfb_rx_q_in = warplab_rfb_Rx_Q
|
---|
689 | PORT rfb_rx_i_out = dc_filtered_i_b
|
---|
690 | PORT rfb_rx_q_out = dc_filtered_q_b
|
---|
691 | END
|
---|
692 |
|
---|