1 |
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2 | # ##############################################################################
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3 | # WARPLab Reference Design
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4 | # XPS Hardware Specification (system.mhs)
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5 | # Copyright 2013 Mango Communications
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6 | # Distributed under the WARP license (http://warpproject.org/license)
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7 | # Target Board: Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 2.2 / Radio 1.4 / Clock 1.1
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8 | # WARPLab version: 7.5.0
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9 | # Family: virtex4
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10 | # Device: XC4VFX100
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11 | # Package: FF1517
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12 | # Speed Grade: -11
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13 | # Processor number: 1
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14 | # Processor 1: ppc405_0
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15 | # Processor clock frequency: 160.0
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16 | # Bus clock frequency: 80.0
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17 | # Debug Interface: FPGA JTAG
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18 | # ##############################################################################
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19 | PARAMETER VERSION = 2.1.0
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20 |
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21 |
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22 | # ##############################################################################
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23 | # Top Level Ports
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24 | # ##############################################################################
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25 | PORT UserIO_LEDs = UserIO_LEDs, DIR = O, VEC = [0:7]
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26 | PORT UserIO_IOEx_SDA = UserIO_IOEx_SDA, DIR = O
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27 | PORT UserIO_IOEx_SCL = UserIO_IOEx_SCL, DIR = O
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28 | PORT UserIO_PB = UserIO_PB, DIR = I, VEC = [0:3]
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29 | PORT UserIO_DIPSW = UserIO_DIPSW, DIR = I, VEC = [0:3]
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30 | PORT rs232_db9_RX = rs232_db9_RX, DIR = I
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31 | PORT rs232_db9_TX = rs232_db9_TX, DIR = O
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32 | PORT rs232_usb_RX = rs232_usb_RX, DIR = I
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33 | PORT rs232_usb_TX = rs232_usb_TX, DIR = O
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34 | PORT ETH_TemacPhy_RST_n = ETH_TemacPhy_RST_n, DIR = O
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35 | PORT ETH_MII_TX_CLK = ETH_MII_TX_CLK, DIR = I
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36 | PORT ETH_GMII_TXD = ETH_GMII_TXD, DIR = O, VEC = [7:0]
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37 | PORT ETH_GMII_TX_EN = ETH_GMII_TX_EN, DIR = O
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38 | PORT ETH_GMII_TX_ER = ETH_GMII_TX_ER, DIR = O
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39 | PORT ETH_GMII_TX_CLK = ETH_GMII_TX_CLK, DIR = O
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40 | PORT ETH_GMII_RXD = ETH_GMII_RXD, DIR = I, VEC = [7:0]
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41 | PORT ETH_GMII_RX_DV = ETH_GMII_RX_DV, DIR = I
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42 | PORT ETH_GMII_RX_ER = ETH_GMII_RX_ER, DIR = I
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43 | PORT ETH_GMII_RX_CLK = ETH_GMII_RX_CLK, DIR = I
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44 | PORT ETH_MDC = ETH_MDC, DIR = O
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45 | PORT ETH_MDIO = ETH_MDIO, DIR = IO
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46 | # Clock board config
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47 | PORT clk_board_config_sys_clk = clk_board_config_sys_clk, DIR = I
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48 | PORT clk_board_config_radio_dat_out = clk_board_config_radio_dat_out, DIR = O
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49 | PORT clk_board_config_radio_csb_out = clk_board_config_radio_csb_out, DIR = O
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50 | PORT clk_board_config_radio_en_out = clk_board_config_radio_en_out, DIR = O
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51 | PORT clk_board_config_radio_clk_out = clk_board_config_radio_clk_out, DIR = O
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52 | PORT clk_board_config_logic_dat_out = clk_board_config_logic_dat_out, DIR = O
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53 | PORT clk_board_config_logic_csb_out = clk_board_config_logic_csb_out, DIR = O
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54 | PORT clk_board_config_logic_en_out = clk_board_config_logic_en_out, DIR = O
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55 | PORT clk_board_config_logic_clk_out = clk_board_config_logic_clk_out, DIR = O
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56 | # RFA transceiver and front-end (daughtercard slot 2)
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57 | PORT RFA_TxEn = RFA_TxEn, DIR = O
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58 | PORT RFA_RxEn = RFA_RxEn, DIR = O
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59 | PORT RFA_RxHP = RFA_RxHP, DIR = O
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60 | PORT RFA_SHDN = RFA_SHDN, DIR = O
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61 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK, DIR = O
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62 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI, DIR = O
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63 | PORT RFA_SPI_CSn = RFA_SPI_CSn, DIR = O
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64 | PORT RFA_B = RFA_B, DIR = O, VEC = [0:6]
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65 | PORT RFA_LD = RFA_LD, DIR = I
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66 | PORT RFA_PAEn_24 = RFA_PAEn_24, DIR = O
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67 | PORT RFA_PAEn_5 = RFA_PAEn_5, DIR = O
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68 | PORT RFA_AntSw = RFA_AntSw, DIR = O, VEC = [0:1]
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69 | # R G Y
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70 | PORT RFA_LEDs = 0b0 & RFA_statLED_Tx & RFA_statLED_Rx, DIR = O, VEC = [0:2]
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71 | PORT RFA_DIPSW = RFA_DIPSW, DIR = I, VEC = [0:3]
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72 | # RFB transceiver and front-end (daughtercard slot 3)
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73 | PORT RFB_TxEn = RFB_TxEn, DIR = O
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74 | PORT RFB_RxEn = RFB_RxEn, DIR = O
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75 | PORT RFB_RxHP = RFB_RxHP, DIR = O
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76 | PORT RFB_SHDN = RFB_SHDN, DIR = O
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77 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK, DIR = O
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78 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI, DIR = O
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79 | PORT RFB_SPI_CSn = RFB_SPI_CSn, DIR = O
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80 | PORT RFB_B = RFB_B, DIR = O, VEC = [0:6]
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81 | PORT RFB_LD = RFB_LD, DIR = I
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82 | PORT RFB_PAEn_24 = RFB_PAEn_24, DIR = O
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83 | PORT RFB_PAEn_5 = RFB_PAEn_5, DIR = O
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84 | PORT RFB_AntSw = RFB_AntSw, DIR = O, VEC = [0:1]
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85 | PORT RFB_LEDs = 0b0 & RFB_statLED_Tx & RFB_statLED_Rx, DIR = O, VEC = [0:2]
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86 | PORT RFB_DIPSW = RFB_DIPSW, DIR = I, VEC = [0:3]
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87 | # RFC transceiver and front-end (daughtercard slot 1)
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88 | PORT RFC_TxEn = RFC_TxEn, DIR = O
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89 | PORT RFC_RxEn = RFC_RxEn, DIR = O
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90 | PORT RFC_RxHP = RFC_RxHP, DIR = O
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91 | PORT RFC_SHDN = RFC_SHDN, DIR = O
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92 | PORT RFC_SPI_SCLK = RFC_SPI_SCLK, DIR = O
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93 | PORT RFC_SPI_MOSI = RFC_SPI_MOSI, DIR = O
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94 | PORT RFC_SPI_CSn = RFC_SPI_CSn, DIR = O
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95 | PORT RFC_B = RFC_B, DIR = O, VEC = [0:6]
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96 | PORT RFC_LD = RFC_LD, DIR = I
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97 | PORT RFC_PAEn_24 = RFC_PAEn_24, DIR = O
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98 | PORT RFC_PAEn_5 = RFC_PAEn_5, DIR = O
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99 | PORT RFC_AntSw = RFC_AntSw, DIR = O, VEC = [0:1]
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100 | PORT RFC_LEDs = 0b0 & RFC_statLED_Tx & RFC_statLED_Rx, DIR = O, VEC = [0:2]
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101 | PORT RFC_DIPSW = RFC_DIPSW, DIR = I, VEC = [0:3]
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102 | # RFD transceiver and front-end (daughtercard slot 4)
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103 | PORT RFD_TxEn = RFD_TxEn, DIR = O
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104 | PORT RFD_RxEn = RFD_RxEn, DIR = O
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105 | PORT RFD_RxHP = RFD_RxHP, DIR = O
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106 | PORT RFD_SHDN = RFD_SHDN, DIR = O
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107 | PORT RFD_SPI_SCLK = RFD_SPI_SCLK, DIR = O
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108 | PORT RFD_SPI_MOSI = RFD_SPI_MOSI, DIR = O
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109 | PORT RFD_SPI_CSn = RFD_SPI_CSn, DIR = O
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110 | PORT RFD_B = RFD_B, DIR = O, VEC = [0:6]
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111 | PORT RFD_LD = RFD_LD, DIR = I
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112 | PORT RFD_PAEn_24 = RFD_PAEn_24, DIR = O
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113 | PORT RFD_PAEn_5 = RFD_PAEn_5, DIR = O
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114 | PORT RFD_AntSw = RFD_AntSw, DIR = O, VEC = [0:1]
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115 | PORT RFD_LEDs = 0b0 & RFD_statLED_Tx & RFD_statLED_Rx, DIR = O, VEC = [0:2]
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116 | PORT RFD_DIPSW = RFD_DIPSW, DIR = I, VEC = [0:3]
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117 | # RSSI ADCs
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118 | PORT RFA_RSSI_ADC_D = RFA_RSSI_ADC_D, DIR = I, VEC = [9:0]
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119 | PORT RFA_RSSI_ADC_CLK = RFA_RSSI_ADC_CLK, DIR = O
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120 | PORT RFA_RSSI_ADC_CLAMP = RFA_RSSI_ADC_CLAMP, DIR = O
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121 | PORT RFA_RSSI_ADC_HIZ = RFA_RSSI_ADC_HIZ, DIR = O
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122 | PORT RFA_RSSI_ADC_SLEEP = RFA_RSSI_ADC_SLEEP, DIR = O
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123 | PORT RFB_RSSI_ADC_D = RFB_RSSI_ADC_D, DIR = I, VEC = [9:0]
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124 | PORT RFB_RSSI_ADC_CLK = RFB_RSSI_ADC_CLK, DIR = O
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125 | PORT RFB_RSSI_ADC_CLAMP = RFB_RSSI_ADC_CLAMP, DIR = O
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126 | PORT RFB_RSSI_ADC_HIZ = RFB_RSSI_ADC_HIZ, DIR = O
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127 | PORT RFB_RSSI_ADC_SLEEP = RFB_RSSI_ADC_SLEEP, DIR = O
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128 | PORT RFC_RSSI_ADC_D = RFC_RSSI_ADC_D, DIR = I, VEC = [9:0]
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129 | PORT RFC_RSSI_ADC_CLK = RFC_RSSI_ADC_CLK, DIR = O
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130 | PORT RFC_RSSI_ADC_CLAMP = RFC_RSSI_ADC_CLAMP, DIR = O
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131 | PORT RFC_RSSI_ADC_HIZ = RFC_RSSI_ADC_HIZ, DIR = O
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132 | PORT RFC_RSSI_ADC_SLEEP = RFC_RSSI_ADC_SLEEP, DIR = O
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133 | PORT RFD_RSSI_ADC_D = RFD_RSSI_ADC_D, DIR = I, VEC = [9:0]
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134 | PORT RFD_RSSI_ADC_CLK = RFD_RSSI_ADC_CLK, DIR = O
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135 | PORT RFD_RSSI_ADC_CLAMP = RFD_RSSI_ADC_CLAMP, DIR = O
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136 | PORT RFD_RSSI_ADC_HIZ = RFD_RSSI_ADC_HIZ, DIR = O
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137 | PORT RFD_RSSI_ADC_SLEEP = RFD_RSSI_ADC_SLEEP, DIR = O
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138 | # I/Q ADCs/DACs
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139 | PORT RFA_DAC_I = RFA_DAC_I, DIR = O, VEC = [15:0]
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140 | PORT RFA_DAC_Q = RFA_DAC_Q, DIR = O, VEC = [15:0]
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141 | PORT RFA_DAC_SPI_CSn = RFA_DAC_SPI_CSn, DIR = O
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142 | PORT RFA_DAC_SPI_SCLK = RFA_DAC_SPI_SCLK, DIR = O
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143 | PORT RFA_DAC_SPI_MOSI = RFA_DAC_SPI_MOSI, DIR = O
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144 | PORT RFA_DAC_SPI_MISO = RFA_DAC_SPI_MISO, DIR = I
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145 | PORT RFA_DAC_RESET = RFA_DAC_RESET, DIR = O
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146 | PORT RFA_DAC_PLLLOCK = RFA_DAC_PLLLOCK, DIR = I
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147 | PORT RFA_RX_ADC_I = RFA_RX_ADC_I, DIR = I, VEC = [13:0]
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148 | PORT RFA_RX_ADC_Q = RFA_RX_ADC_Q, DIR = I, VEC = [13:0]
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149 | PORT RFA_RX_ADC_I_OTR = RFA_RX_ADC_I_OTR, DIR = I
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150 | PORT RFA_RX_ADC_Q_OTR = RFA_RX_ADC_Q_OTR, DIR = I
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151 | PORT RFA_RX_ADC_DCS = RFA_RX_ADC_DCS, DIR = O
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152 | PORT RFA_RX_ADC_DFS = RFA_RX_ADC_DFS, DIR = O
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153 | PORT RFA_RX_ADC_I_PWDN = RFA_RX_ADC_PWDN, DIR = O
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154 | PORT RFA_RX_ADC_Q_PWDN = RFA_RX_ADC_PWDN, DIR = O
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155 | PORT RFB_DAC_I = RFB_DAC_I, DIR = O, VEC = [15:0]
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156 | PORT RFB_DAC_Q = RFB_DAC_Q, DIR = O, VEC = [15:0]
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157 | PORT RFB_DAC_SPI_CSn = RFB_DAC_SPI_CSn, DIR = O
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158 | PORT RFB_DAC_SPI_SCLK = RFB_DAC_SPI_SCLK, DIR = O
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159 | PORT RFB_DAC_SPI_MOSI = RFB_DAC_SPI_MOSI, DIR = O
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160 | PORT RFB_DAC_SPI_MISO = RFB_DAC_SPI_MISO, DIR = I
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161 | PORT RFB_DAC_RESET = RFB_DAC_RESET, DIR = O
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162 | PORT RFB_DAC_PLLLOCK = RFB_DAC_PLLLOCK, DIR = I
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163 | PORT RFB_RX_ADC_I = RFB_RX_ADC_I, DIR = I, VEC = [13:0]
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164 | PORT RFB_RX_ADC_Q = RFB_RX_ADC_Q, DIR = I, VEC = [13:0]
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165 | PORT RFB_RX_ADC_I_OTR = RFB_RX_ADC_I_OTR, DIR = I
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166 | PORT RFB_RX_ADC_Q_OTR = RFB_RX_ADC_Q_OTR, DIR = I
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167 | PORT RFB_RX_ADC_DCS = RFB_RX_ADC_DCS, DIR = O
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168 | PORT RFB_RX_ADC_DFS = RFB_RX_ADC_DFS, DIR = O
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169 | PORT RFB_RX_ADC_I_PWDN = RFB_RX_ADC_PWDN, DIR = O
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170 | PORT RFB_RX_ADC_Q_PWDN = RFB_RX_ADC_PWDN, DIR = O
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171 | PORT RFC_DAC_I = RFC_DAC_I, DIR = O, VEC = [15:0]
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172 | PORT RFC_DAC_Q = RFC_DAC_Q, DIR = O, VEC = [15:0]
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173 | PORT RFC_DAC_SPI_CSn = RFC_DAC_SPI_CSn, DIR = O
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174 | PORT RFC_DAC_SPI_SCLK = RFC_DAC_SPI_SCLK, DIR = O
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175 | PORT RFC_DAC_SPI_MOSI = RFC_DAC_SPI_MOSI, DIR = O
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176 | PORT RFC_DAC_SPI_MISO = RFC_DAC_SPI_MISO, DIR = I
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177 | PORT RFC_DAC_RESET = RFC_DAC_RESET, DIR = O
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178 | PORT RFC_DAC_PLLLOCK = RFC_DAC_PLLLOCK, DIR = I
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179 | PORT RFC_RX_ADC_I = RFC_RX_ADC_I, DIR = I, VEC = [13:0]
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180 | PORT RFC_RX_ADC_Q = RFC_RX_ADC_Q, DIR = I, VEC = [13:0]
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181 | PORT RFC_RX_ADC_I_OTR = RFC_RX_ADC_I_OTR, DIR = I
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182 | PORT RFC_RX_ADC_Q_OTR = RFC_RX_ADC_Q_OTR, DIR = I
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183 | PORT RFC_RX_ADC_DCS = RFC_RX_ADC_DCS, DIR = O
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184 | PORT RFC_RX_ADC_DFS = RFC_RX_ADC_DFS, DIR = O
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185 | PORT RFC_RX_ADC_I_PWDN = RFC_RX_ADC_PWDN, DIR = O
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186 | PORT RFC_RX_ADC_Q_PWDN = RFC_RX_ADC_PWDN, DIR = O
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187 | PORT RFD_DAC_I = RFD_DAC_I, DIR = O, VEC = [15:0]
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188 | PORT RFD_DAC_Q = RFD_DAC_Q, DIR = O, VEC = [15:0]
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189 | PORT RFD_DAC_SPI_CSn = RFD_DAC_SPI_CSn, DIR = O
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190 | PORT RFD_DAC_SPI_SCLK = RFD_DAC_SPI_SCLK, DIR = O
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191 | PORT RFD_DAC_SPI_MOSI = RFD_DAC_SPI_MOSI, DIR = O
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192 | PORT RFD_DAC_SPI_MISO = RFD_DAC_SPI_MISO, DIR = I
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193 | PORT RFD_DAC_RESET = RFD_DAC_RESET, DIR = O
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194 | PORT RFD_DAC_PLLLOCK = RFD_DAC_PLLLOCK, DIR = I
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195 | PORT RFD_RX_ADC_I = RFD_RX_ADC_I, DIR = I, VEC = [13:0]
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196 | PORT RFD_RX_ADC_Q = RFD_RX_ADC_Q, DIR = I, VEC = [13:0]
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197 | PORT RFD_RX_ADC_I_OTR = RFD_RX_ADC_I_OTR, DIR = I
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198 | PORT RFD_RX_ADC_Q_OTR = RFD_RX_ADC_Q_OTR, DIR = I
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199 | PORT RFD_RX_ADC_DCS = RFD_RX_ADC_DCS, DIR = O
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200 | PORT RFD_RX_ADC_DFS = RFD_RX_ADC_DFS, DIR = O
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201 | PORT RFD_RX_ADC_I_PWDN = RFD_RX_ADC_PWDN, DIR = O
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202 | PORT RFD_RX_ADC_Q_PWDN = RFD_RX_ADC_PWDN, DIR = O
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203 | # EEPROM I/O
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204 | PORT RFA_EEPROM_IO = RFA_EEPROM_IO, DIR = IO
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205 | PORT RFB_EEPROM_IO = RFB_EEPROM_IO, DIR = IO
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206 | PORT RFC_EEPROM_IO = RFC_EEPROM_IO, DIR = IO
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207 | PORT RFD_EEPROM_IO = RFD_EEPROM_IO, DIR = IO
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208 | PORT FPGA_EEPROM_IO = FPGA_EEPROM_IO, DIR = IO
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209 | # Clock & Reset
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210 | PORT clk_1_sys_clk = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000
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211 | PORT rst_1_sys_rst = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
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212 | # Digital I/O header
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213 | PORT debughdr = debug_capture_running & debug_transmit_running, DIR = O, VEC = [1:0]
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214 | PORT debug_sw_gpio = debug_sw_gpio, DIR = IO, VEC = [1:0]
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215 | PORT trigger_in = trig_0_in & trig_1_in & trig_2_in & trig_3_in, DIR = I, VEC = [0:3]
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216 | PORT trigger_0_out = trig_2_0_out & trig_3_0_out & trig_4_0_out & trig_5_0_out, DIR = O, VEC = [0:3]
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217 | PORT trigger_1_out = trig_2_1_out & trig_3_1_out & trig_4_1_out & trig_5_1_out, DIR = O, VEC = [0:3]
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218 |
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219 |
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220 | # Optional Debug Header functionality
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221 | # To switch to 6 SW GPIO pins on the Debug Header:
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222 | # - Change above debug_sw_gpio line to:
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223 | # PORT debug_sw_gpio = debug_sw_gpio, DIR = IO, VEC = [5:0]
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224 | # - Modify the xps_gpio instance and change C_GPIO_WIDTH to 6 GPIOs
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225 | # - Comment out trigger_1_out
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226 | # - Modify the system.ucf file to use the debug_sw_gpio pins instead of the trigger_1_out pins
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227 | # ##############################################################################
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228 | # Processor
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229 | # ##############################################################################
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230 | BEGIN ppc405_virtex4
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231 | PARAMETER INSTANCE = ppc405_0
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232 | PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
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233 | PARAMETER C_IDCR_BASEADDR = 0b0100000000
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234 | PARAMETER C_IDCR_HIGHADDR = 0b0111111111
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235 | PARAMETER HW_VER = 2.01.b
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236 | BUS_INTERFACE DPLB0 = plb
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237 | BUS_INTERFACE IPLB0 = plb
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238 | BUS_INTERFACE DSOCM = ppc405_0_docm
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239 | BUS_INTERFACE ISOCM = ppc405_0_iocm
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240 | BUS_INTERFACE JTAGPPC = ppc405_0_jtagppc_bus
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241 | BUS_INTERFACE RESETPPC = ppc_reset_bus
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242 | PORT CPMC405CLOCK = clk_160_0000MHzDCM0
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243 | END
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244 |
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245 | BEGIN isocm_v10
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246 | PARAMETER INSTANCE = ppc405_0_iocm
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247 | PARAMETER C_ISCNTLVALUE = 0xa3
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248 | PARAMETER HW_VER = 2.00.b
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249 | PORT ISOCM_Clk = clk_80_0000MHzDCM0
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250 | PORT SYS_Rst = sys_bus_reset
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251 | END
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252 |
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253 | BEGIN isbram_if_cntlr
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254 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr
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255 | PARAMETER HW_VER = 3.00.c
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256 | PARAMETER C_BASEADDR = 0xffff0000
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257 | PARAMETER C_HIGHADDR = 0xffffffff
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258 | BUS_INTERFACE ISOCM = ppc405_0_iocm
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259 | BUS_INTERFACE DCR_WRITE_PORT = ppc405_0_iocm_cntlr_porta
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260 | BUS_INTERFACE INSTRN_READ_PORT = ppc405_0_iocm_cntlr_portb
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261 | END
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262 |
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263 | BEGIN bram_block
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264 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr_bram
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265 | PARAMETER HW_VER = 1.00.a
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266 | BUS_INTERFACE PORTA = ppc405_0_iocm_cntlr_porta
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267 | BUS_INTERFACE PORTB = ppc405_0_iocm_cntlr_portb
|
---|
268 | END
|
---|
269 |
|
---|
270 | BEGIN dsocm_v10
|
---|
271 | PARAMETER INSTANCE = ppc405_0_docm
|
---|
272 | PARAMETER C_DSCNTLVALUE = 0xa3
|
---|
273 | PARAMETER HW_VER = 2.00.b
|
---|
274 | PORT DSOCM_Clk = clk_80_0000MHzDCM0
|
---|
275 | PORT SYS_Rst = sys_bus_reset
|
---|
276 | END
|
---|
277 |
|
---|
278 | BEGIN dsbram_if_cntlr
|
---|
279 | PARAMETER INSTANCE = ppc405_0_docm_cntlr
|
---|
280 | PARAMETER HW_VER = 3.00.c
|
---|
281 | PARAMETER C_BASEADDR = 0x40110000
|
---|
282 | PARAMETER C_HIGHADDR = 0x4011ffff
|
---|
283 | BUS_INTERFACE DSOCM = ppc405_0_docm
|
---|
284 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
|
---|
285 | END
|
---|
286 |
|
---|
287 | BEGIN bram_block
|
---|
288 | PARAMETER INSTANCE = ppc405_0_docm_cntlr_bram
|
---|
289 | PARAMETER HW_VER = 1.00.a
|
---|
290 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
|
---|
291 | END
|
---|
292 |
|
---|
293 | # ##############################################################################
|
---|
294 | # Clock / Reset / Debug
|
---|
295 | # ##############################################################################
|
---|
296 | BEGIN clock_generator
|
---|
297 | PARAMETER INSTANCE = clock_generator_0
|
---|
298 | PARAMETER C_CLKIN_FREQ = 40000000
|
---|
299 | PARAMETER C_CLKOUT0_FREQ = 125000000
|
---|
300 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
301 | PARAMETER C_CLKOUT0_GROUP = NONE
|
---|
302 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
303 | PARAMETER C_CLKOUT1_FREQ = 160000000
|
---|
304 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
305 | PARAMETER C_CLKOUT1_GROUP = DCM0
|
---|
306 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
307 | PARAMETER C_CLKOUT2_FREQ = 200000000
|
---|
308 | PARAMETER C_CLKOUT2_PHASE = 0
|
---|
309 | PARAMETER C_CLKOUT2_GROUP = NONE
|
---|
310 | PARAMETER C_CLKOUT2_BUF = TRUE
|
---|
311 | PARAMETER C_CLKOUT3_FREQ = 40000000
|
---|
312 | PARAMETER C_CLKOUT3_PHASE = 0
|
---|
313 | PARAMETER C_CLKOUT3_GROUP = NONE
|
---|
314 | PARAMETER C_CLKOUT3_BUF = TRUE
|
---|
315 | PARAMETER C_CLKOUT4_FREQ = 80000000
|
---|
316 | PARAMETER C_CLKOUT4_PHASE = 0
|
---|
317 | PARAMETER C_CLKOUT4_GROUP = DCM0
|
---|
318 | PARAMETER C_CLKOUT4_BUF = TRUE
|
---|
319 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
320 | PARAMETER HW_VER = 4.03.a
|
---|
321 | PORT CLKIN = CLK_S
|
---|
322 | PORT CLKOUT0 = clk_125_0000MHz
|
---|
323 | PORT CLKOUT1 = clk_160_0000MHzDCM0
|
---|
324 | PORT CLKOUT2 = clk_200_0000MHz
|
---|
325 | PORT CLKOUT3 = clk_40_0000MHz
|
---|
326 | PORT CLKOUT4 = clk_80_0000MHzDCM0
|
---|
327 | PORT RST = clk_board_config_config_invalid
|
---|
328 | PORT LOCKED = Dcm_all_locked
|
---|
329 | END
|
---|
330 |
|
---|
331 | BEGIN jtagppc_cntlr
|
---|
332 | PARAMETER INSTANCE = jtagppc_cntlr_inst
|
---|
333 | PARAMETER HW_VER = 2.01.c
|
---|
334 | BUS_INTERFACE JTAGPPC0 = ppc405_0_jtagppc_bus
|
---|
335 | END
|
---|
336 |
|
---|
337 | BEGIN proc_sys_reset
|
---|
338 | PARAMETER INSTANCE = proc_sys_reset_0
|
---|
339 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
340 | PARAMETER HW_VER = 3.00.a
|
---|
341 | BUS_INTERFACE RESETPPC0 = ppc_reset_bus
|
---|
342 | PORT Slowest_sync_clk = clk_40_0000MHz
|
---|
343 | PORT Ext_Reset_In = sys_rst_s
|
---|
344 | PORT Dcm_locked = Dcm_all_locked
|
---|
345 | PORT Bus_Struct_Reset = sys_bus_reset
|
---|
346 | PORT Peripheral_Reset = sys_periph_reset
|
---|
347 | END
|
---|
348 |
|
---|
349 | # ##############################################################################
|
---|
350 | # Interconnect
|
---|
351 | # ##############################################################################
|
---|
352 | BEGIN plb_v46
|
---|
353 | PARAMETER INSTANCE = plb
|
---|
354 | PARAMETER C_DCR_INTFCE = 0
|
---|
355 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
|
---|
356 | PARAMETER HW_VER = 1.05.a
|
---|
357 | PORT PLB_Clk = clk_80_0000MHzDCM0
|
---|
358 | PORT SYS_Rst = sys_bus_reset
|
---|
359 | END
|
---|
360 |
|
---|
361 | # ##############################################################################
|
---|
362 | # Peripherals
|
---|
363 | # ##############################################################################
|
---|
364 | BEGIN xps_central_dma
|
---|
365 | PARAMETER INSTANCE = xps_central_dma_0
|
---|
366 | PARAMETER HW_VER = 2.03.a
|
---|
367 | PARAMETER C_BASEADDR = 0x81000000
|
---|
368 | PARAMETER C_HIGHADDR = 0x8100FFFF
|
---|
369 | BUS_INTERFACE MPLB = plb
|
---|
370 | BUS_INTERFACE SPLB = plb
|
---|
371 | END
|
---|
372 |
|
---|
373 | BEGIN xps_timer
|
---|
374 | PARAMETER INSTANCE = xps_timer_0
|
---|
375 | PARAMETER HW_VER = 1.02.a
|
---|
376 | PARAMETER C_BASEADDR = 0x80100000
|
---|
377 | PARAMETER C_HIGHADDR = 0x8010FFFF
|
---|
378 | BUS_INTERFACE SPLB = plb
|
---|
379 | END
|
---|
380 |
|
---|
381 | BEGIN xps_gpio
|
---|
382 | PARAMETER INSTANCE = xps_gpio_0
|
---|
383 | PARAMETER HW_VER = 2.00.a
|
---|
384 | # PARAMETER C_GPIO_WIDTH = 6
|
---|
385 | PARAMETER C_GPIO_WIDTH = 2
|
---|
386 | PARAMETER C_BASEADDR = 0x80000000
|
---|
387 | PARAMETER C_HIGHADDR = 0x8000FFFF
|
---|
388 | BUS_INTERFACE SPLB = plb
|
---|
389 | PORT GPIO_IO_O = debug_sw_gpio
|
---|
390 | END
|
---|
391 |
|
---|
392 | BEGIN xps_uartlite
|
---|
393 | PARAMETER INSTANCE = rs232_db9
|
---|
394 | PARAMETER C_BAUDRATE = 57600
|
---|
395 | PARAMETER C_DATA_BITS = 8
|
---|
396 | PARAMETER C_USE_PARITY = 0
|
---|
397 | PARAMETER C_ODD_PARITY = 0
|
---|
398 | PARAMETER HW_VER = 1.02.a
|
---|
399 | PARAMETER C_BASEADDR = 0x80300000
|
---|
400 | PARAMETER C_HIGHADDR = 0x8030FFFF
|
---|
401 | BUS_INTERFACE SPLB = plb
|
---|
402 | PORT RX = rs232_db9_RX
|
---|
403 | PORT TX = rs232_db9_TX
|
---|
404 | END
|
---|
405 |
|
---|
406 | BEGIN xps_uartlite
|
---|
407 | PARAMETER INSTANCE = rs232_usb
|
---|
408 | PARAMETER C_BAUDRATE = 57600
|
---|
409 | PARAMETER C_DATA_BITS = 8
|
---|
410 | PARAMETER C_USE_PARITY = 0
|
---|
411 | PARAMETER C_ODD_PARITY = 0
|
---|
412 | PARAMETER HW_VER = 1.02.a
|
---|
413 | PARAMETER C_BASEADDR = 0x80200000
|
---|
414 | PARAMETER C_HIGHADDR = 0x8020FFFF
|
---|
415 | BUS_INTERFACE SPLB = plb
|
---|
416 | PORT RX = rs232_usb_RX
|
---|
417 | PORT TX = rs232_usb_TX
|
---|
418 | END
|
---|
419 |
|
---|
420 | BEGIN xps_bram_if_cntlr
|
---|
421 | PARAMETER INSTANCE = xps_bram_if_cntlr_1
|
---|
422 | PARAMETER C_SPLB_NATIVE_DWIDTH = 64
|
---|
423 | PARAMETER HW_VER = 1.00.b
|
---|
424 | PARAMETER C_BASEADDR = 0x00000000
|
---|
425 | PARAMETER C_HIGHADDR = 0x0000ffff
|
---|
426 | BUS_INTERFACE SPLB = plb
|
---|
427 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
---|
428 | END
|
---|
429 |
|
---|
430 | BEGIN bram_block
|
---|
431 | PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
|
---|
432 | PARAMETER HW_VER = 1.00.a
|
---|
433 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
---|
434 | END
|
---|
435 |
|
---|
436 | # ##############################################################################
|
---|
437 | # Ethernet
|
---|
438 | # ##############################################################################
|
---|
439 | BEGIN xps_ll_temac
|
---|
440 | PARAMETER INSTANCE = ETH_A_MAC
|
---|
441 | PARAMETER C_NUM_IDELAYCTRL = 2
|
---|
442 | PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y6
|
---|
443 | PARAMETER C_PHY_TYPE = 1
|
---|
444 | PARAMETER C_BUS2CORE_CLK_RATIO = 1
|
---|
445 | PARAMETER C_TEMAC_TYPE = 1
|
---|
446 | PARAMETER HW_VER = 2.03.a
|
---|
447 | PARAMETER C_BASEADDR = 0x82100000
|
---|
448 | PARAMETER C_HIGHADDR = 0x8217FFFF
|
---|
449 | PARAMETER C_TEMAC0_TXFIFO = 2048
|
---|
450 | PARAMETER C_TEMAC0_RXFIFO = 2048
|
---|
451 | PARAMETER C_TEMAC0_TXCSUM = 0
|
---|
452 | PARAMETER C_TEMAC0_RXCSUM = 0
|
---|
453 | BUS_INTERFACE SPLB = plb
|
---|
454 | BUS_INTERFACE LLINK0 = ETH_llink0
|
---|
455 | PORT TemacPhy_RST_n = ETH_TemacPhy_RST_n
|
---|
456 | PORT GTX_CLK_0 = clk_125_0000MHz
|
---|
457 | PORT REFCLK = clk_200_0000MHz
|
---|
458 | PORT LlinkTemac0_CLK = clk_80_0000MHzDCM0
|
---|
459 | PORT MII_TX_CLK_0 = ETH_MII_TX_CLK
|
---|
460 | PORT GMII_TXD_0 = ETH_GMII_TXD
|
---|
461 | PORT GMII_TX_EN_0 = ETH_GMII_TX_EN
|
---|
462 | PORT GMII_TX_ER_0 = ETH_GMII_TX_ER
|
---|
463 | PORT GMII_TX_CLK_0 = ETH_GMII_TX_CLK
|
---|
464 | PORT GMII_RXD_0 = ETH_GMII_RXD
|
---|
465 | PORT GMII_RX_DV_0 = ETH_GMII_RX_DV
|
---|
466 | PORT GMII_RX_ER_0 = ETH_GMII_RX_ER
|
---|
467 | PORT GMII_RX_CLK_0 = ETH_GMII_RX_CLK
|
---|
468 | PORT MDC_0 = ETH_MDC
|
---|
469 | PORT MDIO_0 = ETH_MDIO
|
---|
470 | END
|
---|
471 |
|
---|
472 | BEGIN xps_ll_fifo
|
---|
473 | PARAMETER INSTANCE = ETH_A_FIFO
|
---|
474 | PARAMETER HW_VER = 1.02.a
|
---|
475 | PARAMETER C_BASEADDR = 0x82000000
|
---|
476 | PARAMETER C_HIGHADDR = 0x8200FFFF
|
---|
477 | BUS_INTERFACE SPLB = plb
|
---|
478 | BUS_INTERFACE LLINK = ETH_llink0
|
---|
479 | END
|
---|
480 |
|
---|
481 | # ##############################################################################
|
---|
482 | # Mango Cores
|
---|
483 | # ##############################################################################
|
---|
484 | BEGIN warp_v4_userio
|
---|
485 | PARAMETER INSTANCE = UserIO
|
---|
486 | PARAMETER C_ADDRESS_0 = 0x40
|
---|
487 | PARAMETER C_ADDRESS_1 = 0x42
|
---|
488 | PARAMETER C_I2C_DIVIDER = 0x40
|
---|
489 | PARAMETER HW_VER = 1.00.a
|
---|
490 | PARAMETER C_BASEADDR = 0x80500000
|
---|
491 | PARAMETER C_HIGHADDR = 0x8050FFFF
|
---|
492 | BUS_INTERFACE SPLB = plb
|
---|
493 | PORT LEDs_out = UserIO_LEDs
|
---|
494 | PORT IOEx_SDA = UserIO_IOEx_SDA
|
---|
495 | PORT IOEx_SCL = UserIO_IOEx_SCL
|
---|
496 | PORT PB_in = UserIO_PB
|
---|
497 | PORT DIPSW_in = UserIO_DIPSW
|
---|
498 | END
|
---|
499 |
|
---|
500 | BEGIN clock_board_config
|
---|
501 | PARAMETER INSTANCE = clk_board_config
|
---|
502 | PARAMETER HW_VER = 1.05.a
|
---|
503 | PARAMETER radio_clk_out4_mode = 0x1eff
|
---|
504 | PARAMETER radio_clk_out7_mode = 0x1eff
|
---|
505 | PARAMETER logic_clk_out0_mode = 0x08ff
|
---|
506 | PARAMETER logic_clk_out1_mode = 0x08ff
|
---|
507 | PARAMETER radio_clk_source_sel_mode = 1
|
---|
508 | PARAMETER logic_clk_source_sel_mode = 1
|
---|
509 | PARAMETER fpga_radio_clk_source = 1
|
---|
510 | PARAMETER fpga_logic_clk_source = 1
|
---|
511 | PARAMETER radio_clk_forward_out_mode = 0x08FF
|
---|
512 | PARAMETER logic_clk_forward_out_mode = 0x1EFF
|
---|
513 | PORT sys_clk = clk_board_config_sys_clk
|
---|
514 | PORT sys_rst = net_gnd
|
---|
515 | PORT cfg_radio_dat_out = clk_board_config_radio_dat_out
|
---|
516 | PORT cfg_radio_csb_out = clk_board_config_radio_csb_out
|
---|
517 | PORT cfg_radio_en_out = clk_board_config_radio_en_out
|
---|
518 | PORT cfg_radio_clk_out = clk_board_config_radio_clk_out
|
---|
519 | PORT cfg_logic_dat_out = clk_board_config_logic_dat_out
|
---|
520 | PORT cfg_logic_csb_out = clk_board_config_logic_csb_out
|
---|
521 | PORT cfg_logic_en_out = clk_board_config_logic_en_out
|
---|
522 | PORT cfg_logic_clk_out = clk_board_config_logic_clk_out
|
---|
523 | PORT radio_clk_src_sel = radio2_dipsw_zero
|
---|
524 | PORT logic_clk_src_sel = radio2_dipsw_one
|
---|
525 | PORT config_invalid = clk_board_config_config_invalid
|
---|
526 | END
|
---|
527 |
|
---|
528 | BEGIN util_bus_split
|
---|
529 | PARAMETER INSTANCE = util_bus_split_0
|
---|
530 | PARAMETER HW_VER = 1.00.a
|
---|
531 | PARAMETER C_SIZE_IN = 4
|
---|
532 | PARAMETER C_SPLIT = 2
|
---|
533 | PORT Sig = RFA_DIPSW
|
---|
534 | PORT Out1 = radio2_dipsw_zero & radio2_dipsw_one
|
---|
535 | END
|
---|
536 |
|
---|
537 | BEGIN eeprom_onewire
|
---|
538 | PARAMETER INSTANCE = eeprom_controller
|
---|
539 | PARAMETER HW_VER = 1.10.a
|
---|
540 | PARAMETER C_MEM0_BASEADDR = 0x80400000
|
---|
541 | PARAMETER C_MEM0_HIGHADDR = 0x8040FFFF
|
---|
542 | BUS_INTERFACE SPLB = plb
|
---|
543 | PORT DQ0 = FPGA_EEPROM_IO
|
---|
544 | PORT DQ1 = RFA_EEPROM_IO
|
---|
545 | PORT DQ2 = RFB_EEPROM_IO
|
---|
546 | PORT DQ3 = RFC_EEPROM_IO
|
---|
547 | PORT DQ4 = RFD_EEPROM_IO
|
---|
548 | PORT DQ5_I = net_vcc
|
---|
549 | PORT DQ6_I = net_vcc
|
---|
550 | PORT DQ7_I = net_vcc
|
---|
551 | END
|
---|
552 |
|
---|
553 | BEGIN radio_controller
|
---|
554 | PARAMETER INSTANCE = radio_controller_0
|
---|
555 | PARAMETER HW_VER = 2.00.a
|
---|
556 | PARAMETER C_BASEADDR = 0x85000000
|
---|
557 | PARAMETER C_HIGHADDR = 0x8500FFFF
|
---|
558 | BUS_INTERFACE SPLB = plb
|
---|
559 | # RFA
|
---|
560 | PORT RFA_TxEn = RFA_TxEn
|
---|
561 | PORT RFA_RxEn = RFA_RxEn
|
---|
562 | PORT RFA_RxHP = RFA_RxHP
|
---|
563 | PORT RFA_SHDN = RFA_SHDN
|
---|
564 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK
|
---|
565 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI
|
---|
566 | PORT RFA_SPI_CSn = RFA_SPI_CSn
|
---|
567 | PORT RFA_B = RFA_B
|
---|
568 | PORT RFA_LD = RFA_LD
|
---|
569 | PORT RFA_PAEn_24 = RFA_PAEn_24
|
---|
570 | PORT RFA_PAEn_5 = RFA_PAEn_5
|
---|
571 | PORT RFA_AntSw = RFA_AntSw
|
---|
572 | PORT RFA_DIPSW = RFA_DIPSW
|
---|
573 | PORT RFA_RSSI_ADC_CLAMP = RFA_RSSI_ADC_CLAMP
|
---|
574 | PORT RFA_RSSI_ADC_HIZ = RFA_RSSI_ADC_HIZ
|
---|
575 | PORT RFA_RSSI_ADC_SLEEP = RFA_RSSI_ADC_SLEEP
|
---|
576 | PORT RFA_DAC_SPI_CSn = RFA_DAC_SPI_CSn
|
---|
577 | PORT RFA_DAC_SPI_SCLK = RFA_DAC_SPI_SCLK
|
---|
578 | PORT RFA_DAC_SPI_MOSI = RFA_DAC_SPI_MOSI
|
---|
579 | PORT RFA_DAC_SPI_MISO = RFA_DAC_SPI_MISO
|
---|
580 | PORT RFA_DAC_RESET = RFA_DAC_RESET
|
---|
581 | PORT RFA_DAC_PLLLOCK = RFA_DAC_PLLLOCK
|
---|
582 | PORT RFA_RX_ADC_DCS = RFA_RX_ADC_DCS
|
---|
583 | PORT RFA_RX_ADC_DFS = RFA_RX_ADC_DFS
|
---|
584 | PORT RFA_RX_ADC_PWDN = RFA_RX_ADC_PWDN
|
---|
585 | # RFA - User ports
|
---|
586 | PORT usr_RFA_statLED_Tx = RFA_statLED_Tx
|
---|
587 | PORT usr_RFA_statLED_Rx = RFA_statLED_Rx
|
---|
588 | PORT usr_RFA_RxHP = agc_rxhp_a
|
---|
589 | PORT usr_RFA_RxGainRF = agc_g_rf_a
|
---|
590 | PORT usr_RFA_RxGainBB = agc_g_bb_a
|
---|
591 | # RFB
|
---|
592 | PORT RFB_TxEn = RFB_TxEn
|
---|
593 | PORT RFB_RxEn = RFB_RxEn
|
---|
594 | PORT RFB_RxHP = RFB_RxHP
|
---|
595 | PORT RFB_SHDN = RFB_SHDN
|
---|
596 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK
|
---|
597 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI
|
---|
598 | PORT RFB_SPI_CSn = RFB_SPI_CSn
|
---|
599 | PORT RFB_B = RFB_B
|
---|
600 | PORT RFB_LD = RFB_LD
|
---|
601 | PORT RFB_PAEn_24 = RFB_PAEn_24
|
---|
602 | PORT RFB_PAEn_5 = RFB_PAEn_5
|
---|
603 | PORT RFB_AntSw = RFB_AntSw
|
---|
604 | PORT RFB_DIPSW = RFB_DIPSW
|
---|
605 | PORT RFB_RSSI_ADC_CLAMP = RFB_RSSI_ADC_CLAMP
|
---|
606 | PORT RFB_RSSI_ADC_HIZ = RFB_RSSI_ADC_HIZ
|
---|
607 | PORT RFB_RSSI_ADC_SLEEP = RFB_RSSI_ADC_SLEEP
|
---|
608 | PORT RFB_DAC_SPI_CSn = RFB_DAC_SPI_CSn
|
---|
609 | PORT RFB_DAC_SPI_SCLK = RFB_DAC_SPI_SCLK
|
---|
610 | PORT RFB_DAC_SPI_MOSI = RFB_DAC_SPI_MOSI
|
---|
611 | PORT RFB_DAC_SPI_MISO = RFB_DAC_SPI_MISO
|
---|
612 | PORT RFB_DAC_RESET = RFB_DAC_RESET
|
---|
613 | PORT RFB_DAC_PLLLOCK = RFB_DAC_PLLLOCK
|
---|
614 | PORT RFB_RX_ADC_DCS = RFB_RX_ADC_DCS
|
---|
615 | PORT RFB_RX_ADC_DFS = RFB_RX_ADC_DFS
|
---|
616 | PORT RFB_RX_ADC_PWDN = RFB_RX_ADC_PWDN
|
---|
617 | # RFB - User ports
|
---|
618 | PORT usr_RFB_statLED_Tx = RFB_statLED_Tx
|
---|
619 | PORT usr_RFB_statLED_Rx = RFB_statLED_Rx
|
---|
620 | PORT usr_RFB_RxHP = agc_rxhp_b
|
---|
621 | PORT usr_RFB_RxGainRF = agc_g_rf_b
|
---|
622 | PORT usr_RFB_RxGainBB = agc_g_bb_b
|
---|
623 | # RFC
|
---|
624 | PORT RFC_TxEn = RFC_TxEn
|
---|
625 | PORT RFC_RxEn = RFC_RxEn
|
---|
626 | PORT RFC_RxHP = RFC_RxHP
|
---|
627 | PORT RFC_SHDN = RFC_SHDN
|
---|
628 | PORT RFC_SPI_SCLK = RFC_SPI_SCLK
|
---|
629 | PORT RFC_SPI_MOSI = RFC_SPI_MOSI
|
---|
630 | PORT RFC_SPI_CSn = RFC_SPI_CSn
|
---|
631 | PORT RFC_B = RFC_B
|
---|
632 | PORT RFC_LD = RFC_LD
|
---|
633 | PORT RFC_PAEn_24 = RFC_PAEn_24
|
---|
634 | PORT RFC_PAEn_5 = RFC_PAEn_5
|
---|
635 | PORT RFC_AntSw = RFC_AntSw
|
---|
636 | PORT RFC_DIPSW = RFC_DIPSW
|
---|
637 | PORT RFC_RSSI_ADC_CLAMP = RFC_RSSI_ADC_CLAMP
|
---|
638 | PORT RFC_RSSI_ADC_HIZ = RFC_RSSI_ADC_HIZ
|
---|
639 | PORT RFC_RSSI_ADC_SLEEP = RFC_RSSI_ADC_SLEEP
|
---|
640 | PORT RFC_DAC_SPI_CSn = RFC_DAC_SPI_CSn
|
---|
641 | PORT RFC_DAC_SPI_SCLK = RFC_DAC_SPI_SCLK
|
---|
642 | PORT RFC_DAC_SPI_MOSI = RFC_DAC_SPI_MOSI
|
---|
643 | PORT RFC_DAC_SPI_MISO = RFC_DAC_SPI_MISO
|
---|
644 | PORT RFC_DAC_RESET = RFC_DAC_RESET
|
---|
645 | PORT RFC_DAC_PLLLOCK = RFC_DAC_PLLLOCK
|
---|
646 | PORT RFC_RX_ADC_DCS = RFC_RX_ADC_DCS
|
---|
647 | PORT RFC_RX_ADC_DFS = RFC_RX_ADC_DFS
|
---|
648 | PORT RFC_RX_ADC_PWDN = RFC_RX_ADC_PWDN
|
---|
649 | # RFC - User ports
|
---|
650 | PORT usr_RFC_statLED_Tx = RFC_statLED_Tx
|
---|
651 | PORT usr_RFC_statLED_Rx = RFC_statLED_Rx
|
---|
652 | PORT usr_RFC_RxHP = agc_rxhp_c
|
---|
653 | PORT usr_RFC_RxGainRF = agc_g_rf_c
|
---|
654 | PORT usr_RFC_RxGainBB = agc_g_bb_c
|
---|
655 | # RFD
|
---|
656 | PORT RFD_TxEn = RFD_TxEn
|
---|
657 | PORT RFD_RxEn = RFD_RxEn
|
---|
658 | PORT RFD_RxHP = RFD_RxHP
|
---|
659 | PORT RFD_SHDN = RFD_SHDN
|
---|
660 | PORT RFD_SPI_SCLK = RFD_SPI_SCLK
|
---|
661 | PORT RFD_SPI_MOSI = RFD_SPI_MOSI
|
---|
662 | PORT RFD_SPI_CSn = RFD_SPI_CSn
|
---|
663 | PORT RFD_B = RFD_B
|
---|
664 | PORT RFD_LD = RFD_LD
|
---|
665 | PORT RFD_PAEn_24 = RFD_PAEn_24
|
---|
666 | PORT RFD_PAEn_5 = RFD_PAEn_5
|
---|
667 | PORT RFD_AntSw = RFD_AntSw
|
---|
668 | PORT RFD_DIPSW = RFD_DIPSW
|
---|
669 | PORT RFD_RSSI_ADC_CLAMP = RFD_RSSI_ADC_CLAMP
|
---|
670 | PORT RFD_RSSI_ADC_HIZ = RFD_RSSI_ADC_HIZ
|
---|
671 | PORT RFD_RSSI_ADC_SLEEP = RFD_RSSI_ADC_SLEEP
|
---|
672 | PORT RFD_DAC_SPI_CSn = RFD_DAC_SPI_CSn
|
---|
673 | PORT RFD_DAC_SPI_SCLK = RFD_DAC_SPI_SCLK
|
---|
674 | PORT RFD_DAC_SPI_MOSI = RFD_DAC_SPI_MOSI
|
---|
675 | PORT RFD_DAC_SPI_MISO = RFD_DAC_SPI_MISO
|
---|
676 | PORT RFD_DAC_RESET = RFD_DAC_RESET
|
---|
677 | PORT RFD_DAC_PLLLOCK = RFD_DAC_PLLLOCK
|
---|
678 | PORT RFD_RX_ADC_DCS = RFD_RX_ADC_DCS
|
---|
679 | PORT RFD_RX_ADC_DFS = RFD_RX_ADC_DFS
|
---|
680 | PORT RFD_RX_ADC_PWDN = RFD_RX_ADC_PWDN
|
---|
681 | # RFD - User ports
|
---|
682 | PORT usr_RFD_statLED_Tx = RFD_statLED_Tx
|
---|
683 | PORT usr_RFD_statLED_Rx = RFD_statLED_Rx
|
---|
684 | PORT usr_RFD_RxHP = agc_rxhp_d
|
---|
685 | PORT usr_RFD_RxGainRF = agc_g_rf_d
|
---|
686 | PORT usr_RFD_RxGainBB = agc_g_bb_d
|
---|
687 | END
|
---|
688 |
|
---|
689 | BEGIN radio_bridge
|
---|
690 | PARAMETER INSTANCE = radio_bridge_RFA
|
---|
691 | PARAMETER HW_VER = 2.00.a
|
---|
692 | PORT samp_clock = clk_40_0000MHz
|
---|
693 | PORT radio_ADC_I = RFA_RX_ADC_I
|
---|
694 | PORT radio_ADC_Q = RFA_RX_ADC_Q
|
---|
695 | PORT radio_DAC_I = RFA_DAC_I
|
---|
696 | PORT radio_DAC_Q = RFA_DAC_Q
|
---|
697 | PORT radio_ADC_I_OTR = RFA_RX_ADC_I_OTR
|
---|
698 | PORT radio_ADC_Q_OTR = RFA_RX_ADC_Q_OTR
|
---|
699 | PORT user_ADC_I = warplab_rfa_Rx_I
|
---|
700 | PORT user_ADC_Q = warplab_rfa_Rx_Q
|
---|
701 | PORT user_DAC_I = warplab_rfa_Tx_I
|
---|
702 | PORT user_DAC_Q = warplab_rfa_Tx_Q
|
---|
703 | PORT radio_RSSI_ADC_D = RFA_RSSI_ADC_D
|
---|
704 | PORT radio_RSSI_ADC_CLK = RFA_RSSI_ADC_CLK
|
---|
705 | PORT user_RSSI_ADC_D = warplab_rfa_rssi
|
---|
706 | PORT user_RSSI_ADC_CLK = warplab_rssi_clk
|
---|
707 | END
|
---|
708 |
|
---|
709 | BEGIN radio_bridge
|
---|
710 | PARAMETER INSTANCE = radio_bridge_RFB
|
---|
711 | PARAMETER HW_VER = 2.00.a
|
---|
712 | PORT samp_clock = clk_40_0000MHz
|
---|
713 | PORT radio_ADC_I = RFB_RX_ADC_I
|
---|
714 | PORT radio_ADC_Q = RFB_RX_ADC_Q
|
---|
715 | PORT radio_DAC_I = RFB_DAC_I
|
---|
716 | PORT radio_DAC_Q = RFB_DAC_Q
|
---|
717 | PORT radio_ADC_I_OTR = RFB_RX_ADC_I_OTR
|
---|
718 | PORT radio_ADC_Q_OTR = RFB_RX_ADC_Q_OTR
|
---|
719 | PORT user_ADC_I = warplab_rfb_Rx_I
|
---|
720 | PORT user_ADC_Q = warplab_rfb_Rx_Q
|
---|
721 | PORT user_DAC_I = warplab_rfb_Tx_I
|
---|
722 | PORT user_DAC_Q = warplab_rfb_Tx_Q
|
---|
723 | PORT radio_RSSI_ADC_D = RFB_RSSI_ADC_D
|
---|
724 | PORT radio_RSSI_ADC_CLK = RFB_RSSI_ADC_CLK
|
---|
725 | PORT user_RSSI_ADC_D = warplab_rfb_rssi
|
---|
726 | PORT user_RSSI_ADC_CLK = warplab_rssi_clk
|
---|
727 | END
|
---|
728 |
|
---|
729 | BEGIN radio_bridge
|
---|
730 | PARAMETER INSTANCE = radio_bridge_RFC
|
---|
731 | PARAMETER HW_VER = 2.00.a
|
---|
732 | PORT samp_clock = clk_40_0000MHz
|
---|
733 | PORT radio_ADC_I = RFC_RX_ADC_I
|
---|
734 | PORT radio_ADC_Q = RFC_RX_ADC_Q
|
---|
735 | PORT radio_DAC_I = RFC_DAC_I
|
---|
736 | PORT radio_DAC_Q = RFC_DAC_Q
|
---|
737 | PORT radio_ADC_I_OTR = RFC_RX_ADC_I_OTR
|
---|
738 | PORT radio_ADC_Q_OTR = RFC_RX_ADC_Q_OTR
|
---|
739 | PORT user_ADC_I = warplab_rfc_Rx_I
|
---|
740 | PORT user_ADC_Q = warplab_rfc_Rx_Q
|
---|
741 | PORT user_DAC_I = warplab_rfc_Tx_I
|
---|
742 | PORT user_DAC_Q = warplab_rfc_Tx_Q
|
---|
743 | PORT radio_RSSI_ADC_D = RFC_RSSI_ADC_D
|
---|
744 | PORT radio_RSSI_ADC_CLK = RFC_RSSI_ADC_CLK
|
---|
745 | PORT user_RSSI_ADC_D = warplab_rfc_rssi
|
---|
746 | PORT user_RSSI_ADC_CLK = warplab_rssi_clk
|
---|
747 | END
|
---|
748 |
|
---|
749 | BEGIN radio_bridge
|
---|
750 | PARAMETER INSTANCE = radio_bridge_RFD
|
---|
751 | PARAMETER HW_VER = 2.00.a
|
---|
752 | PORT samp_clock = clk_40_0000MHz
|
---|
753 | PORT radio_ADC_I = RFD_RX_ADC_I
|
---|
754 | PORT radio_ADC_Q = RFD_RX_ADC_Q
|
---|
755 | PORT radio_DAC_I = RFD_DAC_I
|
---|
756 | PORT radio_DAC_Q = RFD_DAC_Q
|
---|
757 | PORT radio_ADC_I_OTR = RFD_RX_ADC_I_OTR
|
---|
758 | PORT radio_ADC_Q_OTR = RFD_RX_ADC_Q_OTR
|
---|
759 | PORT user_ADC_I = warplab_rfd_Rx_I
|
---|
760 | PORT user_ADC_Q = warplab_rfd_Rx_Q
|
---|
761 | PORT user_DAC_I = warplab_rfd_Tx_I
|
---|
762 | PORT user_DAC_Q = warplab_rfd_Tx_Q
|
---|
763 | PORT radio_RSSI_ADC_D = RFD_RSSI_ADC_D
|
---|
764 | PORT radio_RSSI_ADC_CLK = RFD_RSSI_ADC_CLK
|
---|
765 | PORT user_RSSI_ADC_D = warplab_rfd_rssi
|
---|
766 | PORT user_RSSI_ADC_CLK = warplab_rssi_clk
|
---|
767 | END
|
---|
768 |
|
---|
769 | # ##############################################################################
|
---|
770 | # Local Cores
|
---|
771 | # ##############################################################################
|
---|
772 | BEGIN w2_warplab_trigger_proc_plbw
|
---|
773 | PARAMETER INSTANCE = warplab_trigger_proc
|
---|
774 | PARAMETER HW_VER = 1.04.b
|
---|
775 | PARAMETER C_BASEADDR = 0x84000000
|
---|
776 | PARAMETER C_HIGHADDR = 0x8400FFFF
|
---|
777 | BUS_INTERFACE SPLB = plb
|
---|
778 | PORT sysgen_clk = clk_160_0000MHzDCM0
|
---|
779 | PORT agc_done_in = agc_is_done
|
---|
780 | PORT rfa_rssi = warplab_rfa_rssi
|
---|
781 | PORT rfb_rssi = warplab_rfb_rssi
|
---|
782 | PORT rfc_rssi = warplab_rfc_rssi
|
---|
783 | PORT rfd_rssi = warplab_rfd_rssi
|
---|
784 | PORT rssi_clk = warplab_rssi_clk
|
---|
785 | # Debug header trigger inputs
|
---|
786 | PORT debug_0_in = trig_0_in
|
---|
787 | PORT debug_1_in = trig_1_in
|
---|
788 | PORT debug_2_in = trig_2_in
|
---|
789 | PORT debug_3_in = trig_3_in
|
---|
790 | # Trigger outputs to internal modules
|
---|
791 | PORT trig_0_out = baseband_trigger
|
---|
792 | PORT trig_1_out = agc_start
|
---|
793 | # Trigger outputs to the debug header
|
---|
794 | PORT trig_2_0_out = trig_2_0_out
|
---|
795 | PORT trig_3_0_out = trig_3_0_out
|
---|
796 | PORT trig_4_0_out = trig_4_0_out
|
---|
797 | PORT trig_5_0_out = trig_5_0_out
|
---|
798 | # Replicated trigger outputs to the debug header
|
---|
799 | PORT trig_2_1_out = trig_2_1_out
|
---|
800 | PORT trig_3_1_out = trig_3_1_out
|
---|
801 | PORT trig_4_1_out = trig_4_1_out
|
---|
802 | PORT trig_5_1_out = trig_5_1_out
|
---|
803 | END
|
---|
804 |
|
---|
805 | BEGIN w2_warplab_buffers_plbw
|
---|
806 | PARAMETER INSTANCE = warplab_buffers
|
---|
807 | PARAMETER HW_VER = 3.01.c
|
---|
808 | PARAMETER C_BASEADDR = 0x83000000
|
---|
809 | PARAMETER C_HIGHADDR = 0x833FFFFF
|
---|
810 | BUS_INTERFACE SPLB = plb
|
---|
811 | PORT sysgen_clk = clk_40_0000MHz
|
---|
812 | PORT rssi_adc_clk = warplab_rssi_clk
|
---|
813 | PORT DESIGN_VER = 0x00070501
|
---|
814 | PORT agc_done = agc_is_done
|
---|
815 | # RFA
|
---|
816 | PORT rfa_dac_i = warplab_rfa_Tx_I
|
---|
817 | PORT rfa_dac_q = warplab_rfa_Tx_Q
|
---|
818 | PORT rfa_adc_i = warplab_rfa_Rx_I
|
---|
819 | PORT rfa_adc_q = warplab_rfa_Rx_Q
|
---|
820 | PORT rfa_agc_filt_i = dc_filtered_i_a
|
---|
821 | PORT rfa_agc_filt_q = dc_filtered_q_a
|
---|
822 | PORT rfa_rssi = warplab_rfa_rssi
|
---|
823 | PORT rfa_g_bb = agc_g_bb_a
|
---|
824 | PORT rfa_g_rf = agc_g_rf_a
|
---|
825 | PORT rfa_rxhp = agc_rxhp_a
|
---|
826 | # RFB
|
---|
827 | PORT rfb_dac_i = warplab_rfb_Tx_I
|
---|
828 | PORT rfb_dac_q = warplab_rfb_Tx_Q
|
---|
829 | PORT rfb_adc_i = warplab_rfb_Rx_I
|
---|
830 | PORT rfb_adc_q = warplab_rfb_Rx_Q
|
---|
831 | PORT rfb_agc_filt_i = dc_filtered_i_b
|
---|
832 | PORT rfb_agc_filt_q = dc_filtered_q_b
|
---|
833 | PORT rfb_rssi = warplab_rfb_rssi
|
---|
834 | PORT rfb_g_bb = agc_g_bb_b
|
---|
835 | PORT rfb_g_rf = agc_g_rf_b
|
---|
836 | PORT rfb_rxhp = agc_rxhp_b
|
---|
837 | # RFC
|
---|
838 | PORT rfc_dac_i = warplab_rfc_Tx_I
|
---|
839 | PORT rfc_dac_q = warplab_rfc_Tx_Q
|
---|
840 | PORT rfc_adc_i = warplab_rfc_Rx_I
|
---|
841 | PORT rfc_adc_q = warplab_rfc_Rx_Q
|
---|
842 | PORT rfc_agc_filt_i = dc_filtered_i_c
|
---|
843 | PORT rfc_agc_filt_q = dc_filtered_q_c
|
---|
844 | PORT rfc_rssi = warplab_rfc_rssi
|
---|
845 | PORT rfc_g_bb = agc_g_bb_c
|
---|
846 | PORT rfc_g_rf = agc_g_rf_c
|
---|
847 | PORT rfc_rxhp = agc_rxhp_c
|
---|
848 | # RFD
|
---|
849 | PORT rfd_dac_i = warplab_rfd_Tx_I
|
---|
850 | PORT rfd_dac_q = warplab_rfd_Tx_Q
|
---|
851 | PORT rfd_adc_i = warplab_rfd_Rx_I
|
---|
852 | PORT rfd_adc_q = warplab_rfd_Rx_Q
|
---|
853 | PORT rfd_agc_filt_i = dc_filtered_i_d
|
---|
854 | PORT rfd_agc_filt_q = dc_filtered_q_d
|
---|
855 | PORT rfd_rssi = warplab_rfd_rssi
|
---|
856 | PORT rfd_g_bb = agc_g_bb_d
|
---|
857 | PORT rfd_g_rf = agc_g_rf_d
|
---|
858 | PORT rfd_rxhp = agc_rxhp_d
|
---|
859 | # Other ports
|
---|
860 | PORT stoptx = net_gnd
|
---|
861 | PORT trigger_in = baseband_trigger
|
---|
862 | PORT capture_running = debug_capture_running
|
---|
863 | PORT transmit_running = debug_transmit_running
|
---|
864 | PORT dram_init_done = net_gnd
|
---|
865 | END
|
---|
866 |
|
---|
867 | BEGIN w2_warplab_agc_plbw
|
---|
868 | PARAMETER INSTANCE = warplab_agc
|
---|
869 | PARAMETER HW_VER = 3.00.b
|
---|
870 | PARAMETER C_BASEADDR = 0x84800000
|
---|
871 | PARAMETER C_HIGHADDR = 0x8480FFFF
|
---|
872 | BUS_INTERFACE SPLB = plb
|
---|
873 | PORT sysgen_clk = clk_80_0000MHzDCM0
|
---|
874 | PORT adc_rx_clk = clk_40_0000MHz
|
---|
875 | PORT agc_run = agc_start
|
---|
876 | PORT agc_done = agc_is_done
|
---|
877 | # RFA
|
---|
878 | PORT rfa_agc_rxhp = agc_rxhp_a
|
---|
879 | PORT rfa_agc_g_bb = agc_g_bb_a
|
---|
880 | PORT rfa_agc_g_rf = agc_g_rf_a
|
---|
881 | PORT rfa_rssi = warplab_rfa_rssi
|
---|
882 | PORT rfa_rx_i_in = warplab_rfa_Rx_I
|
---|
883 | PORT rfa_rx_q_in = warplab_rfa_Rx_Q
|
---|
884 | PORT rfa_rx_i_out = dc_filtered_i_a
|
---|
885 | PORT rfa_rx_q_out = dc_filtered_q_a
|
---|
886 | # RFB
|
---|
887 | PORT rfb_agc_rxhp = agc_rxhp_b
|
---|
888 | PORT rfb_agc_g_bb = agc_g_bb_b
|
---|
889 | PORT rfb_agc_g_rf = agc_g_rf_b
|
---|
890 | PORT rfb_rssi = warplab_rfb_rssi
|
---|
891 | PORT rfb_rx_i_in = warplab_rfb_Rx_I
|
---|
892 | PORT rfb_rx_q_in = warplab_rfb_Rx_Q
|
---|
893 | PORT rfb_rx_i_out = dc_filtered_i_b
|
---|
894 | PORT rfb_rx_q_out = dc_filtered_q_b
|
---|
895 | # RFC
|
---|
896 | PORT rfc_agc_rxhp = agc_rxhp_c
|
---|
897 | PORT rfc_agc_g_bb = agc_g_bb_c
|
---|
898 | PORT rfc_agc_g_rf = agc_g_rf_c
|
---|
899 | PORT rfc_rssi = warplab_rfc_rssi
|
---|
900 | PORT rfc_rx_i_in = warplab_rfc_Rx_I
|
---|
901 | PORT rfc_rx_q_in = warplab_rfc_Rx_Q
|
---|
902 | PORT rfc_rx_i_out = dc_filtered_i_c
|
---|
903 | PORT rfc_rx_q_out = dc_filtered_q_c
|
---|
904 | # RFD
|
---|
905 | PORT rfd_agc_rxhp = agc_rxhp_d
|
---|
906 | PORT rfd_agc_g_bb = agc_g_bb_d
|
---|
907 | PORT rfd_agc_g_rf = agc_g_rf_d
|
---|
908 | PORT rfd_rssi = warplab_rfd_rssi
|
---|
909 | PORT rfd_rx_i_in = warplab_rfd_Rx_I
|
---|
910 | PORT rfd_rx_q_in = warplab_rfd_Rx_Q
|
---|
911 | PORT rfd_rx_i_out = dc_filtered_i_d
|
---|
912 | PORT rfd_rx_q_out = dc_filtered_q_d
|
---|
913 | END
|
---|
914 |
|
---|