[1918] | 1 |
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| 2 | # ##############################################################################
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[4195] | 3 | # WARPLab Reference Design
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| 4 | # XPS Hardware Specification (system.mhs)
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| 5 | # Copyright 2013 Mango Communications
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| 6 | # Distributed under the WARP license (http://warpproject.org/license)
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| 7 | # WARPLab version: 7.5.0
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| 8 | # Family: virtex6
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| 9 | # Device: xc6vlx240t
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| 10 | # Package: ff1156
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| 11 | # Speed Grade: -1
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[1918] | 12 | # ##############################################################################
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| 13 | PARAMETER VERSION = 2.1.0
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| 14 |
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| 15 |
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[4195] | 16 | # ##############################################################################
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| 17 | # Top Level Ports
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| 18 | # ##############################################################################
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[1918] | 19 | PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
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| 20 | # USERIO
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| 21 | PORT userio_pb_d = userio_pb_d, DIR = I
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| 22 | PORT userio_pb_m = userio_pb_m, DIR = I
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| 23 | PORT userio_pb_u = userio_pb_u, DIR = I
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| 24 | PORT userio_leds_green = userio_leds_green, DIR = O, VEC = [3:0]
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| 25 | PORT userio_leds_red = userio_leds_red, DIR = O, VEC = [3:0]
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| 26 | PORT userio_dipsw = userio_dipsw, DIR = I, VEC = [3:0]
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| 27 | PORT userio_hexdisp_left = userio_hexdisp_left, DIR = O, VEC = [6:0]
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| 28 | PORT userio_hexdisp_right = userio_hexdisp_right, DIR = O, VEC = [6:0]
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| 29 | PORT userio_hexdisp_left_dp = userio_hexdisp_left_dp, DIR = O
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| 30 | PORT userio_hexdisp_right_dp = userio_hexdisp_right_dp, DIR = O
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| 31 | PORT userio_rfa_led_red = userio_rfa_led_red, DIR = O
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| 32 | PORT userio_rfa_led_green = userio_rfa_led_green, DIR = O
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| 33 | PORT userio_rfb_led_red = userio_rfb_led_red, DIR = O
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| 34 | PORT userio_rfb_led_green = userio_rfb_led_green, DIR = O
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| 35 | # Ethernet pins
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| 36 | PORT ETH_COMA = net_gnd, DIR = O
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| 37 | # ETH_A
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| 38 | PORT ETH_A_PHY_RST_N = ETH_A_PHY_RST_N, DIR = O
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| 39 | PORT ETH_A_MDIO = ETH_A_MDIO, DIR = IO
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| 40 | PORT ETH_A_MDC = ETH_A_MDC, DIR = O
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| 41 | PORT ETH_A_RGMII_TXC = ETH_A_RGMII_TXC, DIR = O
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| 42 | PORT ETH_A_RGMII_TX_CTL = ETH_A_RGMII_TX_CTL, DIR = O
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| 43 | PORT ETH_A_RGMII_TXD = ETH_A_RGMII_TXD, DIR = O, VEC = [3:0]
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| 44 | PORT ETH_A_RGMII_RXC = ETH_A_RGMII_RXC, DIR = I
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| 45 | PORT ETH_A_RGMII_RX_CTL = ETH_A_RGMII_RX_CTL, DIR = I
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| 46 | PORT ETH_A_RGMII_RXD = ETH_A_RGMII_RXD, DIR = I, VEC = [3:0]
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| 47 | PORT ETH_A_PD = net_gnd, DIR = O
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| 48 | # ETH_B
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| 49 | # PORT ETH_B_PHY_RST_N = ETH_B_PHY_RST_N, DIR = O
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| 50 | PORT ETH_B_MDIO = ETH_B_MDIO, DIR = IO
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| 51 | PORT ETH_B_MDC = ETH_B_MDC, DIR = O
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| 52 | PORT ETH_B_RGMII_TXC = ETH_B_RGMII_TXC, DIR = O
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| 53 | PORT ETH_B_RGMII_TX_CTL = ETH_B_RGMII_TX_CTL, DIR = O
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| 54 | PORT ETH_B_RGMII_TXD = ETH_B_RGMII_TXD, DIR = O, VEC = [3:0]
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| 55 | PORT ETH_B_RGMII_RXC = ETH_B_RGMII_RXC, DIR = I
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| 56 | PORT ETH_B_RGMII_RX_CTL = ETH_B_RGMII_RX_CTL, DIR = I
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| 57 | PORT ETH_B_RGMII_RXD = ETH_B_RGMII_RXD, DIR = I, VEC = [3:0]
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| 58 | PORT ETH_B_PD = net_gnd, DIR = O
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| 59 | # USB UART
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[4306] | 60 | PORT usb_uart_sin = axi_uartlite_0_RX, DIR = I
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| 61 | PORT usb_uart_sout = uart_tx, DIR = O
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[1918] | 62 | # AD9512 clock buffer control pins (RF reference & sampling clocks)
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[4306] | 63 | PORT clk_rfref_spi_cs_n = clk_rfref_spi_cs_n, DIR = O
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| 64 | PORT clk_rfref_spi_mosi = clk_rfref_spi_mosi, DIR = O
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| 65 | PORT clk_rfref_spi_sclk = clk_rfref_spi_sclk, DIR = O
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| 66 | PORT clk_rfref_spi_miso = clk_rfref_spi_miso, DIR = I
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| 67 | PORT clk_rfref_func = net_vcc, DIR = O
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| 68 | PORT clk_samp_spi_cs_n = clk_samp_spi_cs_n, DIR = O
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| 69 | PORT clk_samp_spi_mosi = clk_samp_spi_mosi, DIR = O
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| 70 | PORT clk_samp_spi_sclk = clk_samp_spi_sclk, DIR = O
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| 71 | PORT clk_samp_spi_miso = clk_samp_spi_miso, DIR = I
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| 72 | PORT clk_samp_func = net_vcc, DIR = O
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[1918] | 73 | # IIC EEPROM pins
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[4306] | 74 | PORT IIC_EEPROM_iic_scl = IIC_EEPROM_iic_scl, DIR = IO
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| 75 | PORT IIC_EEPROM_iic_sda = IIC_EEPROM_iic_sda, DIR = IO
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| 76 | # CM-PLL pins
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| 77 | PORT cm_spi_sclk = cm_spi_sclk, DIR = O
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| 78 | PORT cm_spi_mosi = cm_spi_mosi, DIR = O
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| 79 | PORT cm_spi_miso = cm_spi_miso, DIR = I
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| 80 | PORT cm_spi_cs_n = cm_spi_cs_n, DIR = O
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| 81 | PORT cm_pll_status = cm_pll_status, DIR = I
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| 82 | PORT cm_switch = cm_switch, DIR = I, VEC = [2:0]
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| 83 | PORT pll_refclk_p = pll_refclk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
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| 84 | PORT pll_refclk_n = pll_refclk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
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[1918] | 85 | # 80MHz sampling clock from AD9512
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[4306] | 86 | PORT samp_clk_p = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
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| 87 | PORT samp_clk_n = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
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[1918] | 88 | # 200MHz LVDS oscillator input
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[4306] | 89 | PORT osc200_p = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
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| 90 | PORT osc200_n = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
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[1918] | 91 | # AD9963 ADC/DAC control pins (RFA & RFB)
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[4306] | 92 | PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n, DIR = O
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[1918] | 93 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO
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[4306] | 94 | PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk, DIR = O
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| 95 | PORT RFA_AD_reset_n = RFA_AD_reset_n, DIR = O
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| 96 | PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n, DIR = O
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[1918] | 97 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO
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[4306] | 98 | PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk, DIR = O
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| 99 | PORT RFB_AD_reset_n = RFB_AD_reset_n, DIR = O
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[1918] | 100 | # RFA AD pins
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| 101 | PORT RFA_AD_TRXD = rfa_trxd, DIR = I, VEC = [11:0]
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| 102 | PORT RFA_AD_TRXCLK = rfa_trxclk, DIR = I
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| 103 | PORT RFA_AD_TRXIQ = rfa_trxiq, DIR = I
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| 104 | PORT RFA_AD_TXD = rfa_txd, DIR = O, VEC = [11:0]
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| 105 | PORT RFA_AD_TXIQ = rfa_txiq, DIR = O
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| 106 | PORT RFA_AD_TXCLK = rfa_txclk, DIR = O
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| 107 | # RFB AD pins
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| 108 | PORT RFB_AD_TRXD = rfb_trxd, DIR = I, VEC = [11:0]
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| 109 | PORT RFB_AD_TRXCLK = rfb_trxclk, DIR = I
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| 110 | PORT RFB_AD_TRXIQ = rfb_trxiq, DIR = I
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| 111 | PORT RFB_AD_TXD = rfb_txd, DIR = O, VEC = [11:0]
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| 112 | PORT RFB_AD_TXIQ = rfb_txiq, DIR = O
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| 113 | PORT RFB_AD_TXCLK = rfb_txclk, DIR = O
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[4306] | 114 | # On-board RSSI ADC pins
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[1918] | 115 | PORT RFA_RSSI_D = warplab_rfa_rssi, DIR = I, VEC = [9:0]
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| 116 | PORT RFB_RSSI_D = warplab_rfb_rssi, DIR = I, VEC = [9:0]
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| 117 | PORT RF_RSSI_CLK = warplab_rssi_clk, DIR = O
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| 118 | PORT RF_RSSI_PD = net_gnd, DIR = O
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| 119 | # RFA transceiver and front-end
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[4306] | 120 | PORT RFA_TxEn = RFA_TxEn, DIR = O
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| 121 | PORT RFA_RxEn = RFA_RxEn, DIR = O
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| 122 | PORT RFA_RxHP = RFA_RxHP, DIR = O
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| 123 | PORT RFA_SHDN = RFA_SHDN, DIR = O
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| 124 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK, DIR = O
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| 125 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI, DIR = O
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| 126 | PORT RFA_SPI_CSn = RFA_SPI_CSn, DIR = O
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| 127 | PORT RFA_B = RFA_B, DIR = O, VEC = [0:6]
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| 128 | PORT RFA_LD = RFA_LD, DIR = I
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| 129 | PORT RFA_PAEn_24 = RFA_PAEn_24, DIR = O
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| 130 | PORT RFA_PAEn_5 = RFA_PAEn_5, DIR = O
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| 131 | PORT RFA_AntSw = RFA_AntSw, DIR = O, VEC = [0:1]
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[1918] | 132 | # RFB transceiver and front-end
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[4306] | 133 | PORT RFB_TxEn = RFB_TxEn, DIR = O
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| 134 | PORT RFB_RxEn = RFB_RxEn, DIR = O
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| 135 | PORT RFB_RxHP = RFB_RxHP, DIR = O
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| 136 | PORT RFB_SHDN = RFB_SHDN, DIR = O
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| 137 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK, DIR = O
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| 138 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI, DIR = O
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| 139 | PORT RFB_SPI_CSn = RFB_SPI_CSn, DIR = O
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| 140 | PORT RFB_B = RFB_B, DIR = O, VEC = [0:6]
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| 141 | PORT RFB_LD = RFB_LD, DIR = I
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| 142 | PORT RFB_PAEn_24 = RFB_PAEn_24, DIR = O
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| 143 | PORT RFB_PAEn_5 = RFB_PAEn_5, DIR = O
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| 144 | PORT RFB_AntSw = RFB_AntSw, DIR = O, VEC = [0:1]
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[2080] | 145 | # DDR
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| 146 | PORT ddr3_sodimm_ck_p = ddr3_sodimm_ck_p, DIR = O, SIGIS = CLK, VEC = [1:0]
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| 147 | PORT ddr3_sodimm_ck_n = ddr3_sodimm_ck_n, DIR = O, SIGIS = CLK, VEC = [1:0]
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| 148 | PORT ddr3_sodimm_cke = ddr3_sodimm_cke, DIR = O
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| 149 | PORT ddr3_sodimm_cs_n = ddr3_sodimm_cs_n, DIR = O
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| 150 | PORT ddr3_sodimm_odt = ddr3_sodimm_odt, DIR = O
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| 151 | PORT ddr3_sodimm_ras_n = ddr3_sodimm_ras_n, DIR = O
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| 152 | PORT ddr3_sodimm_cas_n = ddr3_sodimm_cas_n, DIR = O
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| 153 | PORT ddr3_sodimm_we_n = ddr3_sodimm_we_n, DIR = O
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| 154 | PORT ddr3_sodimm_ba = ddr3_sodimm_ba, DIR = O, VEC = [2:0]
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| 155 | PORT ddr3_sodimm_addr = ddr3_sodimm_addr, DIR = O, VEC = [14:0]
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| 156 | PORT ddr3_sodimm_dq = ddr3_sodimm_dq, DIR = IO, VEC = [63:0]
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| 157 | PORT ddr3_sodimm_dm = ddr3_sodimm_dm, DIR = O, VEC = [7:0]
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| 158 | PORT ddr3_sodimm_reset_n = ddr3_sodimm_reset_n, DIR = O
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| 159 | PORT ddr3_sodimm_dqs_p = ddr3_sodimm_dqs_p, DIR = IO, VEC = [7:0]
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| 160 | PORT ddr3_sodimm_dqs_n = ddr3_sodimm_dqs_n, DIR = IO, VEC = [7:0]
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| 161 | # PORT phy_init_done = ddr3_sodimm_phy_init_done
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[4306] | 162 | # Trigger in/out via CM-PLL daisy chain headers
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| 163 | PORT cm_pll_hdr_in_d = cm_pll_0_in & cm_pll_1_in & cm_pll_2_in & cm_pll_3_in, DIR = I, VEC = [0:3]
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| 164 | PORT cm_pll_hdr_out_d = cm_pll_0_out & cm_pll_1_out & cm_pll_2_out & cm_pll_3_out, DIR = O, VEC = [0:3]
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[4457] | 165 | # Debug Header
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| 166 | PORT debughdr = debug_capture_running & debug_transmit_running, DIR = O, VEC = [0:1]
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[4306] | 167 | PORT debug_sw_gpio = debug_sw_gpio, DIR = IO, VEC = [1:0]
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[2039] | 168 | PORT trigger_in = trig_0_in & trig_1_in & trig_2_in & trig_3_in, DIR = I, VEC = [0:3]
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[4306] | 169 | PORT trigger_0_out = trig_2_0_out & trig_3_0_out & trig_4_0_out & trig_5_0_out, DIR = O, VEC = [0:3]
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| 170 | PORT trigger_1_out = trig_2_1_out & trig_3_1_out & trig_4_1_out & trig_5_1_out, DIR = O, VEC = [0:3]
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[4690] | 171 |
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| 172 |
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| 173 | # ##############################################################################
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[4457] | 174 | # Optional Debug Header functionality
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[4690] | 175 | # ##############################################################################
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| 176 | # 1) To switch to 6 SW GPIO pins on the Debug Header:
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| 177 | # --- Change above debug_sw_gpio line to:
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[4457] | 178 | # PORT debug_sw_gpio = debug_sw_gpio, DIR = IO, VEC = [5:0]
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[4690] | 179 | # --- Modify the axi_gpio instance and change C_GPIO_WIDTH to 6 GPIOs
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| 180 | # --- Comment out trigger_1_out
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| 181 | # --- Modify the system.ucf file to use the debug_sw_gpio pins instead of the trigger_1_out pins
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| 182 | # #################
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| 183 | # 2) To probe Ethernet TX/RX using trigger_1_out pins
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| 184 | # --- Change above trigger_1_out line to:
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[4457] | 185 | # PORT trigger_1_out = ETH_A_RGMII_TX_CTL & ETH_A_RGMII_RX_CTL & ETH_B_RGMII_TX_CTL & ETH_B_RGMII_RX_CTL, DIR = O, VEC = [0:3]
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[4195] | 186 | # ##############################################################################
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| 187 | # Local Cores
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| 188 | # ##############################################################################
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[2382] | 189 | BEGIN w3_warplab_trigger_proc_axiw
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| 190 | PARAMETER INSTANCE = warplab_trigger_proc
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[4929] | 191 | PARAMETER HW_VER = 1.07.g
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[4213] | 192 | PARAMETER C_BASEADDR = 0x10100000
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| 193 | PARAMETER C_HIGHADDR = 0x1010FFFF
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[4185] | 194 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 0
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| 195 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 0
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| 196 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 0
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| 197 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 0
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| 198 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 0
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| 199 | BUS_INTERFACE S_AXI = axi_interconnect_periph_160
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| 200 | BUS_INTERFACE AXI_STR_ETH_A_RXD = ETH_A_MAC_AXI_STR_RXD
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| 201 | BUS_INTERFACE AXI_STR_ETH_B_RXD = ETH_B_MAC_AXI_STR_RXD
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| 202 | PORT axi_aclk = clk_160MHz
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[2382] | 203 | PORT sysgen_clk = clk_160MHz
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| 204 | PORT agc_done_in = agc_is_done
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| 205 | PORT rfa_rssi = warplab_rfa_rssi
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| 206 | PORT rfb_rssi = warplab_rfb_rssi
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| 207 | PORT rfc_rssi = net_gnd
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| 208 | PORT rfd_rssi = net_gnd
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| 209 | PORT rssi_clk = warplab_rssi_clk
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[4306] | 210 | # Debug header trigger inputs
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| 211 | PORT debug_0_in = trig_0_in
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| 212 | PORT debug_1_in = trig_1_in
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| 213 | PORT debug_2_in = trig_2_in
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| 214 | PORT debug_3_in = trig_3_in
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| 215 | # CM-PLL header trigger inputs
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| 216 | PORT cm_pll_0_in = cm_pll_0_in
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| 217 | PORT cm_pll_1_in = cm_pll_1_in
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| 218 | PORT cm_pll_2_in = cm_pll_2_in
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| 219 | PORT cm_pll_3_in = cm_pll_3_in
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| 220 | # Trigger outputs to internal modules
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[2382] | 221 | PORT trig_0_out = baseband_trigger
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| 222 | PORT trig_1_out = agc_start
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[4306] | 223 | # Trigger outputs to the debug header
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| 224 | PORT trig_2_0_out = trig_2_0_out
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| 225 | PORT trig_3_0_out = trig_3_0_out
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| 226 | PORT trig_4_0_out = trig_4_0_out
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| 227 | PORT trig_5_0_out = trig_5_0_out
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| 228 | # Replicated trigger outputs to the debug header
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| 229 | PORT trig_2_1_out = trig_2_1_out
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| 230 | PORT trig_3_1_out = trig_3_1_out
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| 231 | PORT trig_4_1_out = trig_4_1_out
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| 232 | PORT trig_5_1_out = trig_5_1_out
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| 233 | # Replicated trigger outputs to the CM-PLL header
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| 234 | PORT cm_pll_0_out = cm_pll_0_out
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| 235 | PORT cm_pll_1_out = cm_pll_1_out
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| 236 | PORT cm_pll_2_out = cm_pll_2_out
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| 237 | PORT cm_pll_3_out = cm_pll_3_out
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[2382] | 238 | END
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| 239 |
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| 240 | BEGIN w3_warplab_agc_axiw
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| 241 | PARAMETER INSTANCE = warplab_agc
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[4813] | 242 | PARAMETER HW_VER = 3.01.c
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[4213] | 243 | PARAMETER C_BASEADDR = 0x10200000
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| 244 | PARAMETER C_HIGHADDR = 0x1020FFFF
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[4185] | 245 | BUS_INTERFACE S_AXI = axi_interconnect_periph_160
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| 246 | PORT AXI_ACLK = clk_160MHz
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| 247 | PORT sysgen_clk = clk_160MHz
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| 248 | PORT adc_rx_clk = clk_40MHz
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| 249 | PORT agc_run = agc_start
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[2382] | 250 | PORT agc_done = agc_is_done
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[4185] | 251 | PORT rfa_agc_rxhp = agc_rxhp_a
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| 252 | PORT rfa_agc_g_bb = agc_g_bb_a
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| 253 | PORT rfa_agc_g_rf = agc_g_rf_a
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| 254 | PORT rfa_rssi = warplab_rfa_rssi
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| 255 | PORT rfa_rx_i_in = warplab_rfa_Rx_I
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| 256 | PORT rfa_rx_q_in = warplab_rfa_Rx_Q
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| 257 | PORT rfa_rx_i_out = dc_filtered_i_a
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| 258 | PORT rfa_rx_q_out = dc_filtered_q_a
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| 259 | PORT rfb_agc_rxhp = agc_rxhp_b
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| 260 | PORT rfb_agc_g_bb = agc_g_bb_b
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| 261 | PORT rfb_agc_g_rf = agc_g_rf_b
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| 262 | PORT rfb_rssi = warplab_rfb_rssi
|
---|
| 263 | PORT rfb_rx_i_in = warplab_rfb_Rx_I
|
---|
| 264 | PORT rfb_rx_q_in = warplab_rfb_Rx_Q
|
---|
| 265 | PORT rfb_rx_i_out = dc_filtered_i_b
|
---|
| 266 | PORT rfb_rx_q_out = dc_filtered_q_b
|
---|
[2382] | 267 | END
|
---|
| 268 |
|
---|
| 269 | BEGIN w3_warplab_buffers_axiw
|
---|
| 270 | PARAMETER INSTANCE = warplab_buffers
|
---|
[4929] | 271 | PARAMETER HW_VER = 3.01.h
|
---|
[4213] | 272 | PARAMETER C_BASEADDR = 0x10300000
|
---|
| 273 | PARAMETER C_HIGHADDR = 0x1030FFFF
|
---|
[4185] | 274 | BUS_INTERFACE S_AXI = axi_interconnect_periph_160
|
---|
[2382] | 275 | BUS_INTERFACE RFA_RX_PORTB = w3_warplab_buffers_RFA_RX_PORTB
|
---|
| 276 | BUS_INTERFACE RFA_TX_PORTB = w3_warplab_buffers_RFA_TX_PORTB
|
---|
[4185] | 277 | BUS_INTERFACE RFA_RSSI_PORTB = w3_warplab_buffers_RFA_RSSI_PORTB
|
---|
[2382] | 278 | BUS_INTERFACE RFB_RX_PORTB = w3_warplab_buffers_RFB_RX_PORTB
|
---|
| 279 | BUS_INTERFACE RFB_TX_PORTB = w3_warplab_buffers_RFB_TX_PORTB
|
---|
[4185] | 280 | BUS_INTERFACE RFB_RSSI_PORTB = w3_warplab_buffers_RFB_RSSI_PORTB
|
---|
| 281 | PORT AXI_ACLK = clk_160MHz
|
---|
[2382] | 282 | PORT sysgen_clk = clk_40MHz
|
---|
[4185] | 283 | PORT rssi_adc_clk = warplab_rssi_clk
|
---|
[4819] | 284 | PORT DESIGN_VER = 0x00070700
|
---|
[4185] | 285 | PORT agc_done = agc_is_done
|
---|
[2382] | 286 | PORT rfa_dac_i = warplab_rfa_Tx_I
|
---|
| 287 | PORT rfa_dac_q = warplab_rfa_Tx_Q
|
---|
[4185] | 288 | PORT rfa_adc_i = warplab_rfa_Rx_I
|
---|
| 289 | PORT rfa_adc_q = warplab_rfa_Rx_Q
|
---|
| 290 | PORT rfa_agc_filt_i = dc_filtered_i_a
|
---|
| 291 | PORT rfa_agc_filt_q = dc_filtered_q_a
|
---|
| 292 | PORT rfa_rssi = warplab_rfa_rssi
|
---|
| 293 | PORT rfa_g_bb = agc_g_bb_a
|
---|
| 294 | PORT rfa_g_rf = agc_g_rf_a
|
---|
| 295 | PORT rfa_rxhp = agc_rxhp_a
|
---|
[2382] | 296 | PORT rfb_dac_i = warplab_rfb_Tx_I
|
---|
| 297 | PORT rfb_dac_q = warplab_rfb_Tx_Q
|
---|
| 298 | PORT rfb_adc_i = warplab_rfb_Rx_I
|
---|
| 299 | PORT rfb_adc_q = warplab_rfb_Rx_Q
|
---|
[4185] | 300 | PORT rfb_agc_filt_i = dc_filtered_i_b
|
---|
| 301 | PORT rfb_agc_filt_q = dc_filtered_q_b
|
---|
[2382] | 302 | PORT rfb_rssi = warplab_rfb_rssi
|
---|
[4185] | 303 | PORT rfb_g_bb = agc_g_bb_b
|
---|
| 304 | PORT rfb_g_rf = agc_g_rf_b
|
---|
| 305 | PORT rfb_rxhp = agc_rxhp_b
|
---|
[2382] | 306 | PORT stoptx = net_gnd
|
---|
[4185] | 307 | PORT trigger_in = baseband_trigger
|
---|
[4457] | 308 | PORT capture_running = debug_capture_running
|
---|
| 309 | PORT transmit_running = debug_transmit_running
|
---|
[4185] | 310 | PORT rf_rx_iq_rssi_int = warplab_buffers_rf_rx_iq_rssi_int
|
---|
[4233] | 311 | PORT rf_tx_iq_int = warplab_buffers_rf_tx_iq_int
|
---|
[4195] | 312 | PORT dram_init_done = dram_init_done
|
---|
[2382] | 313 | END
|
---|
| 314 |
|
---|
[4195] | 315 | # ##############################################################################
|
---|
| 316 | # Mango Cores
|
---|
| 317 | # ##############################################################################
|
---|
[1918] | 318 | BEGIN w3_iic_eeprom_axi
|
---|
| 319 | PARAMETER INSTANCE = w3_iic_eeprom_onBoard
|
---|
[4306] | 320 | PARAMETER HW_VER = 1.01.a
|
---|
[4213] | 321 | PARAMETER C_BASEADDR = 0x20900000
|
---|
| 322 | PARAMETER C_HIGHADDR = 0x2090FFFF
|
---|
[4185] | 323 | BUS_INTERFACE S_AXI = axi_interconnect_periph_80
|
---|
[2080] | 324 | PORT S_AXI_ACLK = clk_80MHz
|
---|
[4306] | 325 | PORT iic_scl_I = axi_iic_eeprom_scl_I
|
---|
| 326 | PORT iic_scl_O = axi_iic_eeprom_scl_O
|
---|
| 327 | PORT iic_scl_T = axi_iic_eeprom_scl_T
|
---|
| 328 | PORT iic_sda_I = axi_iic_eeprom_sda_I
|
---|
| 329 | PORT iic_sda_O = axi_iic_eeprom_sda_O
|
---|
| 330 | PORT iic_sda_T = axi_iic_eeprom_sda_T
|
---|
[1918] | 331 | END
|
---|
| 332 |
|
---|
| 333 | BEGIN w3_clock_controller_axi
|
---|
| 334 | PARAMETER INSTANCE = w3_clock_controller_0
|
---|
[4306] | 335 | PARAMETER HW_VER = 4.00.a
|
---|
[1918] | 336 | PARAMETER C_DPHASE_TIMEOUT = 0
|
---|
[4213] | 337 | PARAMETER C_BASEADDR = 0x20100000
|
---|
| 338 | PARAMETER C_HIGHADDR = 0x2010FFFF
|
---|
[4185] | 339 | BUS_INTERFACE S_AXI = axi_interconnect_periph_80
|
---|
[2080] | 340 | PORT S_AXI_ACLK = clk_80MHz
|
---|
[1918] | 341 | PORT samp_spi_cs_n = clk_samp_spi_cs_n
|
---|
| 342 | PORT samp_spi_mosi = clk_samp_spi_mosi
|
---|
[4306] | 343 | PORT samp_spi_miso = clk_samp_spi_miso
|
---|
| 344 | PORT samp_spi_sclk = clk_samp_spi_sclk
|
---|
| 345 | PORT samp_func = samp_func
|
---|
| 346 | PORT rfref_spi_cs_n = clk_rfref_spi_cs_n
|
---|
[1918] | 347 | PORT rfref_spi_mosi = clk_rfref_spi_mosi
|
---|
[4306] | 348 | PORT rfref_spi_miso = clk_rfref_spi_miso
|
---|
[1918] | 349 | PORT rfref_spi_sclk = clk_rfref_spi_sclk
|
---|
[4306] | 350 | PORT rfref_func = rfref_func
|
---|
| 351 | PORT cm_spi_cs_n = cm_spi_cs_n
|
---|
| 352 | PORT cm_spi_mosi = cm_spi_mosi
|
---|
| 353 | PORT cm_spi_miso = cm_spi_miso
|
---|
| 354 | PORT cm_spi_sclk = cm_spi_sclk
|
---|
| 355 | PORT cm_pll_status = cm_pll_status
|
---|
| 356 | PORT pll_refclk = pll_refclk
|
---|
[1918] | 357 | PORT usr_status = net_gnd
|
---|
| 358 | PORT at_boot_clk_in = clk_200MHz
|
---|
| 359 | PORT at_boot_clk_in_valid = clk_gen_1_locked
|
---|
[4306] | 360 | PORT at_boot_config_sw = cm_switch
|
---|
[1918] | 361 | PORT at_boot_clkbuf_clocks_invalid = mmcm_inputs_invalid
|
---|
[4306] | 362 | # Communication ports
|
---|
| 363 | PORT uart_tx = clk_cfg_uart_tx
|
---|
| 364 | PORT iic_eeprom_scl_I = clk_cfg_iic_eeprom_scl_I
|
---|
| 365 | PORT iic_eeprom_scl_T = clk_cfg_iic_eeprom_scl_T
|
---|
| 366 | PORT iic_eeprom_scl_O = clk_cfg_iic_eeprom_scl_O
|
---|
| 367 | PORT iic_eeprom_sda_I = clk_cfg_iic_eeprom_sda_I
|
---|
| 368 | PORT iic_eeprom_sda_T = clk_cfg_iic_eeprom_sda_T
|
---|
| 369 | PORT iic_eeprom_sda_O = clk_cfg_iic_eeprom_sda_O
|
---|
[1918] | 370 | END
|
---|
| 371 |
|
---|
[4306] | 372 | BEGIN w3_boot_io_mux
|
---|
| 373 | PARAMETER INSTANCE = boot_io_mux
|
---|
| 374 | PARAMETER HW_VER = 1.00.a
|
---|
| 375 | # Mux Control
|
---|
| 376 | PORT iic_sel_a = mmcm_inputs_invalid
|
---|
| 377 | PORT uart_sel_a = mmcm_inputs_invalid
|
---|
| 378 | # IOBs
|
---|
| 379 | PORT iic_scl = IIC_EEPROM_iic_scl
|
---|
| 380 | PORT iic_sda = IIC_EEPROM_iic_sda
|
---|
| 381 | PORT uart_tx = uart_tx
|
---|
| 382 | # IIC Port A
|
---|
| 383 | PORT iic_scl_I_a = clk_cfg_iic_eeprom_scl_I
|
---|
| 384 | PORT iic_scl_O_a = clk_cfg_iic_eeprom_scl_O
|
---|
| 385 | PORT iic_scl_T_a = clk_cfg_iic_eeprom_scl_T
|
---|
| 386 | PORT iic_sda_I_a = clk_cfg_iic_eeprom_sda_I
|
---|
| 387 | PORT iic_sda_O_a = clk_cfg_iic_eeprom_sda_O
|
---|
| 388 | PORT iic_sda_T_a = clk_cfg_iic_eeprom_sda_T
|
---|
| 389 | # IIC Port B
|
---|
| 390 | PORT iic_scl_I_b = axi_iic_eeprom_scl_I
|
---|
| 391 | PORT iic_scl_O_b = axi_iic_eeprom_scl_O
|
---|
| 392 | PORT iic_scl_T_b = axi_iic_eeprom_scl_T
|
---|
| 393 | PORT iic_sda_I_b = axi_iic_eeprom_sda_I
|
---|
| 394 | PORT iic_sda_O_b = axi_iic_eeprom_sda_O
|
---|
| 395 | PORT iic_sda_T_b = axi_iic_eeprom_sda_T
|
---|
| 396 | # UART Ports
|
---|
| 397 | PORT uart_tx_a = clk_cfg_uart_tx
|
---|
| 398 | PORT uart_tx_b = axi_uart_tx
|
---|
| 399 | END
|
---|
| 400 |
|
---|
[2382] | 401 | BEGIN w3_ad_controller_axi
|
---|
| 402 | PARAMETER INSTANCE = w3_ad_controller_0
|
---|
[4645] | 403 | PARAMETER HW_VER = 3.02.a
|
---|
[4213] | 404 | PARAMETER C_BASEADDR = 0x20400000
|
---|
| 405 | PARAMETER C_HIGHADDR = 0x2040FFFF
|
---|
[4645] | 406 | PARAMETER INCLUDE_RFC_RFD_IO = 0
|
---|
[4185] | 407 | BUS_INTERFACE S_AXI = axi_interconnect_periph_80
|
---|
[2382] | 408 | PORT S_AXI_ACLK = clk_80MHz
|
---|
[4813] | 409 | PORT RF_AD_TXCLK_out_en = RF_AD_TXCLK_out_en
|
---|
[2382] | 410 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio
|
---|
| 411 | PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk
|
---|
[4228] | 412 | PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n
|
---|
[2382] | 413 | PORT RFA_AD_reset_n = RFA_AD_reset_n
|
---|
[4228] | 414 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio
|
---|
[2382] | 415 | PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk
|
---|
| 416 | PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n
|
---|
[4228] | 417 | PORT RFB_AD_reset_n = RFB_AD_reset_n
|
---|
[2382] | 418 | END
|
---|
| 419 |
|
---|
| 420 | BEGIN w3_ad_bridge
|
---|
| 421 | PARAMETER INSTANCE = w3_ad_bridge_onBoard
|
---|
[4813] | 422 | PARAMETER HW_VER = 3.01.e
|
---|
[2382] | 423 | # Clock ports (inputs to w3_ad_bridge)
|
---|
| 424 | PORT sys_samp_clk_Tx = clk_40MHz
|
---|
| 425 | PORT sys_samp_clk_Tx_90 = clk_40MHz_90degphase
|
---|
| 426 | PORT sys_samp_clk_Rx = clk_40MHz
|
---|
[4813] | 427 | PORT ad_TXCLK_out_en = RF_AD_TXCLK_out_en
|
---|
[2382] | 428 | # Top-level AD9963 ports
|
---|
| 429 | PORT ad_RFA_TXD = rfa_txd
|
---|
| 430 | PORT ad_RFA_TXCLK = rfa_txclk
|
---|
| 431 | PORT ad_RFA_TXIQ = rfa_txiq
|
---|
| 432 | PORT ad_RFA_TRXD = rfa_trxd
|
---|
| 433 | PORT ad_RFA_TRXCLK = rfa_trxclk
|
---|
| 434 | PORT ad_RFA_TRXIQ = rfa_trxiq
|
---|
| 435 | PORT ad_RFB_TXD = rfb_txd
|
---|
| 436 | PORT ad_RFB_TXCLK = rfb_txclk
|
---|
| 437 | PORT ad_RFB_TXIQ = rfb_txiq
|
---|
| 438 | PORT ad_RFB_TRXD = rfb_trxd
|
---|
| 439 | PORT ad_RFB_TRXCLK = rfb_trxclk
|
---|
| 440 | PORT ad_RFB_TRXIQ = rfb_trxiq
|
---|
| 441 | PORT user_RFA_TXD_I = warplab_rfa_Tx_I
|
---|
| 442 | PORT user_RFA_TXD_Q = warplab_rfa_Tx_Q
|
---|
| 443 | PORT user_RFA_RXD_I = warplab_rfa_Rx_I
|
---|
| 444 | PORT user_RFA_RXD_Q = warplab_rfa_Rx_Q
|
---|
| 445 | PORT user_RFB_TXD_I = warplab_rfb_Tx_I
|
---|
| 446 | PORT user_RFB_TXD_Q = warplab_rfb_Tx_Q
|
---|
| 447 | PORT user_RFB_RXD_I = warplab_rfb_Rx_I
|
---|
| 448 | PORT user_RFB_RXD_Q = warplab_rfb_Rx_Q
|
---|
| 449 | END
|
---|
| 450 |
|
---|
[4195] | 451 | BEGIN w3_userio_axi
|
---|
| 452 | PARAMETER INSTANCE = W3_USERIO
|
---|
| 453 | PARAMETER HW_VER = 1.01.a
|
---|
[4213] | 454 | PARAMETER C_BASEADDR = 0x20200000
|
---|
| 455 | PARAMETER C_HIGHADDR = 0x2020FFFF
|
---|
[4185] | 456 | BUS_INTERFACE S_AXI = axi_interconnect_periph_80
|
---|
[2080] | 457 | PORT S_AXI_ACLK = clk_80MHz
|
---|
[4195] | 458 | PORT leds_red = userio_leds_red
|
---|
| 459 | PORT leds_green = userio_leds_green
|
---|
| 460 | PORT hexdisp_left = userio_hexdisp_left
|
---|
| 461 | PORT hexdisp_right = userio_hexdisp_right
|
---|
| 462 | PORT hexdisp_left_dp = userio_hexdisp_left_dp
|
---|
| 463 | PORT hexdisp_right_dp = userio_hexdisp_right_dp
|
---|
| 464 | PORT rfa_led_red = userio_rfa_led_red
|
---|
| 465 | PORT rfa_led_green = userio_rfa_led_green
|
---|
| 466 | PORT rfb_led_red = userio_rfb_led_red
|
---|
| 467 | PORT rfb_led_green = userio_rfb_led_green
|
---|
| 468 | PORT dipsw = userio_dipsw
|
---|
| 469 | PORT pb_u = userio_pb_u
|
---|
| 470 | PORT pb_m = userio_pb_m
|
---|
| 471 | PORT pb_d = userio_pb_d
|
---|
| 472 | PORT usr_rfa_led_red = RFA_statLED_Rx
|
---|
| 473 | PORT usr_rfa_led_green = RFA_statLED_Tx
|
---|
| 474 | PORT usr_rfb_led_red = RFB_statLED_Rx
|
---|
| 475 | PORT usr_rfb_led_green = RFB_statLED_Tx
|
---|
| 476 | PORT DNA_Port_Clk = clk_40MHz
|
---|
[1918] | 477 | END
|
---|
| 478 |
|
---|
[4195] | 479 | BEGIN radio_controller_axi
|
---|
| 480 | PARAMETER INSTANCE = radio_controller_0
|
---|
[4457] | 481 | PARAMETER HW_VER = 3.01.a
|
---|
[4213] | 482 | PARAMETER C_BASEADDR = 0x20300000
|
---|
| 483 | PARAMETER C_HIGHADDR = 0x2030FFFF
|
---|
[4195] | 484 | BUS_INTERFACE S_AXI = axi_interconnect_periph_80
|
---|
| 485 | PORT S_AXI_ACLK = clk_80MHz
|
---|
[4457] | 486 | # RFA
|
---|
[4195] | 487 | PORT RFA_TxEn = RFA_TxEn
|
---|
| 488 | PORT RFA_RxEn = RFA_RxEn
|
---|
| 489 | PORT RFA_RxHP = RFA_RxHP
|
---|
| 490 | PORT RFA_SHDN = RFA_SHDN
|
---|
| 491 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK
|
---|
| 492 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI
|
---|
| 493 | PORT RFA_SPI_CSn = RFA_SPI_CSn
|
---|
| 494 | PORT RFA_B = RFA_B
|
---|
| 495 | PORT RFA_LD = RFA_LD
|
---|
| 496 | PORT RFA_PAEn_24 = RFA_PAEn_24
|
---|
| 497 | PORT RFA_PAEn_5 = RFA_PAEn_5
|
---|
| 498 | PORT RFA_AntSw = RFA_AntSw
|
---|
[4457] | 499 | # RFA - User ports
|
---|
| 500 | PORT usr_RFA_statLED_Tx = RFA_statLED_Tx
|
---|
| 501 | PORT usr_RFA_statLED_Rx = RFA_statLED_Rx
|
---|
| 502 | PORT usr_RFA_RxHP = agc_rxhp_a
|
---|
| 503 | PORT usr_RFA_RxGainRF = agc_g_rf_a
|
---|
| 504 | PORT usr_RFA_RxGainBB = agc_g_bb_a
|
---|
| 505 | # RFB
|
---|
[4195] | 506 | PORT RFB_TxEn = RFB_TxEn
|
---|
| 507 | PORT RFB_RxEn = RFB_RxEn
|
---|
| 508 | PORT RFB_RxHP = RFB_RxHP
|
---|
| 509 | PORT RFB_SHDN = RFB_SHDN
|
---|
| 510 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK
|
---|
| 511 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI
|
---|
| 512 | PORT RFB_SPI_CSn = RFB_SPI_CSn
|
---|
| 513 | PORT RFB_B = RFB_B
|
---|
| 514 | PORT RFB_LD = RFB_LD
|
---|
| 515 | PORT RFB_PAEn_24 = RFB_PAEn_24
|
---|
| 516 | PORT RFB_PAEn_5 = RFB_PAEn_5
|
---|
| 517 | PORT RFB_AntSw = RFB_AntSw
|
---|
[4457] | 518 | # RFB - User ports
|
---|
[4195] | 519 | PORT usr_RFB_statLED_Tx = RFB_statLED_Tx
|
---|
| 520 | PORT usr_RFB_statLED_Rx = RFB_statLED_Rx
|
---|
| 521 | PORT usr_RFB_RxHP = agc_rxhp_b
|
---|
| 522 | PORT usr_RFB_RxGainRF = agc_g_rf_b
|
---|
| 523 | PORT usr_RFB_RxGainBB = agc_g_bb_b
|
---|
| 524 | END
|
---|
| 525 |
|
---|
| 526 | # ##############################################################################
|
---|
| 527 | # Buffer core memories
|
---|
| 528 | # ##############################################################################
|
---|
[4228] | 529 | # RFA
|
---|
[2382] | 530 | BEGIN axi_bram_ctrl
|
---|
[4185] | 531 | PARAMETER INSTANCE = rfa_iq_rx_buffer_ctrl
|
---|
[2382] | 532 | PARAMETER HW_VER = 1.03.a
|
---|
[4185] | 533 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
|
---|
[4228] | 534 | PARAMETER C_S_AXI_BASEADDR = 0x41000000
|
---|
[4286] | 535 | PARAMETER C_S_AXI_HIGHADDR = 0x4101FFFF
|
---|
[4225] | 536 | PARAMETER C_S_AXI_DATA_WIDTH = 128
|
---|
[2382] | 537 | PARAMETER C_SINGLE_PORT_BRAM = 1
|
---|
[4306] | 538 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 539 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 540 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 541 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 542 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
[4185] | 543 | BUS_INTERFACE S_AXI = axi_interconnect_buffers
|
---|
| 544 | BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_0
|
---|
[2382] | 545 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 546 | END
|
---|
| 547 |
|
---|
| 548 | BEGIN bram_block
|
---|
[4185] | 549 | PARAMETER INSTANCE = rfa_iq_rx_buffer
|
---|
[1918] | 550 | PARAMETER HW_VER = 1.00.a
|
---|
[4185] | 551 | BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_0
|
---|
| 552 | BUS_INTERFACE PORTB = w3_warplab_buffers_RFA_RX_PORTB
|
---|
[2382] | 553 | PORT BRAM_Clk_B = clk_40MHz
|
---|
[1918] | 554 | END
|
---|
| 555 |
|
---|
[2382] | 556 | BEGIN axi_bram_ctrl
|
---|
[4185] | 557 | PARAMETER INSTANCE = rfa_rssi_buffer_ctrl
|
---|
[2382] | 558 | PARAMETER HW_VER = 1.03.a
|
---|
[4185] | 559 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
|
---|
[4228] | 560 | PARAMETER C_S_AXI_BASEADDR = 0x41020000
|
---|
| 561 | PARAMETER C_S_AXI_HIGHADDR = 0x41023FFF
|
---|
[4225] | 562 | PARAMETER C_S_AXI_DATA_WIDTH = 128
|
---|
[2382] | 563 | PARAMETER C_SINGLE_PORT_BRAM = 1
|
---|
[4306] | 564 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 565 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 566 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 567 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 568 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
[4185] | 569 | BUS_INTERFACE S_AXI = axi_interconnect_buffers
|
---|
| 570 | BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_1
|
---|
[2382] | 571 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 572 | END
|
---|
| 573 |
|
---|
| 574 | BEGIN bram_block
|
---|
[4185] | 575 | PARAMETER INSTANCE = rfa_rssi_buffer
|
---|
[2382] | 576 | PARAMETER HW_VER = 1.00.a
|
---|
[4185] | 577 | BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_1
|
---|
| 578 | BUS_INTERFACE PORTB = w3_warplab_buffers_RFA_RSSI_PORTB
|
---|
[2382] | 579 | PORT BRAM_Clk_B = clk_40MHz
|
---|
| 580 | END
|
---|
| 581 |
|
---|
| 582 | BEGIN axi_bram_ctrl
|
---|
[4185] | 583 | PARAMETER INSTANCE = rfa_iq_tx_buffer_ctrl
|
---|
[2382] | 584 | PARAMETER HW_VER = 1.03.a
|
---|
[4185] | 585 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
|
---|
[4213] | 586 | PARAMETER C_S_AXI_BASEADDR = 0x41040000
|
---|
| 587 | PARAMETER C_S_AXI_HIGHADDR = 0x4105FFFF
|
---|
[4225] | 588 | PARAMETER C_S_AXI_DATA_WIDTH = 128
|
---|
[2382] | 589 | PARAMETER C_SINGLE_PORT_BRAM = 1
|
---|
[4306] | 590 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 591 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 592 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 593 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 594 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
[4185] | 595 | BUS_INTERFACE S_AXI = axi_interconnect_buffers
|
---|
| 596 | BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_2
|
---|
[2382] | 597 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 598 | END
|
---|
| 599 |
|
---|
| 600 | BEGIN bram_block
|
---|
[4185] | 601 | PARAMETER INSTANCE = rfa_iq_tx_buffer
|
---|
[2382] | 602 | PARAMETER HW_VER = 1.00.a
|
---|
[4185] | 603 | BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_2
|
---|
| 604 | BUS_INTERFACE PORTB = w3_warplab_buffers_RFA_TX_PORTB
|
---|
[2382] | 605 | PORT BRAM_Clk_B = clk_40MHz
|
---|
| 606 | END
|
---|
| 607 |
|
---|
[4228] | 608 | # RFB
|
---|
[2382] | 609 | BEGIN axi_bram_ctrl
|
---|
| 610 | PARAMETER INSTANCE = rfb_iq_rx_buffer_ctrl
|
---|
| 611 | PARAMETER HW_VER = 1.03.a
|
---|
[4228] | 612 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
|
---|
[4213] | 613 | PARAMETER C_S_AXI_BASEADDR = 0x41080000
|
---|
[4286] | 614 | PARAMETER C_S_AXI_HIGHADDR = 0x4109FFFF
|
---|
[4225] | 615 | PARAMETER C_S_AXI_DATA_WIDTH = 128
|
---|
[2382] | 616 | PARAMETER C_SINGLE_PORT_BRAM = 1
|
---|
[4306] | 617 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 618 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 619 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 620 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 621 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
[4185] | 622 | BUS_INTERFACE S_AXI = axi_interconnect_buffers
|
---|
| 623 | BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_3
|
---|
[2382] | 624 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 625 | END
|
---|
| 626 |
|
---|
| 627 | BEGIN bram_block
|
---|
| 628 | PARAMETER INSTANCE = rfb_iq_rx_buffer
|
---|
| 629 | PARAMETER HW_VER = 1.00.a
|
---|
[4185] | 630 | BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_3
|
---|
[2382] | 631 | BUS_INTERFACE PORTB = w3_warplab_buffers_RFB_RX_PORTB
|
---|
| 632 | PORT BRAM_Clk_B = clk_40MHz
|
---|
| 633 | END
|
---|
| 634 |
|
---|
[4185] | 635 | BEGIN axi_bram_ctrl
|
---|
| 636 | PARAMETER INSTANCE = rfb_rssi_buffer_ctrl
|
---|
| 637 | PARAMETER HW_VER = 1.03.a
|
---|
| 638 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
|
---|
[4228] | 639 | PARAMETER C_S_AXI_BASEADDR = 0x410A0000
|
---|
| 640 | PARAMETER C_S_AXI_HIGHADDR = 0x410A3FFF
|
---|
[4225] | 641 | PARAMETER C_S_AXI_DATA_WIDTH = 128
|
---|
[4185] | 642 | PARAMETER C_SINGLE_PORT_BRAM = 1
|
---|
[4306] | 643 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 644 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 645 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 646 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 647 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
[4185] | 648 | BUS_INTERFACE S_AXI = axi_interconnect_buffers
|
---|
| 649 | BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_4
|
---|
| 650 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 651 | END
|
---|
| 652 |
|
---|
| 653 | BEGIN bram_block
|
---|
| 654 | PARAMETER INSTANCE = rfb_rssi_buffer
|
---|
| 655 | PARAMETER HW_VER = 1.00.a
|
---|
| 656 | BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_4
|
---|
| 657 | BUS_INTERFACE PORTB = w3_warplab_buffers_RFB_RSSI_PORTB
|
---|
| 658 | PORT BRAM_Clk_B = clk_40MHz
|
---|
| 659 | END
|
---|
| 660 |
|
---|
| 661 | BEGIN axi_bram_ctrl
|
---|
| 662 | PARAMETER INSTANCE = rfb_iq_tx_buffer_ctrl
|
---|
| 663 | PARAMETER HW_VER = 1.03.a
|
---|
[4228] | 664 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
|
---|
[4213] | 665 | PARAMETER C_S_AXI_BASEADDR = 0x410C0000
|
---|
| 666 | PARAMETER C_S_AXI_HIGHADDR = 0x410DFFFF
|
---|
[4225] | 667 | PARAMETER C_S_AXI_DATA_WIDTH = 128
|
---|
[4185] | 668 | PARAMETER C_SINGLE_PORT_BRAM = 1
|
---|
[4306] | 669 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 670 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 671 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 672 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 673 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
[4185] | 674 | BUS_INTERFACE S_AXI = axi_interconnect_buffers
|
---|
| 675 | BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_5
|
---|
| 676 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 677 | END
|
---|
| 678 |
|
---|
| 679 | BEGIN bram_block
|
---|
| 680 | PARAMETER INSTANCE = rfb_iq_tx_buffer
|
---|
| 681 | PARAMETER HW_VER = 1.00.a
|
---|
| 682 | BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_5
|
---|
| 683 | BUS_INTERFACE PORTB = w3_warplab_buffers_RFB_TX_PORTB
|
---|
| 684 | PORT BRAM_Clk_B = clk_40MHz
|
---|
| 685 | END
|
---|
| 686 |
|
---|
[4195] | 687 | # ##############################################################################
|
---|
| 688 | # Clock / Reset
|
---|
| 689 | # ##############################################################################
|
---|
[1918] | 690 | BEGIN proc_sys_reset
|
---|
| 691 | PARAMETER INSTANCE = proc_sys_reset_0
|
---|
| 692 | PARAMETER HW_VER = 3.00.a
|
---|
| 693 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 694 | PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
|
---|
| 695 | PORT Dcm_locked = clk_gen_all_locked
|
---|
| 696 | PORT MB_Reset = proc_sys_reset_0_MB_Reset
|
---|
| 697 | PORT Slowest_sync_clk = clk_40MHz
|
---|
| 698 | PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
|
---|
| 699 | PORT Ext_Reset_In = RESET
|
---|
| 700 | PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
|
---|
| 701 | END
|
---|
| 702 |
|
---|
| 703 | BEGIN clock_generator
|
---|
[2382] | 704 | PARAMETER INSTANCE = clock_generator_asyncClks
|
---|
| 705 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 706 | PARAMETER HW_VER = 4.03.a
|
---|
| 707 | # 200MHz clock input (driven by 200MHz LVDS oscillator)
|
---|
| 708 | PARAMETER C_CLKIN_FREQ = 200000000
|
---|
| 709 | # TEMAC TxClk
|
---|
| 710 | PARAMETER C_CLKOUT0_FREQ = 125000000
|
---|
| 711 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
| 712 | PARAMETER C_CLKOUT0_GROUP = NONE
|
---|
| 713 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
| 714 | # IDELAYCTRL refclk
|
---|
| 715 | PARAMETER C_CLKOUT1_FREQ = 200000000
|
---|
| 716 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
| 717 | PARAMETER C_CLKOUT1_GROUP = NONE
|
---|
| 718 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
| 719 | PORT CLKIN = osc200_in
|
---|
| 720 | PORT CLKOUT0 = clk_125MHz
|
---|
| 721 | PORT CLKOUT1 = clk_200MHz
|
---|
| 722 | PORT RST = RESET
|
---|
| 723 | PORT LOCKED = clk_gen_1_locked
|
---|
| 724 | END
|
---|
| 725 |
|
---|
| 726 | BEGIN clock_generator
|
---|
[1918] | 727 | PARAMETER INSTANCE = clock_generator_ProcBusSamp_Clocks
|
---|
| 728 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 729 | PARAMETER HW_VER = 4.03.a
|
---|
| 730 | # 80MHz clock input (driven by AD9512 for sampling clock)
|
---|
| 731 | PARAMETER C_CLKIN_FREQ = 80000000
|
---|
| 732 | # 2x Sampling clock 0 deg phase
|
---|
| 733 | PARAMETER C_CLKOUT0_FREQ = 80000000
|
---|
| 734 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
| 735 | PARAMETER C_CLKOUT0_GROUP = MMCM0
|
---|
| 736 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
| 737 | # MB and primary PLB
|
---|
| 738 | PARAMETER C_CLKOUT1_FREQ = 160000000
|
---|
| 739 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
| 740 | PARAMETER C_CLKOUT1_GROUP = MMCM0
|
---|
| 741 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
| 742 | # Sampling clock 0 deg phase
|
---|
| 743 | PARAMETER C_CLKOUT2_FREQ = 40000000
|
---|
| 744 | PARAMETER C_CLKOUT2_PHASE = 0
|
---|
| 745 | PARAMETER C_CLKOUT2_GROUP = MMCM0
|
---|
| 746 | PARAMETER C_CLKOUT2_BUF = TRUE
|
---|
| 747 | # Sampling clock 90 deg phase
|
---|
| 748 | PARAMETER C_CLKOUT3_FREQ = 40000000
|
---|
| 749 | PARAMETER C_CLKOUT3_PHASE = 90
|
---|
| 750 | PARAMETER C_CLKOUT3_BUF = TRUE
|
---|
| 751 | PARAMETER C_CLKOUT3_GROUP = MMCM0
|
---|
| 752 | PORT CLKIN = ad_refclk_in
|
---|
| 753 | PORT CLKOUT0 = clk_80MHz
|
---|
| 754 | PORT CLKOUT1 = clk_160MHz
|
---|
| 755 | PORT CLKOUT2 = clk_40MHz
|
---|
| 756 | PORT CLKOUT3 = clk_40MHz_90degphase
|
---|
| 757 | PORT RST = mmcm_inputs_invalid
|
---|
| 758 | PORT LOCKED = clk_gen_0_locked
|
---|
| 759 | END
|
---|
| 760 |
|
---|
| 761 | BEGIN clock_generator
|
---|
| 762 | PARAMETER INSTANCE = clock_generator_MPMC_Clocks
|
---|
| 763 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 764 | PARAMETER HW_VER = 4.03.a
|
---|
| 765 | # 80MHz clock input (driven by other clock generator)
|
---|
| 766 | PARAMETER C_CLKIN_FREQ = 80000000
|
---|
| 767 | # MPMC DRAM clock (2x bus)
|
---|
| 768 | PARAMETER C_CLKOUT0_FREQ = 320000000
|
---|
| 769 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
| 770 | PARAMETER C_CLKOUT0_GROUP = MMCM0
|
---|
| 771 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
| 772 | # MPMC DRAM clock (2x bus, variable phase)
|
---|
| 773 | PARAMETER C_CLKOUT1_FREQ = 320000000
|
---|
| 774 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
| 775 | PARAMETER C_CLKOUT1_GROUP = MMCM0
|
---|
| 776 | PARAMETER C_CLKOUT1_BUF = FALSE
|
---|
| 777 | PARAMETER C_CLKOUT1_VARIABLE_PHASE = TRUE
|
---|
| 778 | PARAMETER C_PSDONE_GROUP = MMCM0
|
---|
| 779 | PORT CLKIN = clk_80MHz
|
---|
| 780 | PORT PSCLK = clk_80MHz
|
---|
| 781 | PORT RST = mmcm_inputs_invalid
|
---|
| 782 | PORT LOCKED = clk_gen_2_locked
|
---|
[2080] | 783 | PORT CLKOUT0 = clock_generator_MPMC_Clocks_CLKOUT0
|
---|
| 784 | PORT CLKOUT1 = clock_generator_MPMC_Clocks_CLKOUT1
|
---|
| 785 | PORT PSEN = MMCM_PSEN
|
---|
| 786 | PORT PSINCDEC = MMCM_PSINCDEC
|
---|
| 787 | PORT PSDONE = clock_generator_MPMC_Clocks_PSDONE
|
---|
[1918] | 788 | END
|
---|
| 789 |
|
---|
[2382] | 790 | BEGIN util_reduced_logic
|
---|
| 791 | PARAMETER INSTANCE = clk_gen_locked_AND
|
---|
| 792 | PARAMETER HW_VER = 1.00.a
|
---|
| 793 | PARAMETER C_OPERATION = AND
|
---|
| 794 | PARAMETER C_SIZE = 3
|
---|
| 795 | PORT Op1 = clk_gen_0_locked & clk_gen_1_locked & clk_gen_2_locked
|
---|
| 796 | PORT Res = clk_gen_all_locked
|
---|
[1918] | 797 | END
|
---|
| 798 |
|
---|
[4195] | 799 | # ##############################################################################
|
---|
| 800 | # Microblaze
|
---|
| 801 | # ##############################################################################
|
---|
| 802 | BEGIN microblaze
|
---|
| 803 | PARAMETER INSTANCE = microblaze_0
|
---|
| 804 | PARAMETER HW_VER = 8.40.b
|
---|
| 805 | PARAMETER C_INTERCONNECT = 2
|
---|
| 806 | PARAMETER C_DEBUG_ENABLED = 1
|
---|
[4213] | 807 | PARAMETER C_USE_DCACHE = 1
|
---|
[4195] | 808 | PARAMETER C_USE_ICACHE = 0
|
---|
| 809 | # Little endian
|
---|
| 810 | PARAMETER C_ENDIANNESS = 1
|
---|
| 811 | # MMU Settings
|
---|
| 812 | PARAMETER C_USE_MMU = 0
|
---|
| 813 | PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1
|
---|
| 814 | PARAMETER C_ILL_OPCODE_EXCEPTION = 1
|
---|
| 815 | PARAMETER C_UNALIGNED_EXCEPTIONS = 1
|
---|
| 816 | PARAMETER C_OPCODE_0x0_ILLEGAL = 1
|
---|
| 817 | PARAMETER C_USE_BARREL = 1
|
---|
| 818 | PARAMETER C_PVR = 2
|
---|
| 819 | PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1
|
---|
| 820 | PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 1
|
---|
| 821 | PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1
|
---|
| 822 | PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1
|
---|
| 823 | PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 1
|
---|
| 824 | PARAMETER C_NUMBER_OF_PC_BRK = 4
|
---|
| 825 | PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2
|
---|
| 826 | PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2
|
---|
| 827 | PARAMETER C_CACHE_BYTE_SIZE = 128
|
---|
[4213] | 828 | PARAMETER C_ICACHE_BASEADDR = 0x80000000
|
---|
[4195] | 829 | PARAMETER C_ICACHE_HIGHADDR = 0xffffffff
|
---|
| 830 | PARAMETER C_ICACHE_ALWAYS_USED = 1
|
---|
| 831 | PARAMETER C_DCACHE_BYTE_SIZE = 128
|
---|
[4213] | 832 | PARAMETER C_DCACHE_BASEADDR = 0x80000000
|
---|
[4195] | 833 | PARAMETER C_DCACHE_HIGHADDR = 0xffffffff
|
---|
| 834 | PARAMETER C_DCACHE_ALWAYS_USED = 1
|
---|
| 835 | PARAMETER C_STREAM_INTERCONNECT = 1
|
---|
| 836 | PARAMETER C_INTERCONNECT_M_AXI_IC_AW_REGISTER = 1
|
---|
| 837 | PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 1
|
---|
| 838 | PARAMETER C_INTERCONNECT_M_AXI_IC_W_REGISTER = 1
|
---|
| 839 | PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 1
|
---|
| 840 | PARAMETER C_INTERCONNECT_M_AXI_IC_B_REGISTER = 1
|
---|
| 841 | PARAMETER C_ICACHE_FORCE_TAG_LUTRAM = 0
|
---|
| 842 | PARAMETER C_DCACHE_FORCE_TAG_LUTRAM = 0
|
---|
| 843 | PARAMETER C_USE_STACK_PROTECTION = 1
|
---|
[4213] | 844 | PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 0
|
---|
| 845 | PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 0
|
---|
| 846 | PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 0
|
---|
| 847 | PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 0
|
---|
| 848 | PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 0
|
---|
[4195] | 849 | BUS_INTERFACE DEBUG = microblaze_0_debug
|
---|
| 850 | BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
|
---|
[4213] | 851 | BUS_INTERFACE M_AXI_DP = axi_interconnect_periph_160
|
---|
[4195] | 852 | BUS_INTERFACE DLMB = microblaze_0_dlmb
|
---|
| 853 | BUS_INTERFACE ILMB = microblaze_0_ilmb
|
---|
[4213] | 854 | BUS_INTERFACE M_AXI_DC = axi_interconnect_core
|
---|
[4195] | 855 | PORT MB_RESET = proc_sys_reset_0_MB_Reset
|
---|
| 856 | PORT CLK = clk_160MHz
|
---|
| 857 | END
|
---|
| 858 |
|
---|
| 859 | BEGIN lmb_v10
|
---|
| 860 | PARAMETER INSTANCE = microblaze_0_ilmb
|
---|
| 861 | PARAMETER HW_VER = 2.00.b
|
---|
| 862 | PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
|
---|
| 863 | PORT LMB_CLK = clk_160MHz
|
---|
| 864 | END
|
---|
| 865 |
|
---|
| 866 | BEGIN lmb_bram_if_cntlr
|
---|
| 867 | PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
|
---|
| 868 | PARAMETER HW_VER = 3.10.c
|
---|
| 869 | PARAMETER C_BASEADDR = 0x00000000
|
---|
| 870 | PARAMETER C_HIGHADDR = 0x0001ffff
|
---|
| 871 | BUS_INTERFACE SLMB = microblaze_0_ilmb
|
---|
| 872 | BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
|
---|
| 873 | END
|
---|
| 874 |
|
---|
| 875 | BEGIN lmb_v10
|
---|
| 876 | PARAMETER INSTANCE = microblaze_0_dlmb
|
---|
| 877 | PARAMETER HW_VER = 2.00.b
|
---|
| 878 | PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
|
---|
| 879 | PORT LMB_CLK = clk_160MHz
|
---|
| 880 | END
|
---|
| 881 |
|
---|
| 882 | BEGIN lmb_bram_if_cntlr
|
---|
| 883 | PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
|
---|
| 884 | PARAMETER HW_VER = 3.10.c
|
---|
| 885 | PARAMETER C_BASEADDR = 0x00000000
|
---|
| 886 | PARAMETER C_HIGHADDR = 0x0001ffff
|
---|
| 887 | BUS_INTERFACE SLMB = microblaze_0_dlmb
|
---|
| 888 | BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
|
---|
| 889 | END
|
---|
| 890 |
|
---|
| 891 | BEGIN bram_block
|
---|
| 892 | PARAMETER INSTANCE = microblaze_0_bram_block
|
---|
| 893 | PARAMETER HW_VER = 1.00.a
|
---|
| 894 | BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
|
---|
| 895 | BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
|
---|
| 896 | END
|
---|
| 897 |
|
---|
| 898 | BEGIN mdm
|
---|
| 899 | PARAMETER INSTANCE = debug_module
|
---|
| 900 | PARAMETER HW_VER = 2.10.a
|
---|
| 901 | PARAMETER C_USE_UART = 0
|
---|
| 902 | BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
|
---|
| 903 | PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
|
---|
| 904 | PORT S_AXI_ACLK = clk_80MHz
|
---|
| 905 | PORT Interrupt = debug_module_Interrupt
|
---|
| 906 | END
|
---|
| 907 |
|
---|
| 908 | # ##############################################################################
|
---|
| 909 | # Peripherals
|
---|
| 910 | # ##############################################################################
|
---|
| 911 | BEGIN axi_uartlite
|
---|
| 912 | PARAMETER INSTANCE = usb_uart
|
---|
| 913 | PARAMETER HW_VER = 1.02.a
|
---|
| 914 | PARAMETER C_BAUDRATE = 115200
|
---|
[4213] | 915 | PARAMETER C_BASEADDR = 0x20800000
|
---|
| 916 | PARAMETER C_HIGHADDR = 0x2080FFFF
|
---|
[4195] | 917 | BUS_INTERFACE S_AXI = axi_interconnect_periph_80
|
---|
| 918 | PORT S_AXI_ACLK = clk_80MHz
|
---|
| 919 | PORT RX = axi_uartlite_0_RX
|
---|
[4306] | 920 | PORT TX = axi_uart_tx
|
---|
[4195] | 921 | PORT Interrupt = usb_uart_Interrupt
|
---|
| 922 | END
|
---|
| 923 |
|
---|
[1918] | 924 | BEGIN axi_timer
|
---|
| 925 | PARAMETER INSTANCE = axi_timer_0
|
---|
| 926 | PARAMETER HW_VER = 1.03.a
|
---|
[4213] | 927 | PARAMETER C_BASEADDR = 0x20700000
|
---|
| 928 | PARAMETER C_HIGHADDR = 0x2070FFFF
|
---|
[4185] | 929 | BUS_INTERFACE S_AXI = axi_interconnect_periph_80
|
---|
[2080] | 930 | PORT S_AXI_ACLK = clk_80MHz
|
---|
[4185] | 931 | PORT Interrupt = axi_timer_0_Interrupt
|
---|
[1918] | 932 | END
|
---|
| 933 |
|
---|
[2382] | 934 | BEGIN axi_sysmon_adc
|
---|
| 935 | PARAMETER INSTANCE = axi_sysmon_adc_0
|
---|
| 936 | PARAMETER HW_VER = 2.00.a
|
---|
| 937 | PARAMETER C_INCLUDE_INTR = 1
|
---|
[4213] | 938 | PARAMETER C_BASEADDR = 0x20600000
|
---|
| 939 | PARAMETER C_HIGHADDR = 0x2060FFFF
|
---|
[4185] | 940 | BUS_INTERFACE S_AXI = axi_interconnect_periph_80
|
---|
[2382] | 941 | PORT S_AXI_ACLK = clk_80MHz
|
---|
| 942 | PORT VAUXP = net_gnd
|
---|
| 943 | PORT VAUXN = net_gnd
|
---|
| 944 | PORT CONVST = net_gnd
|
---|
[4185] | 945 | PORT IP2INTC_Irpt = axi_sysmon_adc_0_IP2INTC_Irpt
|
---|
[2382] | 946 | END
|
---|
| 947 |
|
---|
| 948 | BEGIN axi_gpio
|
---|
| 949 | PARAMETER INSTANCE = axi_gpio_0
|
---|
| 950 | PARAMETER HW_VER = 1.01.b
|
---|
[4306] | 951 | # PARAMETER C_GPIO_WIDTH = 6
|
---|
| 952 | PARAMETER C_GPIO_WIDTH = 2
|
---|
[2382] | 953 | PARAMETER C_TRI_DEFAULT = 0x00000000
|
---|
[4213] | 954 | PARAMETER C_BASEADDR = 0x20500000
|
---|
| 955 | PARAMETER C_HIGHADDR = 0x2050FFFF
|
---|
[4185] | 956 | BUS_INTERFACE S_AXI = axi_interconnect_periph_80
|
---|
[2382] | 957 | PORT S_AXI_ACLK = clk_80MHz
|
---|
| 958 | PORT GPIO_IO = debug_sw_gpio
|
---|
| 959 | END
|
---|
| 960 |
|
---|
[4195] | 961 | BEGIN axi_intc
|
---|
| 962 | PARAMETER INSTANCE = axi_intc_0
|
---|
| 963 | PARAMETER HW_VER = 1.03.a
|
---|
[4213] | 964 | PARAMETER C_BASEADDR = 0x10000000
|
---|
| 965 | PARAMETER C_HIGHADDR = 0x1000FFFF
|
---|
[4195] | 966 | BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
|
---|
| 967 | BUS_INTERFACE S_AXI = axi_interconnect_periph_160
|
---|
[4233] | 968 | PORT Intr = usb_uart_Interrupt & ETH_B_DMA_s2mm_introut & ETH_B_DMA_mm2s_introut & ETH_B_MAC_INTERRUPT & ETH_A_DMA_s2mm_introut & ETH_A_DMA_mm2s_introut & ETH_A_MAC_INTERRUPT & warplab_buffers_rf_tx_iq_int & warplab_buffers_rf_rx_iq_rssi_int & axi_cdma_0_cdma_introut & axi_timer_0_Interrupt
|
---|
[4195] | 969 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 970 | END
|
---|
| 971 |
|
---|
[2382] | 972 | BEGIN axi_cdma
|
---|
| 973 | PARAMETER INSTANCE = axi_cdma_0
|
---|
| 974 | PARAMETER HW_VER = 3.04.a
|
---|
[4225] | 975 | PARAMETER C_ENABLE_KEYHOLE = 0
|
---|
| 976 | PARAMETER C_M_AXI_DATA_WIDTH = 128
|
---|
[4213] | 977 | PARAMETER C_BASEADDR = 0x12000000
|
---|
| 978 | PARAMETER C_HIGHADDR = 0x1200FFFF
|
---|
| 979 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 0
|
---|
| 980 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 0
|
---|
| 981 | PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 0
|
---|
| 982 | PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 0
|
---|
| 983 | PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 0
|
---|
[4185] | 984 | PARAMETER C_INTERCONNECT_M_AXI_AW_REGISTER = 1
|
---|
| 985 | PARAMETER C_INTERCONNECT_M_AXI_AR_REGISTER = 1
|
---|
| 986 | PARAMETER C_INTERCONNECT_M_AXI_W_REGISTER = 1
|
---|
| 987 | PARAMETER C_INTERCONNECT_M_AXI_R_REGISTER = 1
|
---|
| 988 | PARAMETER C_INTERCONNECT_M_AXI_B_REGISTER = 1
|
---|
| 989 | PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 1
|
---|
| 990 | PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 1
|
---|
| 991 | PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 1
|
---|
| 992 | PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 1
|
---|
| 993 | PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 1
|
---|
| 994 | PARAMETER C_INCLUDE_SG = 1
|
---|
[4225] | 995 | PARAMETER C_M_AXI_MAX_BURST_LEN = 64
|
---|
[4185] | 996 | BUS_INTERFACE M_AXI = axi_interconnect_core
|
---|
| 997 | BUS_INTERFACE M_AXI_SG = axi_interconnect_core
|
---|
| 998 | BUS_INTERFACE S_AXI_LITE = axi_interconnect_periph_160
|
---|
| 999 | PORT s_axi_lite_aclk = clk_160MHz
|
---|
[2382] | 1000 | PORT m_axi_aclk = clk_160MHz
|
---|
[4185] | 1001 | PORT cdma_introut = axi_cdma_0_cdma_introut
|
---|
[2382] | 1002 | END
|
---|
| 1003 |
|
---|
| 1004 | BEGIN bram_block
|
---|
| 1005 | PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block_1
|
---|
| 1006 | PARAMETER HW_VER = 1.00.a
|
---|
| 1007 | BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA
|
---|
| 1008 | BUS_INTERFACE PORTB = axi_bram_ctrl_0_BRAM_PORTB
|
---|
| 1009 | END
|
---|
| 1010 |
|
---|
| 1011 | BEGIN axi_bram_ctrl
|
---|
| 1012 | PARAMETER INSTANCE = axi_bram_0
|
---|
| 1013 | PARAMETER HW_VER = 1.03.a
|
---|
[4213] | 1014 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi_cdma_0.M_AXI_SG & axi_cdma_0.M_AXI & axi2axi_connector_2.M_AXI & axi2axi_connector_3.M_AXI & axi2axi_connector_4.M_AXI
|
---|
[4225] | 1015 | PARAMETER C_S_AXI_DATA_WIDTH = 128
|
---|
[2382] | 1016 | PARAMETER C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE = 4
|
---|
| 1017 | PARAMETER C_INTERCONNECT_S_AXI_READ_ACCEPTANCE = 4
|
---|
[4185] | 1018 | PARAMETER C_S_AXI_BASEADDR = 0x50000000
|
---|
| 1019 | PARAMETER C_S_AXI_HIGHADDR = 0x5001FFFF
|
---|
[4306] | 1020 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 1021 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 1022 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 1023 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 1024 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
[4185] | 1025 | BUS_INTERFACE S_AXI = axi_interconnect_core
|
---|
[2382] | 1026 | BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA
|
---|
| 1027 | BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_BRAM_PORTB
|
---|
| 1028 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1029 | END
|
---|
| 1030 |
|
---|
[4195] | 1031 | # ##############################################################################
|
---|
| 1032 | # Ethernet / Ethernet DMAs
|
---|
| 1033 | # ##############################################################################
|
---|
[1918] | 1034 | BEGIN axi_ethernet
|
---|
| 1035 | PARAMETER INSTANCE = ETH_A_MAC
|
---|
| 1036 | PARAMETER HW_VER = 3.01.a
|
---|
| 1037 | PARAMETER C_PHYADDR = 0B00110
|
---|
| 1038 | PARAMETER C_INCLUDE_IO = 1
|
---|
| 1039 | PARAMETER C_TYPE = 2
|
---|
| 1040 | PARAMETER C_PHY_TYPE = 3
|
---|
| 1041 | PARAMETER C_HALFDUP = 0
|
---|
[1995] | 1042 | PARAMETER C_TXMEM = 16384
|
---|
| 1043 | PARAMETER C_RXMEM = 16384
|
---|
[1918] | 1044 | PARAMETER C_TXCSUM = 2
|
---|
| 1045 | PARAMETER C_RXCSUM = 2
|
---|
| 1046 | PARAMETER C_TXVLAN_TRAN = 0
|
---|
| 1047 | PARAMETER C_RXVLAN_TRAN = 0
|
---|
| 1048 | PARAMETER C_TXVLAN_TAG = 0
|
---|
| 1049 | PARAMETER C_RXVLAN_TAG = 0
|
---|
| 1050 | PARAMETER C_TXVLAN_STRP = 0
|
---|
| 1051 | PARAMETER C_RXVLAN_STRP = 0
|
---|
| 1052 | PARAMETER C_MCAST_EXTEND = 0
|
---|
| 1053 | PARAMETER C_STATS = 0
|
---|
| 1054 | PARAMETER C_AVB = 0
|
---|
[4213] | 1055 | PARAMETER C_BASEADDR = 0x11000000
|
---|
| 1056 | PARAMETER C_HIGHADDR = 0x1103FFFF
|
---|
[4185] | 1057 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 0
|
---|
| 1058 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 0
|
---|
| 1059 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 0
|
---|
| 1060 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 0
|
---|
| 1061 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 0
|
---|
| 1062 | BUS_INTERFACE S_AXI = axi_interconnect_periph_160
|
---|
[2080] | 1063 | BUS_INTERFACE AXI_STR_RXD = ETH_A_MAC_AXI_STR_RXD
|
---|
| 1064 | BUS_INTERFACE AXI_STR_RXS = ETH_A_MAC_AXI_STR_RXS
|
---|
| 1065 | BUS_INTERFACE AXI_STR_TXC = ETH_A_DMA_M_AXIS_MM2S_CNTRL
|
---|
| 1066 | BUS_INTERFACE AXI_STR_TXD = ETH_A_DMA_M_AXIS_MM2S
|
---|
[1918] | 1067 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1068 | PORT GTX_CLK = clk_125MHz
|
---|
| 1069 | PORT PHY_RST_N = ETH_A_PHY_RST_N
|
---|
| 1070 | PORT MDIO = ETH_A_MDIO
|
---|
| 1071 | PORT MDC = ETH_A_MDC
|
---|
| 1072 | PORT REF_CLK = clk_200MHz
|
---|
| 1073 | PORT AXI_STR_TXD_ACLK = clk_160MHz
|
---|
| 1074 | PORT AXI_STR_TXC_ACLK = clk_160MHz
|
---|
| 1075 | PORT AXI_STR_RXD_ACLK = clk_160MHz
|
---|
| 1076 | PORT AXI_STR_RXS_ACLK = clk_160MHz
|
---|
| 1077 | PORT AXI_STR_RXS_TREADY = net_vcc
|
---|
| 1078 | PORT RGMII_TXD = ETH_A_RGMII_TXD
|
---|
| 1079 | PORT RGMII_TX_CTL = ETH_A_RGMII_TX_CTL
|
---|
| 1080 | PORT RGMII_TXC = ETH_A_RGMII_TXC
|
---|
| 1081 | PORT RGMII_RXD = ETH_A_RGMII_RXD
|
---|
| 1082 | PORT RGMII_RX_CTL = ETH_A_RGMII_RX_CTL
|
---|
| 1083 | PORT RGMII_RXC = ETH_A_RGMII_RXC
|
---|
[4185] | 1084 | PORT INTERRUPT = ETH_A_MAC_INTERRUPT
|
---|
[1918] | 1085 | END
|
---|
| 1086 |
|
---|
[2080] | 1087 | BEGIN axi_dma
|
---|
| 1088 | PARAMETER INSTANCE = ETH_A_DMA
|
---|
| 1089 | PARAMETER HW_VER = 6.03.a
|
---|
| 1090 | PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1
|
---|
| 1091 | PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 64
|
---|
| 1092 | PARAMETER C_M_AXI_S2MM_DATA_WIDTH = 64
|
---|
[4213] | 1093 | PARAMETER C_BASEADDR = 0x11200000
|
---|
| 1094 | PARAMETER C_HIGHADDR = 0x1120FFFF
|
---|
[4185] | 1095 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 0
|
---|
| 1096 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 0
|
---|
| 1097 | PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 0
|
---|
| 1098 | PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 0
|
---|
| 1099 | PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 0
|
---|
| 1100 | PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 0
|
---|
| 1101 | PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 0
|
---|
| 1102 | PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 0
|
---|
| 1103 | PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 0
|
---|
| 1104 | PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 0
|
---|
| 1105 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 0
|
---|
| 1106 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 0
|
---|
| 1107 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 0
|
---|
| 1108 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 0
|
---|
| 1109 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 0
|
---|
| 1110 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 0
|
---|
| 1111 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 0
|
---|
| 1112 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 0
|
---|
| 1113 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 0
|
---|
| 1114 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 0
|
---|
| 1115 | BUS_INTERFACE S_AXI_LITE = axi_interconnect_periph_160
|
---|
| 1116 | BUS_INTERFACE M_AXI_SG = axi_interconnect_dma
|
---|
| 1117 | BUS_INTERFACE M_AXI_MM2S = axi_interconnect_dma
|
---|
| 1118 | BUS_INTERFACE M_AXI_S2MM = axi_interconnect_dma
|
---|
[2080] | 1119 | BUS_INTERFACE S_AXIS_S2MM = ETH_A_MAC_AXI_STR_RXD
|
---|
| 1120 | BUS_INTERFACE S_AXIS_S2MM_STS = ETH_A_MAC_AXI_STR_RXS
|
---|
| 1121 | BUS_INTERFACE M_AXIS_MM2S_CNTRL = ETH_A_DMA_M_AXIS_MM2S_CNTRL
|
---|
| 1122 | BUS_INTERFACE M_AXIS_MM2S = ETH_A_DMA_M_AXIS_MM2S
|
---|
| 1123 | PORT s_axi_lite_aclk = clk_160MHz
|
---|
| 1124 | PORT m_axi_sg_aclk = clk_160MHz
|
---|
| 1125 | PORT m_axi_mm2s_aclk = clk_160MHz
|
---|
| 1126 | PORT m_axi_s2mm_aclk = clk_160MHz
|
---|
[4185] | 1127 | PORT mm2s_introut = ETH_A_DMA_mm2s_introut
|
---|
| 1128 | PORT s2mm_introut = ETH_A_DMA_s2mm_introut
|
---|
[2080] | 1129 | END
|
---|
| 1130 |
|
---|
[1918] | 1131 | BEGIN axi_ethernet
|
---|
| 1132 | PARAMETER INSTANCE = ETH_B_MAC
|
---|
| 1133 | PARAMETER HW_VER = 3.01.a
|
---|
| 1134 | PARAMETER C_PHYADDR = 0B00111
|
---|
| 1135 | PARAMETER C_INCLUDE_IO = 1
|
---|
| 1136 | PARAMETER C_TYPE = 2
|
---|
| 1137 | PARAMETER C_PHY_TYPE = 3
|
---|
| 1138 | PARAMETER C_HALFDUP = 0
|
---|
[4760] | 1139 | PARAMETER C_TXMEM = 16384
|
---|
| 1140 | PARAMETER C_RXMEM = 16384
|
---|
[1918] | 1141 | PARAMETER C_TXCSUM = 2
|
---|
| 1142 | PARAMETER C_RXCSUM = 2
|
---|
| 1143 | PARAMETER C_TXVLAN_TRAN = 0
|
---|
| 1144 | PARAMETER C_RXVLAN_TRAN = 0
|
---|
| 1145 | PARAMETER C_TXVLAN_TAG = 0
|
---|
| 1146 | PARAMETER C_RXVLAN_TAG = 0
|
---|
| 1147 | PARAMETER C_TXVLAN_STRP = 0
|
---|
| 1148 | PARAMETER C_RXVLAN_STRP = 0
|
---|
| 1149 | PARAMETER C_MCAST_EXTEND = 0
|
---|
| 1150 | PARAMETER C_STATS = 0
|
---|
| 1151 | PARAMETER C_AVB = 0
|
---|
[4213] | 1152 | PARAMETER C_BASEADDR = 0x11100000
|
---|
| 1153 | PARAMETER C_HIGHADDR = 0x1113FFFF
|
---|
[4185] | 1154 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 0
|
---|
| 1155 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 0
|
---|
| 1156 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 0
|
---|
| 1157 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 0
|
---|
| 1158 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 0
|
---|
| 1159 | BUS_INTERFACE S_AXI = axi_interconnect_periph_160
|
---|
| 1160 | BUS_INTERFACE AXI_STR_RXD = ETH_B_MAC_AXI_STR_RXD
|
---|
| 1161 | BUS_INTERFACE AXI_STR_RXS = ETH_B_MAC_AXI_STR_RXS
|
---|
| 1162 | BUS_INTERFACE AXI_STR_TXC = ETH_B_DMA_M_AXIS_MM2S_CNTRL
|
---|
| 1163 | BUS_INTERFACE AXI_STR_TXD = ETH_B_DMA_M_AXIS_MM2S
|
---|
[1918] | 1164 | PORT S_AXI_ACLK = clk_160MHz
|
---|
| 1165 | PORT GTX_CLK = clk_125MHz
|
---|
| 1166 | # PORT PHY_RST_N = ETH_B_PHY_RST_N #88e1121R has single reset port; let ETH_A handle it
|
---|
| 1167 | PORT MDIO = ETH_B_MDIO
|
---|
| 1168 | PORT MDC = ETH_B_MDC
|
---|
| 1169 | PORT REF_CLK = clk_200MHz
|
---|
| 1170 | PORT AXI_STR_TXD_ACLK = clk_160MHz
|
---|
| 1171 | PORT AXI_STR_TXC_ACLK = clk_160MHz
|
---|
| 1172 | PORT AXI_STR_RXD_ACLK = clk_160MHz
|
---|
| 1173 | PORT AXI_STR_RXS_ACLK = clk_160MHz
|
---|
| 1174 | PORT AXI_STR_RXS_TREADY = net_vcc
|
---|
| 1175 | PORT RGMII_TXD = ETH_B_RGMII_TXD
|
---|
| 1176 | PORT RGMII_TX_CTL = ETH_B_RGMII_TX_CTL
|
---|
| 1177 | PORT RGMII_TXC = ETH_B_RGMII_TXC
|
---|
| 1178 | PORT RGMII_RXD = ETH_B_RGMII_RXD
|
---|
| 1179 | PORT RGMII_RX_CTL = ETH_B_RGMII_RX_CTL
|
---|
| 1180 | PORT RGMII_RXC = ETH_B_RGMII_RXC
|
---|
[4185] | 1181 | PORT INTERRUPT = ETH_B_MAC_INTERRUPT
|
---|
[1918] | 1182 | END
|
---|
| 1183 |
|
---|
[4185] | 1184 | BEGIN axi_dma
|
---|
| 1185 | PARAMETER INSTANCE = ETH_B_DMA
|
---|
| 1186 | PARAMETER HW_VER = 6.03.a
|
---|
| 1187 | PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1
|
---|
| 1188 | PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 64
|
---|
| 1189 | PARAMETER C_M_AXI_S2MM_DATA_WIDTH = 64
|
---|
[4213] | 1190 | PARAMETER C_BASEADDR = 0x11300000
|
---|
| 1191 | PARAMETER C_HIGHADDR = 0x1130FFFF
|
---|
[4185] | 1192 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 0
|
---|
| 1193 | PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 0
|
---|
| 1194 | PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 0
|
---|
| 1195 | PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 0
|
---|
| 1196 | PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 0
|
---|
| 1197 | PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 0
|
---|
| 1198 | PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 0
|
---|
| 1199 | PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 0
|
---|
| 1200 | PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 0
|
---|
| 1201 | PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 0
|
---|
| 1202 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 0
|
---|
| 1203 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 0
|
---|
| 1204 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 0
|
---|
| 1205 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 0
|
---|
| 1206 | PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 0
|
---|
| 1207 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 0
|
---|
| 1208 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 0
|
---|
| 1209 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 0
|
---|
| 1210 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 0
|
---|
| 1211 | PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 0
|
---|
| 1212 | BUS_INTERFACE S_AXI_LITE = axi_interconnect_periph_160
|
---|
| 1213 | BUS_INTERFACE M_AXI_SG = axi_interconnect_dma
|
---|
| 1214 | BUS_INTERFACE M_AXI_MM2S = axi_interconnect_dma
|
---|
| 1215 | BUS_INTERFACE M_AXI_S2MM = axi_interconnect_dma
|
---|
| 1216 | BUS_INTERFACE S_AXIS_S2MM = ETH_B_MAC_AXI_STR_RXD
|
---|
| 1217 | BUS_INTERFACE S_AXIS_S2MM_STS = ETH_B_MAC_AXI_STR_RXS
|
---|
| 1218 | BUS_INTERFACE M_AXIS_MM2S_CNTRL = ETH_B_DMA_M_AXIS_MM2S_CNTRL
|
---|
| 1219 | BUS_INTERFACE M_AXIS_MM2S = ETH_B_DMA_M_AXIS_MM2S
|
---|
| 1220 | PORT s_axi_lite_aclk = clk_160MHz
|
---|
| 1221 | PORT m_axi_sg_aclk = clk_160MHz
|
---|
| 1222 | PORT m_axi_mm2s_aclk = clk_160MHz
|
---|
| 1223 | PORT m_axi_s2mm_aclk = clk_160MHz
|
---|
| 1224 | PORT mm2s_introut = ETH_B_DMA_mm2s_introut
|
---|
| 1225 | PORT s2mm_introut = ETH_B_DMA_s2mm_introut
|
---|
[1918] | 1226 | END
|
---|
| 1227 |
|
---|
[4195] | 1228 | # ##############################################################################
|
---|
| 1229 | # DDR
|
---|
| 1230 | # ##############################################################################
|
---|
[2080] | 1231 | BEGIN axi_v6_ddrx
|
---|
| 1232 | PARAMETER INSTANCE = DDR3_SODIMM
|
---|
| 1233 | PARAMETER HW_VER = 1.06.a
|
---|
| 1234 | PARAMETER C_MEM_PARTNO = MT8JSF25664HZ-1G4
|
---|
| 1235 | PARAMETER C_CK_WIDTH = 2
|
---|
| 1236 | PARAMETER C_ROW_WIDTH = 15
|
---|
| 1237 | PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y0
|
---|
| 1238 | # Manually entered params (extracted from MIG-ISE test design that worked in hardware)
|
---|
| 1239 | PARAMETER C_NDQS_COL0 = 5
|
---|
| 1240 | PARAMETER C_NDQS_COL1 = 3
|
---|
| 1241 | PARAMETER C_NDQS_COL2 = 0
|
---|
| 1242 | PARAMETER C_NDQS_COL3 = 0
|
---|
| 1243 | PARAMETER C_DQS_LOC_COL0 = 0x0403020100
|
---|
| 1244 | PARAMETER C_DQS_LOC_COL1 = 0x0000070605
|
---|
| 1245 | PARAMETER C_ECC = OFF
|
---|
| 1246 | # END Manually entered params
|
---|
| 1247 | PARAMETER C_TCK = 3125
|
---|
[4213] | 1248 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & axi_cdma_0.M_AXI & axi2axi_connector_3.M_AXI & axi2axi_connector_4.M_AXI
|
---|
[4225] | 1249 | PARAMETER C_S_AXI_DATA_WIDTH = 128
|
---|
[4185] | 1250 | PARAMETER C_S_AXI_BASEADDR = 0x80000000
|
---|
| 1251 | PARAMETER C_S_AXI_HIGHADDR = 0xFFFFFFFF
|
---|
| 1252 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 1253 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 1254 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 1255 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 1256 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
| 1257 | BUS_INTERFACE S_AXI = axi_interconnect_core
|
---|
[2080] | 1258 | PORT clk = clk_160MHz
|
---|
| 1259 | PORT clk_mem = clock_generator_MPMC_Clocks_CLKOUT0
|
---|
| 1260 | PORT clk_rd_base = clock_generator_MPMC_Clocks_CLKOUT1
|
---|
| 1261 | PORT clk_ref = clk_200MHz
|
---|
| 1262 | PORT pd_PSEN = MMCM_PSEN
|
---|
| 1263 | PORT pd_PSINCDEC = MMCM_PSINCDEC
|
---|
| 1264 | PORT pd_PSDONE = clock_generator_MPMC_Clocks_PSDONE
|
---|
| 1265 | PORT ddr_ck_p = ddr3_sodimm_ck_p
|
---|
| 1266 | PORT ddr_ck_n = ddr3_sodimm_ck_n
|
---|
| 1267 | PORT ddr_cke = ddr3_sodimm_cke
|
---|
| 1268 | PORT ddr_cs_n = ddr3_sodimm_cs_n
|
---|
| 1269 | PORT ddr_odt = ddr3_sodimm_odt
|
---|
| 1270 | PORT ddr_ras_n = ddr3_sodimm_ras_n
|
---|
| 1271 | PORT ddr_cas_n = ddr3_sodimm_cas_n
|
---|
| 1272 | PORT ddr_we_n = ddr3_sodimm_we_n
|
---|
| 1273 | PORT ddr_ba = ddr3_sodimm_ba
|
---|
| 1274 | PORT ddr_addr = ddr3_sodimm_addr
|
---|
| 1275 | PORT ddr_dq = ddr3_sodimm_dq
|
---|
| 1276 | PORT ddr_dm = ddr3_sodimm_dm
|
---|
| 1277 | PORT ddr_reset_n = ddr3_sodimm_reset_n
|
---|
| 1278 | PORT ddr_dqs_p = ddr3_sodimm_dqs_p
|
---|
| 1279 | PORT ddr_dqs_n = ddr3_sodimm_dqs_n
|
---|
[4195] | 1280 | PORT phy_init_done = dram_init_done
|
---|
[2080] | 1281 | END
|
---|
| 1282 |
|
---|
[4195] | 1283 | # ##############################################################################
|
---|
| 1284 | # Interconnect
|
---|
| 1285 | # ##############################################################################
|
---|
[4185] | 1286 | BEGIN axi_interconnect
|
---|
[4195] | 1287 | PARAMETER INSTANCE = axi_interconnect_buffers
|
---|
| 1288 | PARAMETER HW_VER = 1.06.a
|
---|
| 1289 | PORT INTERCONNECT_ACLK = clk_160MHz
|
---|
| 1290 | PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
|
---|
| 1291 | END
|
---|
| 1292 |
|
---|
| 1293 | BEGIN axi_interconnect
|
---|
| 1294 | PARAMETER INSTANCE = axi_interconnect_core
|
---|
| 1295 | PARAMETER HW_VER = 1.06.a
|
---|
[4225] | 1296 | PARAMETER C_INTERCONNECT_DATA_WIDTH = 128
|
---|
[4195] | 1297 | PORT INTERCONNECT_ACLK = clk_160MHz
|
---|
| 1298 | PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
|
---|
| 1299 | END
|
---|
| 1300 |
|
---|
| 1301 | BEGIN axi_interconnect
|
---|
[4185] | 1302 | PARAMETER INSTANCE = axi_interconnect_periph_160
|
---|
| 1303 | PARAMETER HW_VER = 1.06.a
|
---|
| 1304 | PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
|
---|
| 1305 | PORT INTERCONNECT_ACLK = clk_160MHz
|
---|
| 1306 | PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
|
---|
| 1307 | END
|
---|
| 1308 |
|
---|
[4195] | 1309 | BEGIN axi_interconnect
|
---|
| 1310 | PARAMETER INSTANCE = axi_interconnect_periph_80
|
---|
| 1311 | PARAMETER HW_VER = 1.06.a
|
---|
| 1312 | PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
|
---|
| 1313 | PORT INTERCONNECT_ACLK = clk_80MHz
|
---|
| 1314 | PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
|
---|
| 1315 | END
|
---|
| 1316 |
|
---|
| 1317 | BEGIN axi_interconnect
|
---|
| 1318 | PARAMETER INSTANCE = axi_interconnect_dma
|
---|
| 1319 | PARAMETER HW_VER = 1.06.a
|
---|
| 1320 | PARAMETER C_INTERCONNECT_DATA_WIDTH = 64
|
---|
| 1321 | PORT INTERCONNECT_ACLK = clk_160MHz
|
---|
| 1322 | PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
|
---|
| 1323 | END
|
---|
| 1324 |
|
---|
[4185] | 1325 | BEGIN axi2axi_connector
|
---|
[4195] | 1326 | PARAMETER INSTANCE = axi2axi_connector_1
|
---|
| 1327 | PARAMETER HW_VER = 1.00.a
|
---|
[4213] | 1328 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi_cdma_0.M_AXI & axi2axi_connector_2.M_AXI & axi2axi_connector_3.M_AXI & axi2axi_connector_4.M_AXI
|
---|
| 1329 | PARAMETER C_S_AXI_RNG00_BASEADDR = 0x40000000
|
---|
| 1330 | PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x4FFFFFFF
|
---|
[4195] | 1331 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 1332 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 1333 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 1334 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 1335 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
| 1336 | BUS_INTERFACE S_AXI = axi_interconnect_core
|
---|
| 1337 | BUS_INTERFACE M_AXI = axi_interconnect_buffers
|
---|
| 1338 | END
|
---|
| 1339 |
|
---|
| 1340 | BEGIN axi2axi_connector
|
---|
[4185] | 1341 | PARAMETER INSTANCE = axi2axi_connector_2
|
---|
| 1342 | PARAMETER HW_VER = 1.00.a
|
---|
[4213] | 1343 | PARAMETER C_S_AXI_RNG00_BASEADDR = 0x40000000
|
---|
| 1344 | PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x7FFFFFFF
|
---|
[4185] | 1345 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 1346 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 1347 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 1348 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 1349 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
| 1350 | PARAMETER C_S_AXI_PROTOCOL = AXI4LITE
|
---|
[4213] | 1351 | BUS_INTERFACE M_AXI = axi_interconnect_core
|
---|
| 1352 | BUS_INTERFACE S_AXI = axi_interconnect_periph_160
|
---|
[4185] | 1353 | END
|
---|
| 1354 |
|
---|
| 1355 | BEGIN axi2axi_connector
|
---|
| 1356 | PARAMETER INSTANCE = axi2axi_connector_3
|
---|
| 1357 | PARAMETER HW_VER = 1.00.a
|
---|
| 1358 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ETH_A_DMA.M_AXI_SG & ETH_A_DMA.M_AXI_MM2S & ETH_A_DMA.M_AXI_S2MM
|
---|
| 1359 | PARAMETER C_S_AXI_RNG00_BASEADDR = 0x00000000
|
---|
| 1360 | PARAMETER C_S_AXI_RNG00_HIGHADDR = 0xFFFFFFFF
|
---|
| 1361 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 1362 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 1363 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 1364 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 1365 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
| 1366 | BUS_INTERFACE S_AXI = axi_interconnect_dma
|
---|
| 1367 | BUS_INTERFACE M_AXI = axi_interconnect_core
|
---|
| 1368 | END
|
---|
| 1369 |
|
---|
| 1370 | BEGIN axi2axi_connector
|
---|
| 1371 | PARAMETER INSTANCE = axi2axi_connector_4
|
---|
| 1372 | PARAMETER HW_VER = 1.00.a
|
---|
| 1373 | PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ETH_B_DMA.M_AXI_SG & ETH_B_DMA.M_AXI_MM2S & ETH_B_DMA.M_AXI_S2MM
|
---|
| 1374 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 1375 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 1376 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 1377 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 1378 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
| 1379 | PARAMETER C_S_AXI_RNG00_BASEADDR = 0x00000000
|
---|
| 1380 | PARAMETER C_S_AXI_RNG00_HIGHADDR = 0xFFFFFFFF
|
---|
| 1381 | BUS_INTERFACE S_AXI = axi_interconnect_dma
|
---|
| 1382 | BUS_INTERFACE M_AXI = axi_interconnect_core
|
---|
| 1383 | END
|
---|
| 1384 |
|
---|
| 1385 | BEGIN axi2axi_connector
|
---|
| 1386 | PARAMETER INSTANCE = axi2axi_connector_5
|
---|
| 1387 | PARAMETER HW_VER = 1.00.a
|
---|
[4213] | 1388 | PARAMETER C_S_AXI_RNG00_BASEADDR = 0x20000000
|
---|
| 1389 | PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x2FFFFFFF
|
---|
[4185] | 1390 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
---|
| 1391 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
---|
| 1392 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
---|
| 1393 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
---|
| 1394 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
---|
| 1395 | PARAMETER C_S_AXI_PROTOCOL = AXI4LITE
|
---|
| 1396 | BUS_INTERFACE S_AXI = axi_interconnect_periph_160
|
---|
| 1397 | BUS_INTERFACE M_AXI = axi_interconnect_periph_80
|
---|
| 1398 | END
|
---|
[4233] | 1399 |
|
---|