source: ResearchApps/PHY/WARPLAB/WARPLab_v06_1/EDK_Files_MIMO_2x2_FPGAv2/system.mhs

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd
# Thu Jun 28 08:17:23 2012
# Target Board:  Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 2.2 / Radio 1.4 / Clock 1.1 (XPS 13 version)
# Family:    virtex4
# Device:    XC4VFX100
# Package:   FF1517
# Speed Grade:  -11
# Processor number: 1
# Processor 1: ppc405_0
# Processor clock frequency: 160.0
# Bus clock frequency: 80.0
# Debug Interface: FPGA JTAG
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_UserIO_LEDs_out_pin = fpga_0_UserIO_LEDs_out_pin, DIR = O, VEC = [0:7]
 PORT fpga_0_UserIO_IOEx_SDA_pin = fpga_0_UserIO_IOEx_SDA_pin, DIR = O
 PORT fpga_0_UserIO_IOEx_SCL_pin = fpga_0_UserIO_IOEx_SCL_pin, DIR = O
 PORT fpga_0_UserIO_PB_in_pin = fpga_0_UserIO_PB_in_pin, DIR = I, VEC = [0:3]
 PORT fpga_0_UserIO_DIPSW_in_pin = fpga_0_UserIO_DIPSW_in_pin, DIR = I, VEC = [0:3]
 PORT fpga_0_rs232_db9_RX_pin = fpga_0_rs232_db9_RX_pin, DIR = I
 PORT fpga_0_rs232_db9_TX_pin = fpga_0_rs232_db9_TX_pin, DIR = O
 PORT fpga_0_rs232_usb_RX_pin = fpga_0_rs232_usb_RX_pin, DIR = I
 PORT fpga_0_rs232_usb_TX_pin = fpga_0_rs232_usb_TX_pin, DIR = O
 PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin, DIR = O
 PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin, DIR = I
 PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin, DIR = O, VEC = [7:0]
 PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin, DIR = O
 PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin, DIR = O
 PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin, DIR = O
 PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin, DIR = I, VEC = [7:0]
 PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin, DIR = I
 PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin, DIR = I
 PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin, DIR = I
 PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0_pin, DIR = O
 PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0_pin, DIR = IO
 PORT fpga_0_clk_board_config_sys_clk_pin = fpga_0_clk_board_config_sys_clk_pin, DIR = I
 PORT fpga_0_clk_board_config_cfg_radio_dat_out_pin = fpga_0_clk_board_config_cfg_radio_dat_out_pin, DIR = O
 PORT fpga_0_clk_board_config_cfg_radio_csb_out_pin = fpga_0_clk_board_config_cfg_radio_csb_out_pin, DIR = O
 PORT fpga_0_clk_board_config_cfg_radio_en_out_pin = fpga_0_clk_board_config_cfg_radio_en_out_pin, DIR = O
 PORT fpga_0_clk_board_config_cfg_radio_clk_out_pin = fpga_0_clk_board_config_cfg_radio_clk_out_pin, DIR = O
 PORT fpga_0_clk_board_config_cfg_logic_dat_out_pin = fpga_0_clk_board_config_cfg_logic_dat_out_pin, DIR = O
 PORT fpga_0_clk_board_config_cfg_logic_csb_out_pin = fpga_0_clk_board_config_cfg_logic_csb_out_pin, DIR = O
 PORT fpga_0_clk_board_config_cfg_logic_en_out_pin = fpga_0_clk_board_config_cfg_logic_en_out_pin, DIR = O
 PORT fpga_0_clk_board_config_cfg_logic_clk_out_pin = fpga_0_clk_board_config_cfg_logic_clk_out_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_converter_clock_out_pin = fpga_0_radio_bridge_slot_2_converter_clock_out_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_DAC_I_pin = fpga_0_radio_bridge_slot_2_radio_DAC_I_pin, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_2_radio_ADC_I_pin = fpga_0_radio_bridge_slot_2_radio_ADC_I_pin, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_2_radio_B_pin = fpga_0_radio_bridge_slot_2_radio_B_pin, DIR = O, VEC = [6:0]
 PORT fpga_0_radio_bridge_slot_2_radio_ANTSW_pin = fpga_0_radio_bridge_slot_2_radio_ANTSW_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_radio_bridge_slot_2_radio_LED_pin = fpga_0_radio_bridge_slot_2_radio_LED_pin, DIR = O, VEC = [2:0]
 PORT fpga_0_radio_bridge_slot_2_radio_DIPSW_pin = fpga_0_radio_bridge_slot_2_radio_DIPSW_pin, DIR = I, VEC = [3:0]
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0]
 PORT fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin, DIR = IO
 PORT fpga_0_radio_bridge_slot_2_radio_spi_clk_pin = fpga_0_radio_bridge_slot_2_radio_spi_clk_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_spi_data_pin = fpga_0_radio_bridge_slot_2_radio_spi_data_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_spi_cs_pin = fpga_0_radio_bridge_slot_2_radio_spi_cs_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_SHDN_pin = fpga_0_radio_bridge_slot_2_radio_SHDN_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_TxEn_pin = fpga_0_radio_bridge_slot_2_radio_TxEn_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RxEn_pin = fpga_0_radio_bridge_slot_2_radio_RxEn_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RxHP_pin = fpga_0_radio_bridge_slot_2_radio_RxHP_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_24PA_pin = fpga_0_radio_bridge_slot_2_radio_24PA_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_5PA_pin = fpga_0_radio_bridge_slot_2_radio_5PA_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_LD_pin = fpga_0_radio_bridge_slot_2_radio_LD_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_dac_spi_data_pin = fpga_0_radio_bridge_slot_2_dac_spi_data_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_dac_spi_cs_pin = fpga_0_radio_bridge_slot_2_dac_spi_cs_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_2_dac_spi_clk_pin = fpga_0_radio_bridge_slot_2_dac_spi_clk_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_converter_clock_out_pin = fpga_0_radio_bridge_slot_3_converter_clock_out_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_DAC_I_pin = fpga_0_radio_bridge_slot_3_radio_DAC_I_pin, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_3_radio_ADC_I_pin = fpga_0_radio_bridge_slot_3_radio_ADC_I_pin, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_3_radio_B_pin = fpga_0_radio_bridge_slot_3_radio_B_pin, DIR = O, VEC = [6:0]
 PORT fpga_0_radio_bridge_slot_3_radio_ANTSW_pin = fpga_0_radio_bridge_slot_3_radio_ANTSW_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_radio_bridge_slot_3_radio_LED_pin = fpga_0_radio_bridge_slot_3_radio_LED_pin, DIR = O, VEC = [2:0]
 PORT fpga_0_radio_bridge_slot_3_radio_DIPSW_pin = fpga_0_radio_bridge_slot_3_radio_DIPSW_pin, DIR = I, VEC = [3:0]
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0]
 PORT fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin, DIR = IO
 PORT fpga_0_radio_bridge_slot_3_radio_spi_clk_pin = fpga_0_radio_bridge_slot_3_radio_spi_clk_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_spi_data_pin = fpga_0_radio_bridge_slot_3_radio_spi_data_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_spi_cs_pin = fpga_0_radio_bridge_slot_3_radio_spi_cs_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_SHDN_pin = fpga_0_radio_bridge_slot_3_radio_SHDN_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_TxEn_pin = fpga_0_radio_bridge_slot_3_radio_TxEn_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RxEn_pin = fpga_0_radio_bridge_slot_3_radio_RxEn_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RxHP_pin = fpga_0_radio_bridge_slot_3_radio_RxHP_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_24PA_pin = fpga_0_radio_bridge_slot_3_radio_24PA_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_5PA_pin = fpga_0_radio_bridge_slot_3_radio_5PA_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_LD_pin = fpga_0_radio_bridge_slot_3_radio_LD_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_dac_spi_data_pin = fpga_0_radio_bridge_slot_3_dac_spi_data_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_dac_spi_cs_pin = fpga_0_radio_bridge_slot_3_dac_spi_cs_pin, DIR = O
 PORT fpga_0_radio_bridge_slot_3_dac_spi_clk_pin = fpga_0_radio_bridge_slot_3_dac_spi_clk_pin, DIR = O
 PORT fpga_0_eeprom_controller_DQ0_pin = fpga_0_eeprom_controller_DQ0_pin, DIR = IO
 PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1


BEGIN ppc405_virtex4
 PARAMETER INSTANCE = ppc405_0
 PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
 PARAMETER C_IDCR_BASEADDR = 0b0100000000
 PARAMETER C_IDCR_HIGHADDR = 0b0111111111
 PARAMETER HW_VER = 2.01.b
 BUS_INTERFACE DPLB0 = plb
 BUS_INTERFACE IPLB0 = plb
 BUS_INTERFACE DSOCM = ppc405_0_docm
 BUS_INTERFACE ISOCM = ppc405_0_iocm
 BUS_INTERFACE JTAGPPC = ppc405_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC405CLOCK = clk_160_0000MHzDCM0
END

BEGIN isocm_v10
 PARAMETER INSTANCE = ppc405_0_iocm
 PARAMETER C_ISCNTLVALUE = 0xa3
 PARAMETER HW_VER = 2.00.b
 PORT ISOCM_Clk = clk_80_0000MHzDCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN isbram_if_cntlr
 PARAMETER INSTANCE = ppc405_0_iocm_cntlr
 PARAMETER HW_VER = 3.00.c
 PARAMETER C_BASEADDR = 0xffff0000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE ISOCM = ppc405_0_iocm
 BUS_INTERFACE DCR_WRITE_PORT = ppc405_0_iocm_cntlr_porta
 BUS_INTERFACE INSTRN_READ_PORT = ppc405_0_iocm_cntlr_portb
END

BEGIN bram_block
 PARAMETER INSTANCE = ppc405_0_iocm_cntlr_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ppc405_0_iocm_cntlr_porta
 BUS_INTERFACE PORTB = ppc405_0_iocm_cntlr_portb
END

BEGIN dsocm_v10
 PARAMETER INSTANCE = ppc405_0_docm
 PARAMETER C_DSCNTLVALUE = 0xa3
 PARAMETER HW_VER = 2.00.b
 PORT DSOCM_Clk = clk_80_0000MHzDCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN dsbram_if_cntlr
 PARAMETER INSTANCE = ppc405_0_docm_cntlr
 PARAMETER HW_VER = 3.00.c
 PARAMETER C_BASEADDR = 0x40110000
 PARAMETER C_HIGHADDR = 0x4011ffff
 BUS_INTERFACE DSOCM = ppc405_0_docm
 BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
END

BEGIN bram_block
 PARAMETER INSTANCE = ppc405_0_docm_cntlr_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_80_0000MHzDCM0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN warp_v4_userio
 PARAMETER INSTANCE = UserIO
 PARAMETER C_ADDRESS_0 = 0x40
 PARAMETER C_ADDRESS_1 = 0x42
 PARAMETER C_I2C_DIVIDER = 0x40
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xc9600000
 PARAMETER C_HIGHADDR = 0xc960ffff
 BUS_INTERFACE SPLB = plb
 PORT LEDs_out = fpga_0_UserIO_LEDs_out_pin
 PORT IOEx_SDA = fpga_0_UserIO_IOEx_SDA_pin
 PORT IOEx_SCL = fpga_0_UserIO_IOEx_SCL_pin
 PORT PB_in = fpga_0_UserIO_PB_in_pin
 PORT DIPSW_in = fpga_0_UserIO_DIPSW_in_pin
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = rs232_db9
 PARAMETER C_BAUDRATE = 57600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x84020000
 PARAMETER C_HIGHADDR = 0x8402ffff
 BUS_INTERFACE SPLB = plb
 PORT RX = fpga_0_rs232_db9_RX_pin
 PORT TX = fpga_0_rs232_db9_TX_pin
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = rs232_usb
 PARAMETER C_BAUDRATE = 57600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb
 PORT RX = fpga_0_rs232_usb_RX_pin
 PORT TX = fpga_0_rs232_usb_TX_pin
END

BEGIN xps_ll_temac
 PARAMETER INSTANCE = TriMode_MAC_GMII
 PARAMETER C_NUM_IDELAYCTRL = 2
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y6
 PARAMETER C_PHY_TYPE = 1
 PARAMETER C_BUS2CORE_CLK_RATIO = 1
 PARAMETER C_TEMAC_TYPE = 1
 PARAMETER HW_VER = 2.03.a
 PARAMETER C_BASEADDR = 0x87000000
 PARAMETER C_HIGHADDR = 0x8707ffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_llink0
 PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin
 PORT GTX_CLK_0 = clk_125_0000MHz
 PORT REFCLK = clk_200_0000MHz
 PORT LlinkTemac0_CLK = clk_80_0000MHzDCM0
 PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin
 PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin
 PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin
 PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin
 PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin
 PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin
 PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin
 PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin
 PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin
 PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0_pin
 PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0_pin
END

BEGIN clock_board_config
 PARAMETER INSTANCE = clk_board_config
 PARAMETER HW_VER = 1.05.a
 PORT sys_clk = fpga_0_clk_board_config_sys_clk_pin
 PORT sys_rst = net_gnd
 PORT cfg_radio_dat_out = fpga_0_clk_board_config_cfg_radio_dat_out_pin
 PORT cfg_radio_csb_out = fpga_0_clk_board_config_cfg_radio_csb_out_pin
 PORT cfg_radio_en_out = fpga_0_clk_board_config_cfg_radio_en_out_pin
 PORT cfg_radio_clk_out = fpga_0_clk_board_config_cfg_radio_clk_out_pin
 PORT cfg_logic_dat_out = fpga_0_clk_board_config_cfg_logic_dat_out_pin
 PORT cfg_logic_csb_out = fpga_0_clk_board_config_cfg_logic_csb_out_pin
 PORT cfg_logic_en_out = fpga_0_clk_board_config_cfg_logic_en_out_pin
 PORT cfg_logic_clk_out = fpga_0_clk_board_config_cfg_logic_clk_out_pin
 PORT radio_clk_src_sel = net_gnd
 PORT logic_clk_src_sel = net_gnd
 PORT config_invalid = clk_board_config_config_invalid
END

BEGIN radio_controller
 PARAMETER INSTANCE = radio_controller_0
 PARAMETER HW_VER = 1.30.a
 PARAMETER C_BASEADDR = 0xcac00000
 PARAMETER C_HIGHADDR = 0xcac0ffff
 BUS_INTERFACE SPLB = plb_v46_40MHz
 BUS_INTERFACE RC2RB_RAD2 = radio_controller_0_RC2RB_RAD2
 BUS_INTERFACE RC2RB_RAD3 = radio_controller_0_RC2RB_RAD3
END

BEGIN radio_bridge
 PARAMETER INSTANCE = radio_bridge_slot_2
 PARAMETER HW_VER = 1.30.a
 BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD2
 PORT converter_clock_in = clk_40_0000MHz
 PORT converter_clock_out = fpga_0_radio_bridge_slot_2_converter_clock_out_pin
 PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin
 PORT radio_DAC_I = fpga_0_radio_bridge_slot_2_radio_DAC_I_pin
 PORT radio_DAC_Q = fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin
 PORT radio_ADC_I = fpga_0_radio_bridge_slot_2_radio_ADC_I_pin
 PORT radio_ADC_Q = fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin
 PORT radio_B = fpga_0_radio_bridge_slot_2_radio_B_pin
 PORT radio_ANTSW = fpga_0_radio_bridge_slot_2_radio_ANTSW_pin
 PORT radio_LED = fpga_0_radio_bridge_slot_2_radio_LED_pin
 PORT radio_DIPSW = fpga_0_radio_bridge_slot_2_radio_DIPSW_pin
 PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin
 PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin
 PORT radio_spi_clk = fpga_0_radio_bridge_slot_2_radio_spi_clk_pin
 PORT radio_spi_data = fpga_0_radio_bridge_slot_2_radio_spi_data_pin
 PORT radio_spi_cs = fpga_0_radio_bridge_slot_2_radio_spi_cs_pin
 PORT radio_SHDN = fpga_0_radio_bridge_slot_2_radio_SHDN_pin
 PORT radio_TxEn = fpga_0_radio_bridge_slot_2_radio_TxEn_pin
 PORT radio_RxEn = fpga_0_radio_bridge_slot_2_radio_RxEn_pin
 PORT radio_RxHP = fpga_0_radio_bridge_slot_2_radio_RxHP_pin
 PORT radio_24PA = fpga_0_radio_bridge_slot_2_radio_24PA_pin
 PORT radio_5PA = fpga_0_radio_bridge_slot_2_radio_5PA_pin
 PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin
 PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin
 PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin
 PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin
 PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin
 PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin
 PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin
 PORT radio_LD = fpga_0_radio_bridge_slot_2_radio_LD_pin
 PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
 PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
 PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin
 PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin
 PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin
 PORT dac_spi_data = fpga_0_radio_bridge_slot_2_dac_spi_data_pin
 PORT dac_spi_cs = fpga_0_radio_bridge_slot_2_dac_spi_cs_pin
 PORT dac_spi_clk = fpga_0_radio_bridge_slot_2_dac_spi_clk_pin
 PORT user_EEPROM_IO_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
 PORT user_EEPROM_IO_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
 PORT user_EEPROM_IO_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
 PORT user_ADC_I = radio_bridge_slot_2_user_ADC_I
 PORT user_ADC_Q = radio_bridge_slot_2_user_ADC_Q
 PORT user_DAC_I = radio_bridge_slot_2_user_DAC_I
 PORT user_DAC_Q = radio_bridge_slot_2_user_DAC_Q
 PORT user_TxModelStart = radio2_txStart
 PORT user_RSSI_ADC_clk = rssi_clk_out
 PORT user_RSSI_ADC_D = radio_bridge_slot_2_user_RSSI_ADC_D
 PORT user_RxHP_external = agc_rxhp_b
 PORT user_RxBB_gain = agc_g_bb_b
 PORT user_RxRF_gain = agc_g_rf_b
END

BEGIN radio_bridge
 PARAMETER INSTANCE = radio_bridge_slot_3
 PARAMETER HW_VER = 1.30.a
 BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD3
 PORT converter_clock_in = clk_40_0000MHz
 PORT converter_clock_out = fpga_0_radio_bridge_slot_3_converter_clock_out_pin
 PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin
 PORT radio_DAC_I = fpga_0_radio_bridge_slot_3_radio_DAC_I_pin
 PORT radio_DAC_Q = fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin
 PORT radio_ADC_I = fpga_0_radio_bridge_slot_3_radio_ADC_I_pin
 PORT radio_ADC_Q = fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin
 PORT radio_B = fpga_0_radio_bridge_slot_3_radio_B_pin
 PORT radio_ANTSW = fpga_0_radio_bridge_slot_3_radio_ANTSW_pin
 PORT radio_LED = fpga_0_radio_bridge_slot_3_radio_LED_pin
 PORT radio_DIPSW = fpga_0_radio_bridge_slot_3_radio_DIPSW_pin
 PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin
 PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin
 PORT radio_spi_clk = fpga_0_radio_bridge_slot_3_radio_spi_clk_pin
 PORT radio_spi_data = fpga_0_radio_bridge_slot_3_radio_spi_data_pin
 PORT radio_spi_cs = fpga_0_radio_bridge_slot_3_radio_spi_cs_pin
 PORT radio_SHDN = fpga_0_radio_bridge_slot_3_radio_SHDN_pin
 PORT radio_TxEn = fpga_0_radio_bridge_slot_3_radio_TxEn_pin
 PORT radio_RxEn = fpga_0_radio_bridge_slot_3_radio_RxEn_pin
 PORT radio_RxHP = fpga_0_radio_bridge_slot_3_radio_RxHP_pin
 PORT radio_24PA = fpga_0_radio_bridge_slot_3_radio_24PA_pin
 PORT radio_5PA = fpga_0_radio_bridge_slot_3_radio_5PA_pin
 PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin
 PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin
 PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin
 PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin
 PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin
 PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin
 PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin
 PORT radio_LD = fpga_0_radio_bridge_slot_3_radio_LD_pin
 PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
 PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
 PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin
 PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin
 PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin
 PORT dac_spi_data = fpga_0_radio_bridge_slot_3_dac_spi_data_pin
 PORT dac_spi_cs = fpga_0_radio_bridge_slot_3_dac_spi_cs_pin
 PORT dac_spi_clk = fpga_0_radio_bridge_slot_3_dac_spi_clk_pin
 PORT user_EEPROM_IO_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
 PORT user_EEPROM_IO_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
 PORT user_EEPROM_IO_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
 PORT user_ADC_I = radio_bridge_slot_3_user_ADC_I
 PORT user_ADC_Q = radio_bridge_slot_3_user_ADC_Q
 PORT user_DAC_I = radio_bridge_slot_3_user_DAC_I
 PORT user_DAC_Q = radio_bridge_slot_3_user_DAC_Q
 PORT user_TxModelStart = radio3_txStart
 PORT user_RSSI_ADC_clk = rssi_clk_out
 PORT user_RSSI_ADC_D = radio_bridge_slot_3_user_RSSI_ADC_D
 PORT user_RxHP_external = agc_rxhp_c
 PORT user_RxBB_gain = agc_g_bb_c
 PORT user_RxRF_gain = agc_g_rf_c
END

BEGIN eeprom_onewire
 PARAMETER INSTANCE = eeprom_controller
 PARAMETER HW_VER = 1.10.a
 PARAMETER C_MEM0_BASEADDR = 0xc5400000
 PARAMETER C_MEM0_HIGHADDR = 0xc540ffff
 BUS_INTERFACE SPLB = plb
 PORT DQ0 = fpga_0_eeprom_controller_DQ0_pin
 PORT DQ2_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
 PORT DQ2_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
 PORT DQ2_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
 PORT DQ3_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
 PORT DQ3_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
 PORT DQ3_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
 PORT DQ5_I = net_vcc
 PORT DQ6_I = net_vcc
 PORT DQ7_I = net_vcc
END

BEGIN xps_ll_fifo
 PARAMETER INSTANCE = TriMode_MAC_GMII_fifo
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x81a00000
 PARAMETER C_HIGHADDR = 0x81a0ffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE LLINK = TriMode_MAC_GMII_llink0
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 40000000
 PARAMETER C_CLKOUT0_FREQ = 125000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 160000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = DCM0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 200000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = NONE
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 40000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = NONE
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT4_FREQ = 80000000
 PARAMETER C_CLKOUT4_PHASE = 0
 PARAMETER C_CLKOUT4_GROUP = DCM0
 PARAMETER C_CLKOUT4_BUF = TRUE
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.03.a
 PORT CLKIN = CLK_S
 PORT CLKOUT0 = clk_125_0000MHz
 PORT CLKOUT1 = clk_160_0000MHzDCM0
 PORT CLKOUT2 = clk_200_0000MHz
 PORT CLKOUT3 = clk_40_0000MHz
 PORT CLKOUT4 = clk_80_0000MHzDCM0
 PORT RST = clk_board_config_config_invalid
 PORT LOCKED = Dcm_all_locked
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_inst
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = ppc405_0_jtagppc_bus
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 3.00.a
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = clk_40_0000MHz
 PORT Ext_Reset_In = sys_rst_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_40MHz
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_40_0000MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN plbv46_plbv46_bridge
 PARAMETER INSTANCE = plbv46_plbv46_bridge_0
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_BUS_CLOCK_RATIO = 2
 PARAMETER C_NUM_ADDR_RNG = 2
 PARAMETER C_BRIDGE_BASEADDR = 0x86200000
 PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff
 PARAMETER C_RNG0_BASEADDR = 0xc4a00000
 PARAMETER C_RNG0_HIGHADDR = 0xc4a0ffff
 PARAMETER C_RNG1_BASEADDR = 0xcac00000
 PARAMETER C_RNG1_HIGHADDR = 0xcac0ffff
 BUS_INTERFACE MPLB = plb_v46_40MHz
 BUS_INTERFACE SPLB = plb
END

BEGIN warplab_mimo_4x4_plbw
 PARAMETER INSTANCE = warplab_mimo_4x4_plbw_0
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_BASEADDR = 0x83800000
 PARAMETER C_HIGHADDR = 0x83bfffff
 BUS_INTERFACE SPLB = plb
 PORT sysgen_clk = clk_40_0000MHz
 PORT radio1_adc_i = net_gnd
 PORT radio1_adc_q = net_gnd
 PORT radio1_adc_i_otr = net_gnd
 PORT radio1_adc_q_otr = net_gnd
 PORT radio2_adc_i = radio_bridge_slot_2_user_ADC_I
 PORT radio2_adc_q = radio_bridge_slot_2_user_ADC_Q
 PORT radio2_adc_i_otr = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
 PORT radio2_adc_q_otr = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
 PORT startcapture = net_gnd
 PORT StartTx = net_gnd
 PORT StopTx = net_gnd
 PORT radio2_dac_i = radio_bridge_slot_2_user_DAC_I
 PORT radio2_dac_q = radio_bridge_slot_2_user_DAC_Q
 PORT rssi_adc_clk = rssi_clk_out
 PORT debug_capturing = rxrun
 PORT debug_transmitting = txrun
 PORT debug_agc_done = agcsetdone
 PORT radio3_adc_i = radio_bridge_slot_3_user_ADC_I
 PORT radio3_adc_i_otr = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
 PORT radio3_adc_q = radio_bridge_slot_3_user_ADC_Q
 PORT radio3_adc_q_otr = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
 PORT radio3_dac_i = radio_bridge_slot_3_user_DAC_I
 PORT radio3_dac_q = radio_bridge_slot_3_user_DAC_Q
 PORT radio4_adc_i = net_gnd
 PORT radio4_adc_q = net_gnd
 PORT radio4_adc_i_otr = net_gnd
 PORT radio4_adc_q_otr = net_gnd
 PORT radio1_rssi = net_gnd
 PORT radio2_rssi = radio_bridge_slot_2_user_RSSI_ADC_D
 PORT radio3_rssi = radio_bridge_slot_3_user_RSSI_ADC_D
 PORT radio4_rssi = net_gnd
 PORT agc_done = agc_is_done
 PORT fromagc_radio1_i = dc_filtered_i_a
 PORT fromagc_radio1_q = dc_filtered_q_a
 PORT fromagc_radio2_i = dc_filtered_i_b
 PORT fromagc_radio2_q = dc_filtered_q_b
 PORT fromagc_radio3_i = dc_filtered_i_c
 PORT fromagc_radio3_q = dc_filtered_q_c
 PORT fromagc_radio4_i = dc_filtered_i_d
 PORT fromagc_radio4_q = dc_filtered_q_d
END

BEGIN warplab_mimo_4x4_agc_plbw
 PARAMETER INSTANCE = warplab_mimo_4x4_agc_plbw_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0xc4a00000
 PARAMETER C_HIGHADDR = 0xc4a0ffff
 BUS_INTERFACE SPLB = plb_v46_40MHz
 PORT sysgen_clk = clk_40_0000MHz
 PORT rxhp_c = agc_rxhp_c
 PORT rxhp_b = agc_rxhp_b
 PORT g_rf_c = agc_g_rf_c
 PORT g_rf_b = agc_g_rf_b
 PORT g_bb_c = agc_g_bb_c
 PORT g_bb_b = agc_g_bb_b
 PORT agc_done = agc_is_done
 PORT rssi_in_d = net_gnd
 PORT rssi_in_c = radio_bridge_slot_3_user_RSSI_ADC_D
 PORT rssi_in_b = radio_bridge_slot_2_user_RSSI_ADC_D
 PORT rssi_in_a = net_gnd
 PORT reset_in = net_gnd
 PORT q_in_d = net_gnd
 PORT q_in_c = radio_bridge_slot_3_user_ADC_Q
 PORT q_in_b = radio_bridge_slot_2_user_ADC_Q
 PORT q_in_a = net_gnd
 PORT packet_in = net_gnd
 PORT mreset_in = net_gnd
 PORT i_in_d = net_gnd
 PORT i_in_c = radio_bridge_slot_3_user_ADC_I
 PORT i_in_b = radio_bridge_slot_2_user_ADC_I
 PORT i_in_a = net_gnd
 PORT i_out_a = dc_filtered_i_a
 PORT i_out_b = dc_filtered_i_b
 PORT i_out_c = dc_filtered_i_c
 PORT i_out_d = dc_filtered_i_d
 PORT q_out_a = dc_filtered_q_a
 PORT q_out_b = dc_filtered_q_b
 PORT q_out_c = dc_filtered_q_c
 PORT q_out_d = dc_filtered_q_d
END

BEGIN xps_central_dma
 PARAMETER INSTANCE = xps_central_dma_0
 PARAMETER HW_VER = 2.03.a
 PARAMETER C_BASEADDR = 0x80200000
 PARAMETER C_HIGHADDR = 0x8020ffff
 BUS_INTERFACE MPLB = plb
 BUS_INTERFACE SPLB = plb
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = plb
END