1 | #Debug header LOC constraints (manually entered) |
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2 | NET "debug_status<0>" LOC = "L20" | IOSTANDARD = LVTTL; #pin 0 |
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3 | NET "debug_status<1>" LOC = "J21" | IOSTANDARD = LVTTL; #pin 1 |
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4 | |
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5 | NET "debug_sw_gpio<0>" LOC = "G20" | IOSTANDARD = "LVTTL"; #pin 2 |
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6 | NET "debug_sw_gpio<1>" LOC = "J20" | IOSTANDARD = "LVTTL"; #pin 3 |
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7 | NET "debug_sw_gpio<2>" LOC = "K21" | IOSTANDARD = "LVTTL"; #pin 4 |
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8 | NET "debug_sw_gpio<3>" LOC = "F20" | IOSTANDARD = "LVTTL"; #pin 5 |
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9 | NET "debug_sw_gpio<4>" LOC = "H20" | IOSTANDARD = "LVTTL"; #pin 6 |
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10 | NET "debug_sw_gpio<5>" LOC = "L21" | IOSTANDARD = "LVTTL"; #pin 7
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11 | NET "warplab_buffers_plbw_0_startcapture_pin" LOC = "H18" | IOSTANDARD = LVTTL | PULLDOWN;#pin 8
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12 |
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13 | # WARP Kits (FPGA/Clock/Radio Boards)
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14 | Net fpga_0_UserIO_LEDs_out_pin<0> LOC=N24 | IOSTANDARD = LVCMOS25;
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15 | Net fpga_0_UserIO_LEDs_out_pin<1> LOC=N20 | IOSTANDARD = LVCMOS25;
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16 | Net fpga_0_UserIO_LEDs_out_pin<2> LOC=L18 | IOSTANDARD = LVCMOS25;
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17 | Net fpga_0_UserIO_LEDs_out_pin<3> LOC=N18 | IOSTANDARD = LVCMOS25;
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18 | Net fpga_0_UserIO_LEDs_out_pin<4> LOC=M18 | IOSTANDARD = LVCMOS25;
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19 | Net fpga_0_UserIO_LEDs_out_pin<5> LOC=M25 | IOSTANDARD = LVCMOS25;
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20 | Net fpga_0_UserIO_LEDs_out_pin<6> LOC=N19 | IOSTANDARD = LVCMOS25;
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21 | Net fpga_0_UserIO_LEDs_out_pin<7> LOC=P19 | IOSTANDARD = LVCMOS25;
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22 | Net fpga_0_UserIO_IOEx_SDA_pin LOC=AL18 | IOSTANDARD = LVTTL;
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23 | Net fpga_0_UserIO_IOEx_SCL_pin LOC=AK17 | IOSTANDARD = LVTTL;
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24 | Net fpga_0_UserIO_PB_in_pin<0> LOC=N23 | IOSTANDARD = LVCMOS25;
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25 | Net fpga_0_UserIO_PB_in_pin<1> LOC=N22 | IOSTANDARD = LVCMOS25;
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26 | Net fpga_0_UserIO_PB_in_pin<2> LOC=M23 | IOSTANDARD = LVCMOS25;
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27 | Net fpga_0_UserIO_PB_in_pin<3> LOC=L23 | IOSTANDARD = LVCMOS25;
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28 | Net fpga_0_UserIO_DIPSW_in_pin<0> LOC=M17 | IOSTANDARD = LVCMOS25;
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29 | Net fpga_0_UserIO_DIPSW_in_pin<1> LOC=R18 | IOSTANDARD = LVCMOS25;
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30 | Net fpga_0_UserIO_DIPSW_in_pin<2> LOC=P17 | IOSTANDARD = LVCMOS25;
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31 | Net fpga_0_UserIO_DIPSW_in_pin<3> LOC=M16 | IOSTANDARD = LVCMOS25;
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32 | Net fpga_0_rs232_db9_RX_pin LOC=L24 | IOSTANDARD = LVCMOS25;
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33 | Net fpga_0_rs232_db9_TX_pin LOC=K24 | IOSTANDARD = LVCMOS25;
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34 | Net fpga_0_rs232_usb_RX_pin LOC=C23 | IOSTANDARD = LVTTL;
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35 | Net fpga_0_rs232_usb_TX_pin LOC=AA23 | IOSTANDARD = LVTTL;
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36 | Net fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin LOC = C17 | TIG | IOSTANDARD = LVCMOS25;
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37 | Net fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin LOC = G22 | PERIOD = 40 ns | MAXSKEW= 1.0 ns | IOSTANDARD = LVCMOS25;
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38 | Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<7> LOC = K16 | IOSTANDARD = LVCMOS25;
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39 | Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<6> LOC = H17 | IOSTANDARD = LVCMOS25;
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40 | Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<5> LOC = J17 | IOSTANDARD = LVCMOS25;
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41 | Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<4> LOC = J16 | IOSTANDARD = LVCMOS25;
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42 | Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<3> LOC = G15 | IOSTANDARD = LVCMOS25;
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43 | Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<2> LOC = K17 | IOSTANDARD = LVCMOS25;
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44 | Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<1> LOC = E17 | IOSTANDARD = LVCMOS25;
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45 | Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<0> LOC = D17 | IOSTANDARD = LVCMOS25;
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46 | Net fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin LOC = C18 | IOSTANDARD = LVCMOS25;
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47 | Net fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin LOC = K18 | IOSTANDARD = LVCMOS25;
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48 | Net fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin LOC = F21 | IOSTANDARD = LVCMOS25;
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49 | Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<7> LOC = G21 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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50 | Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<6> LOC = E23 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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51 | Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<5> LOC = G23 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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52 | Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<4> LOC = J24 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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53 | Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<3> LOC = H22 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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54 | Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<2> LOC = E22 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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55 | Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<1> LOC = E21 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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56 | Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<0> LOC = K23 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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57 | Net fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin LOC = H23 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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58 | Net fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin LOC = F23 | IOBDELAY=NONE | IOSTANDARD = LVCMOS25;
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59 | Net fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin LOC = J22 | IOSTANDARD = LVCMOS25;
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60 | Net fpga_0_TriMode_MAC_GMII_MDC_0_pin LOC = H15 | IOSTANDARD = LVCMOS25;
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61 | Net fpga_0_TriMode_MAC_GMII_MDIO_0_pin LOC = L16 | IOSTANDARD = LVCMOS25;
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62 | Net fpga_0_clk_board_config_sys_clk_pin LOC=AM21 | IOSTANDARD = LVTTL;
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63 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin LOC=AN19 | IOSTANDARD=LVTTL | SLEW = SLOW;
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64 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin LOC=AP19 | IOSTANDARD=LVTTL | SLEW = SLOW;
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65 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin LOC=AR19 | IOSTANDARD=LVTTL | SLEW = SLOW;
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66 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin LOC=AM20 | IOSTANDARD=LVTTL | SLEW = SLOW;
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67 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin LOC=AR21 | IOSTANDARD=LVTTL | SLEW = SLOW;
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68 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin LOC=AL21 | IOSTANDARD=LVTTL | SLEW = SLOW;
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69 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin LOC=AK21 | IOSTANDARD=LVTTL | SLEW = SLOW;
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70 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin LOC=AN22 | IOSTANDARD=LVTTL | SLEW = SLOW;
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71 | Net fpga_0_radio_bridge_slot_1_converter_clock_out_pin LOC=F10 | IOSTANDARD=LVTTL;
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72 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin LOC=H9 | IOSTANDARD=LVTTL;
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73 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<0> LOC=N10 | IOSTANDARD = LVTTL;
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74 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<1> LOC=R4 | IOSTANDARD = LVTTL;
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75 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<2> LOC=R3 | IOSTANDARD = LVTTL;
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76 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<3> LOC=N9 | IOSTANDARD = LVTTL;
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77 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<4> LOC=R8 | IOSTANDARD = LVTTL;
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78 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<5> LOC=T3 | IOSTANDARD = LVTTL;
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79 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<6> LOC=T11 | IOSTANDARD = LVTTL;
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80 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<7> LOC=P5 | IOSTANDARD = LVTTL;
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81 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<8> LOC=R12 | IOSTANDARD = LVTTL;
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82 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<9> LOC=P12 | IOSTANDARD = LVTTL;
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83 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<10> LOC=T10 | IOSTANDARD = LVTTL;
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84 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<11> LOC=T8 | IOSTANDARD = LVTTL;
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85 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<12> LOC=P10 | IOSTANDARD = LVTTL;
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86 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<13> LOC=P11 | IOSTANDARD = LVTTL;
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87 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<14> LOC=N12 | IOSTANDARD = LVTTL;
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88 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<15> LOC=T6 | IOSTANDARD = LVTTL;
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89 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<0> LOC=N7 | IOSTANDARD = LVTTL;
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90 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<1> LOC=M11 | IOSTANDARD = LVTTL;
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91 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<2> LOC=L4 | IOSTANDARD = LVTTL;
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92 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<3> LOC=M5 | IOSTANDARD = LVTTL;
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93 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<4> LOC=L5 | IOSTANDARD = LVTTL;
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94 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<5> LOC=J10 | IOSTANDARD = LVTTL;
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95 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<6> LOC=J11 | IOSTANDARD = LVTTL;
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96 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<7> LOC=J9 | IOSTANDARD = LVTTL;
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97 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<8> LOC=M7 | IOSTANDARD = LVTTL;
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98 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<9> LOC=M6 | IOSTANDARD = LVTTL;
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99 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<10> LOC=M3 | IOSTANDARD = LVTTL;
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100 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<11> LOC=M10 | IOSTANDARD = LVTTL;
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101 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<12> LOC=K9 | IOSTANDARD = LVTTL;
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102 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<13> LOC=J12 | IOSTANDARD = LVTTL;
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103 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<14> LOC=L6 | IOSTANDARD = LVTTL;
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104 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<15> LOC=L8 | IOSTANDARD = LVTTL;
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105 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<0> LOC=E7 | IOSTANDARD = LVTTL;
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106 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<1> LOC=E8 | IOSTANDARD = LVTTL;
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107 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<2> LOC=D10 | IOSTANDARD = LVTTL;
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108 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<3> LOC=AG20 | IOSTANDARD = LVTTL;
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109 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<4> LOC=D11 | IOSTANDARD = LVTTL;
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110 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<5> LOC=C15 | IOSTANDARD = LVTTL;
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111 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<6> LOC=E6 | IOSTANDARD = LVTTL;
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112 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<7> LOC=E4 | IOSTANDARD = LVTTL;
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113 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<8> LOC=D4 | IOSTANDARD = LVTTL;
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114 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<9> LOC=C10 | IOSTANDARD = LVTTL;
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115 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<10> LOC=G6 | IOSTANDARD = LVTTL;
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116 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<11> LOC=D7 | IOSTANDARD = LVTTL;
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117 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<12> LOC=F4 | IOSTANDARD = LVTTL;
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118 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<13> LOC=E3 | IOSTANDARD = LVTTL;
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119 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<0> LOC=G7 | IOSTANDARD = LVTTL;
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120 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<1> LOC=E12 | IOSTANDARD = LVTTL;
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121 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<2> LOC=E13 | IOSTANDARD = LVTTL;
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122 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<3> LOC=D12 | IOSTANDARD = LVTTL;
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123 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<4> LOC=F9 | IOSTANDARD = LVTTL;
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124 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<5> LOC=H7 | IOSTANDARD = LVTTL;
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125 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<6> LOC=G8 | IOSTANDARD = LVTTL;
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126 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<7> LOC=E9 | IOSTANDARD = LVTTL;
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127 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<8> LOC=C12 | IOSTANDARD = LVTTL;
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128 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<9> LOC=F5 | IOSTANDARD = LVTTL;
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129 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<10> LOC=F8 | IOSTANDARD = LVTTL;
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130 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<11> LOC=D6 | IOSTANDARD = LVTTL;
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131 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<12> LOC=C13 | IOSTANDARD = LVTTL;
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132 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<13> LOC=D9 | IOSTANDARD = LVTTL;
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133 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<0> LOC=F16 | IOSTANDARD = LVTTL;
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134 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<1> LOC=H13 | IOSTANDARD = LVTTL;
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135 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<2> LOC=E16 | IOSTANDARD = LVTTL;
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136 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<3> LOC=D15 | IOSTANDARD = LVTTL;
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137 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<4> LOC=H10 | IOSTANDARD = LVTTL;
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138 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<5> LOC=D16 | IOSTANDARD = LVTTL;
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139 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<6> LOC=H8 | IOSTANDARD = LVTTL;
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140 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<0> LOC=H3 | IOSTANDARD=LVTTL;
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141 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<1> LOC=C5 | IOSTANDARD=LVTTL;
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142 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<0> LOC=H4 | IOSTANDARD=LVTTL;
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143 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<1> LOC=C4 | IOSTANDARD=LVTTL;
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144 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<2> LOC=C8 | IOSTANDARD=LVTTL;
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145 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<0> LOC=J5 | IOSTANDARD=LVTTL;
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146 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<1> LOC=K3 | IOSTANDARD=LVTTL;
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147 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<2> LOC=P6 | IOSTANDARD=LVTTL;
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148 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<3> LOC=J4 | IOSTANDARD=LVTTL;
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149 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<0> LOC=T9 | IOSTANDARD=LVTTL | PULLDOWN;
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150 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<1> LOC=L10 | IOSTANDARD=LVTTL | PULLDOWN;
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151 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<2> LOC=U8 | IOSTANDARD=LVTTL | PULLDOWN;
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152 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<3> LOC=T4 | IOSTANDARD=LVTTL | PULLDOWN;
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153 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<4> LOC=K11 | IOSTANDARD=LVTTL | PULLDOWN;
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154 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<5> LOC=T13 | IOSTANDARD=LVTTL | PULLDOWN;
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155 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<6> LOC=N8 | IOSTANDARD=LVTTL | PULLDOWN;
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156 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<7> LOC=R11 | IOSTANDARD=LVTTL | PULLDOWN;
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157 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<8> LOC=U10 | IOSTANDARD=LVTTL | PULLDOWN;
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158 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<9> LOC=J14 | IOSTANDARD=LVTTL | PULLDOWN;
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159 | Net fpga_0_radio_bridge_slot_1_radio_EEPROM_IO_pin LOC=G12 | IOSTANDARD=LVTTL | SLEW = SLOW | DRIVE = 8;
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160 | Net fpga_0_radio_bridge_slot_1_radio_spi_clk_pin LOC=P9 | IOSTANDARD=LVTTL;
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161 | Net fpga_0_radio_bridge_slot_1_radio_spi_data_pin LOC=K4 | IOSTANDARD=LVTTL;
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162 | Net fpga_0_radio_bridge_slot_1_radio_spi_cs_pin LOC=N3 | IOSTANDARD=LVTTL;
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163 | Net fpga_0_radio_bridge_slot_1_radio_SHDN_pin LOC=F11 | IOSTANDARD=LVTTL;
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164 | Net fpga_0_radio_bridge_slot_1_radio_TxEn_pin LOC=R6 | IOSTANDARD=LVTTL;
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165 | Net fpga_0_radio_bridge_slot_1_radio_RxEn_pin LOC=G13 | IOSTANDARD=LVTTL;
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166 | Net fpga_0_radio_bridge_slot_1_radio_RxHP_pin LOC=F6 | IOSTANDARD=LVTTL;
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167 | Net fpga_0_radio_bridge_slot_1_radio_24PA_pin LOC=G3 | IOSTANDARD=LVTTL;
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168 | Net fpga_0_radio_bridge_slot_1_radio_5PA_pin LOC=F3 | IOSTANDARD=LVTTL;
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169 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin LOC=D14 | IOSTANDARD=LVTTL;
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170 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin LOC=G11 | IOSTANDARD=LVTTL;
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171 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin LOC=G5 | IOSTANDARD=LVTTL;
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172 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin LOC=G10 | IOSTANDARD=LVTTL;
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173 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin LOC=U12 | IOSTANDARD=LVTTL;
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174 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin LOC=U11 | IOSTANDARD=LVTTL;
|
---|
175 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin LOC=T5 | IOSTANDARD=LVTTL;
|
---|
176 | Net fpga_0_radio_bridge_slot_1_radio_LD_pin LOC=L3 | IOSTANDARD=LVTTL;
|
---|
177 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin LOC=C7 | IOSTANDARD=LVTTL;
|
---|
178 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin LOC=C9 | IOSTANDARD=LVTTL;
|
---|
179 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin LOC=V9 | IOSTANDARD=LVTTL;
|
---|
180 | Net fpga_0_radio_bridge_slot_1_radio_DAC_PLL_LOCK_pin LOC=K8 | IOSTANDARD=LVTTL;
|
---|
181 | Net fpga_0_radio_bridge_slot_1_radio_DAC_RESET_pin LOC=P7 | IOSTANDARD=LVTTL;
|
---|
182 | Net fpga_0_radio_bridge_slot_1_dac_spi_data_pin LOC=N5 | IOSTANDARD=LVTTL;
|
---|
183 | Net fpga_0_radio_bridge_slot_1_dac_spi_cs_pin LOC=J6 | IOSTANDARD=LVTTL;
|
---|
184 | Net fpga_0_radio_bridge_slot_1_dac_spi_clk_pin LOC=K7 | IOSTANDARD=LVTTL;
|
---|
185 | Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin LOC=AD5 | IOSTANDARD=LVTTL;
|
---|
186 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin LOC=AF5 | IOSTANDARD=LVTTL;
|
---|
187 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> LOC=AP4 | IOSTANDARD = LVTTL;
|
---|
188 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> LOC=AR3 | IOSTANDARD = LVTTL;
|
---|
189 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> LOC=AT4 | IOSTANDARD = LVTTL;
|
---|
190 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> LOC=AR4 | IOSTANDARD = LVTTL;
|
---|
191 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> LOC=AT5 | IOSTANDARD = LVTTL;
|
---|
192 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> LOC=AN3 | IOSTANDARD = LVTTL;
|
---|
193 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> LOC=AT3 | IOSTANDARD = LVTTL;
|
---|
194 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> LOC=AU5 | IOSTANDARD = LVTTL;
|
---|
195 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> LOC=AM7 | IOSTANDARD = LVTTL;
|
---|
196 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> LOC=AU6 | IOSTANDARD = LVTTL;
|
---|
197 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> LOC=AP5 | IOSTANDARD = LVTTL;
|
---|
198 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> LOC=AN5 | IOSTANDARD = LVTTL;
|
---|
199 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> LOC=AT6 | IOSTANDARD = LVTTL;
|
---|
200 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> LOC=AM6 | IOSTANDARD = LVTTL;
|
---|
201 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> LOC=AL6 | IOSTANDARD = LVTTL;
|
---|
202 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> LOC=AL8 | IOSTANDARD = LVTTL;
|
---|
203 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> LOC=AF8 | IOSTANDARD = LVTTL;
|
---|
204 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> LOC=AF9 | IOSTANDARD = LVTTL;
|
---|
205 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> LOC=AH8 | IOSTANDARD = LVTTL;
|
---|
206 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> LOC=AG7 | IOSTANDARD = LVTTL;
|
---|
207 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> LOC=AJ6 | IOSTANDARD = LVTTL;
|
---|
208 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> LOC=AN4 | IOSTANDARD = LVTTL;
|
---|
209 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> LOC=AG8 | IOSTANDARD = LVTTL;
|
---|
210 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> LOC=AM5 | IOSTANDARD = LVTTL;
|
---|
211 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> LOC=AJ5 | IOSTANDARD = LVTTL;
|
---|
212 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> LOC=AK6 | IOSTANDARD = LVTTL;
|
---|
213 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> LOC=AH7 | IOSTANDARD = LVTTL;
|
---|
214 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> LOC=AJ4 | IOSTANDARD = LVTTL;
|
---|
215 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> LOC=AL4 | IOSTANDARD = LVTTL;
|
---|
216 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> LOC=AB15 | IOSTANDARD = LVTTL;
|
---|
217 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> LOC=AC14 | IOSTANDARD = LVTTL;
|
---|
218 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> LOC=AK4 | IOSTANDARD = LVTTL;
|
---|
219 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> LOC=V14 | IOSTANDARD = LVTTL;
|
---|
220 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> LOC=U15 | IOSTANDARD = LVTTL;
|
---|
221 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> LOC=W6 | IOSTANDARD = LVTTL;
|
---|
222 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> LOC=AG18 | IOSTANDARD = LVTTL;
|
---|
223 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> LOC=V15 | IOSTANDARD = LVTTL;
|
---|
224 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> LOC=V5 | IOSTANDARD = LVTTL;
|
---|
225 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> LOC=AA10 | IOSTANDARD = LVTTL;
|
---|
226 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> LOC=Y11 | IOSTANDARD = LVTTL;
|
---|
227 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> LOC=AA9 | IOSTANDARD = LVTTL;
|
---|
228 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> LOC=V7 | IOSTANDARD = LVTTL;
|
---|
229 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> LOC=U6 | IOSTANDARD = LVTTL;
|
---|
230 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> LOC=AB11 | IOSTANDARD = LVTTL;
|
---|
231 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> LOC=W4 | IOSTANDARD = LVTTL;
|
---|
232 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> LOC=V12 | IOSTANDARD = LVTTL;
|
---|
233 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> LOC=AB7 | IOSTANDARD = LVTTL;
|
---|
234 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> LOC=AE7 | IOSTANDARD = LVTTL;
|
---|
235 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> LOC=AC7 | IOSTANDARD = LVTTL;
|
---|
236 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> LOC=AC5 | IOSTANDARD = LVTTL;
|
---|
237 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> LOC=AE4 | IOSTANDARD = LVTTL;
|
---|
238 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> LOC=AD4 | IOSTANDARD = LVTTL;
|
---|
239 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> LOC=AD7 | IOSTANDARD = LVTTL;
|
---|
240 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> LOC=AD6 | IOSTANDARD = LVTTL;
|
---|
241 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> LOC=W14 | IOSTANDARD = LVTTL;
|
---|
242 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> LOC=U5 | IOSTANDARD = LVTTL;
|
---|
243 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> LOC=W5 | IOSTANDARD = LVTTL;
|
---|
244 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> LOC=AA11 | IOSTANDARD = LVTTL;
|
---|
245 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> LOC=W9 | IOSTANDARD = LVTTL;
|
---|
246 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> LOC=Y12 | IOSTANDARD = LVTTL;
|
---|
247 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> LOC=AA4 | IOSTANDARD = LVTTL;
|
---|
248 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> LOC=AH5 | IOSTANDARD = LVTTL;
|
---|
249 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> LOC=Y4 | IOSTANDARD = LVTTL;
|
---|
250 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> LOC=V17 | IOSTANDARD = LVTTL;
|
---|
251 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> LOC=AC3 | IOSTANDARD = LVTTL;
|
---|
252 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> LOC=Y6 | IOSTANDARD = LVTTL;
|
---|
253 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> LOC=AH4 | IOSTANDARD = LVTTL;
|
---|
254 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> LOC=U3 | IOSTANDARD=LVTTL;
|
---|
255 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> LOC=Y7 | IOSTANDARD=LVTTL;
|
---|
256 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> LOC=AA8 | IOSTANDARD=LVTTL;
|
---|
257 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> LOC=W10 | IOSTANDARD=LVTTL;
|
---|
258 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> LOC=V4 | IOSTANDARD=LVTTL;
|
---|
259 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> LOC=Y13 | IOSTANDARD=LVTTL;
|
---|
260 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> LOC=AH3 | IOSTANDARD=LVTTL;
|
---|
261 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> LOC=W15 | IOSTANDARD=LVTTL;
|
---|
262 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> LOC=AA13 | IOSTANDARD=LVTTL;
|
---|
263 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> LOC=AD10 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
264 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> LOC=AD11 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
265 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> LOC=AE3 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
266 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> LOC=AC13 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
267 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> LOC=AF3 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
268 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> LOC=AM3 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
269 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> LOC=AG10 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
270 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> LOC=AF10 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
271 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> LOC=AL5 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
272 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> LOC=AM8 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
273 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin LOC=AE6 | IOSTANDARD=LVTTL | SLEW = SLOW | DRIVE = 8;
|
---|
274 | Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin LOC=AB12 | IOSTANDARD=LVTTL;
|
---|
275 | Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin LOC=AG3 | IOSTANDARD=LVTTL;
|
---|
276 | Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin LOC=AE8 | IOSTANDARD=LVTTL;
|
---|
277 | Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin LOC=AB3 | IOSTANDARD=LVTTL;
|
---|
278 | Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin LOC=W16 | IOSTANDARD=LVTTL;
|
---|
279 | Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin LOC=AB10 | IOSTANDARD=LVTTL;
|
---|
280 | Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin LOC=AC4 | IOSTANDARD=LVTTL;
|
---|
281 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin LOC=W7 | IOSTANDARD=LVTTL;
|
---|
282 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin LOC=AC8 | IOSTANDARD=LVTTL;
|
---|
283 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin LOC=AA5 | IOSTANDARD=LVTTL;
|
---|
284 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin LOC=AF4 | IOSTANDARD=LVTTL;
|
---|
285 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin LOC=Y8 | IOSTANDARD=LVTTL;
|
---|
286 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin LOC=AA14 | IOSTANDARD=LVTTL;
|
---|
287 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin LOC=AB13 | IOSTANDARD=LVTTL;
|
---|
288 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin LOC=AK3 | IOSTANDARD=LVTTL;
|
---|
289 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin LOC=AH9 | IOSTANDARD=LVTTL;
|
---|
290 | Net fpga_0_radio_bridge_slot_2_radio_LD_pin LOC=AD9 | IOSTANDARD=LVTTL;
|
---|
291 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin LOC=V13 | IOSTANDARD=LVTTL;
|
---|
292 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin LOC=Y9 | IOSTANDARD=LVTTL;
|
---|
293 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin LOC=AC12 | IOSTANDARD=LVTTL;
|
---|
294 | Net fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin LOC=AL3 | IOSTANDARD=LVTTL;
|
---|
295 | Net fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin LOC=AC10 | IOSTANDARD=LVTTL;
|
---|
296 | Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin LOC=AC9 | IOSTANDARD=LVTTL;
|
---|
297 | Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin LOC=AK8 | IOSTANDARD=LVTTL;
|
---|
298 | Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin LOC=AK7 | IOSTANDARD=LVTTL;
|
---|
299 | Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin LOC=AC29 | IOSTANDARD=LVTTL;
|
---|
300 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin LOC=AD32 | IOSTANDARD=LVTTL;
|
---|
301 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> LOC=AB35 | IOSTANDARD = LVTTL;
|
---|
302 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> LOC=AC34 | IOSTANDARD = LVTTL;
|
---|
303 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> LOC=AA30 | IOSTANDARD = LVTTL;
|
---|
304 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> LOC=Y27 | IOSTANDARD = LVTTL;
|
---|
305 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> LOC=AB31 | IOSTANDARD = LVTTL;
|
---|
306 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> LOC=N37 | IOSTANDARD = LVTTL;
|
---|
307 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> LOC=AA31 | IOSTANDARD = LVTTL;
|
---|
308 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> LOC=R34 | IOSTANDARD = LVTTL;
|
---|
309 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> LOC=AC32 | IOSTANDARD = LVTTL;
|
---|
310 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> LOC=Y32 | IOSTANDARD = LVTTL;
|
---|
311 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> LOC=AD35 | IOSTANDARD = LVTTL;
|
---|
312 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> LOC=Y34 | IOSTANDARD = LVTTL;
|
---|
313 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> LOC=P37 | IOSTANDARD = LVTTL;
|
---|
314 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> LOC=R36 | IOSTANDARD = LVTTL;
|
---|
315 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> LOC=T35 | IOSTANDARD = LVTTL;
|
---|
316 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> LOC=Y33 | IOSTANDARD = LVTTL;
|
---|
317 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> LOC=V34 | IOSTANDARD = LVTTL;
|
---|
318 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> LOC=AC35 | IOSTANDARD = LVTTL;
|
---|
319 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> LOC=V33 | IOSTANDARD = LVTTL;
|
---|
320 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> LOC=Y36 | IOSTANDARD = LVTTL;
|
---|
321 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> LOC=U37 | IOSTANDARD = LVTTL;
|
---|
322 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> LOC=AB36 | IOSTANDARD = LVTTL;
|
---|
323 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> LOC=U35 | IOSTANDARD = LVTTL;
|
---|
324 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> LOC=Y37 | IOSTANDARD = LVTTL;
|
---|
325 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> LOC=W37 | IOSTANDARD = LVTTL;
|
---|
326 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> LOC=AA34 | IOSTANDARD = LVTTL;
|
---|
327 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> LOC=W36 | IOSTANDARD = LVTTL;
|
---|
328 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> LOC=AA35 | IOSTANDARD = LVTTL;
|
---|
329 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> LOC=W30 | IOSTANDARD = LVTTL;
|
---|
330 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> LOC=W32 | IOSTANDARD = LVTTL;
|
---|
331 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> LOC=V35 | IOSTANDARD = LVTTL;
|
---|
332 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> LOC=W34 | IOSTANDARD = LVTTL;
|
---|
333 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> LOC=AM33 | IOSTANDARD = LVTTL;
|
---|
334 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> LOC=AF33 | IOSTANDARD = LVTTL;
|
---|
335 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> LOC=AG31 | IOSTANDARD = LVTTL;
|
---|
336 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> LOC=AM22 | IOSTANDARD = LVTTL;
|
---|
337 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> LOC=AH30 | IOSTANDARD = LVTTL;
|
---|
338 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> LOC=AG32 | IOSTANDARD = LVTTL;
|
---|
339 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> LOC=AF31 | IOSTANDARD = LVTTL;
|
---|
340 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> LOC=AH34 | IOSTANDARD = LVTTL;
|
---|
341 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> LOC=AK32 | IOSTANDARD = LVTTL;
|
---|
342 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> LOC=AF34 | IOSTANDARD = LVTTL;
|
---|
343 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> LOC=AN34 | IOSTANDARD = LVTTL;
|
---|
344 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> LOC=AJ36 | IOSTANDARD = LVTTL;
|
---|
345 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> LOC=AN33 | IOSTANDARD = LVTTL;
|
---|
346 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> LOC=AH35 | IOSTANDARD = LVTTL;
|
---|
347 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> LOC=AA26 | IOSTANDARD = LVTTL;
|
---|
348 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> LOC=AE29 | IOSTANDARD = LVTTL;
|
---|
349 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> LOC=AA29 | IOSTANDARD = LVTTL;
|
---|
350 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> LOC=AD29 | IOSTANDARD = LVTTL;
|
---|
351 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> LOC=AB26 | IOSTANDARD = LVTTL;
|
---|
352 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> LOC=AB27 | IOSTANDARD = LVTTL;
|
---|
353 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> LOC=AA28 | IOSTANDARD = LVTTL;
|
---|
354 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> LOC=AC28 | IOSTANDARD = LVTTL;
|
---|
355 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> LOC=AL34 | IOSTANDARD = LVTTL;
|
---|
356 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> LOC=AJ34 | IOSTANDARD = LVTTL;
|
---|
357 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> LOC=AK33 | IOSTANDARD = LVTTL;
|
---|
358 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> LOC=AK34 | IOSTANDARD = LVTTL;
|
---|
359 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> LOC=AJ35 | IOSTANDARD = LVTTL;
|
---|
360 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> LOC=AG33 | IOSTANDARD = LVTTL;
|
---|
361 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> LOC=AG28 | IOSTANDARD = LVTTL;
|
---|
362 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> LOC=AC24 | IOSTANDARD = LVTTL;
|
---|
363 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> LOC=AD31 | IOSTANDARD = LVTTL;
|
---|
364 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> LOC=AA24 | IOSTANDARD = LVTTL;
|
---|
365 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> LOC=AG30 | IOSTANDARD = LVTTL;
|
---|
366 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> LOC=AB23 | IOSTANDARD = LVTTL;
|
---|
367 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> LOC=AH29 | IOSTANDARD = LVTTL;
|
---|
368 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> LOC=AN37 | IOSTANDARD=LVTTL;
|
---|
369 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> LOC=AJ37 | IOSTANDARD=LVTTL;
|
---|
370 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> LOC=AL35 | IOSTANDARD=LVTTL;
|
---|
371 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> LOC=AE33 | IOSTANDARD=LVTTL;
|
---|
372 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> LOC=AM35 | IOSTANDARD=LVTTL;
|
---|
373 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> LOC=AG36 | IOSTANDARD=LVTTL;
|
---|
374 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> LOC=AG37 | IOSTANDARD=LVTTL;
|
---|
375 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> LOC=T34 | IOSTANDARD=LVTTL;
|
---|
376 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> LOC=AH37 | IOSTANDARD=LVTTL;
|
---|
377 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> LOC=P35 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
378 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> LOC=AB28 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
379 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> LOC=M36 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
380 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> LOC=AF35 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
381 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> LOC=L36 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
382 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> LOC=M37 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
383 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> LOC=R37 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
384 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> LOC=P36 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
385 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> LOC=AE34 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
386 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> LOC=Y31 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
387 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin LOC=AE32 | IOSTANDARD=LVTTL | SLEW = SLOW | DRIVE = 8;
|
---|
388 | Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin LOC=AC37 | IOSTANDARD=LVTTL;
|
---|
389 | Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin LOC=AD37 | IOSTANDARD=LVTTL;
|
---|
390 | Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin LOC=AF36 | IOSTANDARD=LVTTL;
|
---|
391 | Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin LOC=AD27 | IOSTANDARD=LVTTL;
|
---|
392 | Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin LOC=AE37 | IOSTANDARD=LVTTL;
|
---|
393 | Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin LOC=Y26 | IOSTANDARD=LVTTL;
|
---|
394 | Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin LOC=AC25 | IOSTANDARD=LVTTL;
|
---|
395 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin LOC=AM36 | IOSTANDARD=LVTTL;
|
---|
396 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin LOC=AN35 | IOSTANDARD=LVTTL;
|
---|
397 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin LOC=AF28 | IOSTANDARD=LVTTL;
|
---|
398 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin LOC=AD34 | IOSTANDARD=LVTTL;
|
---|
399 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin LOC=AK36 | IOSTANDARD=LVTTL;
|
---|
400 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin LOC=AE28 | IOSTANDARD=LVTTL;
|
---|
401 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin LOC=K36 | IOSTANDARD=LVTTL;
|
---|
402 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin LOC=W29 | IOSTANDARD=LVTTL;
|
---|
403 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin LOC=K37 | IOSTANDARD=LVTTL;
|
---|
404 | Net fpga_0_radio_bridge_slot_3_radio_LD_pin LOC=AB37 | IOSTANDARD=LVTTL;
|
---|
405 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin LOC=AM37 | IOSTANDARD=LVTTL;
|
---|
406 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin LOC=AL36 | IOSTANDARD=LVTTL;
|
---|
407 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin LOC=U36 | IOSTANDARD=LVTTL;
|
---|
408 | Net fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin LOC=AG35 | IOSTANDARD=LVTTL;
|
---|
409 | Net fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin LOC=AE36 | IOSTANDARD=LVTTL;
|
---|
410 | Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin LOC=T36 | IOSTANDARD=LVTTL;
|
---|
411 | Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin LOC=W35 | IOSTANDARD=LVTTL;
|
---|
412 | Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin LOC=AA36 | IOSTANDARD=LVTTL;
|
---|
413 | Net fpga_0_radio_bridge_slot_4_converter_clock_out_pin LOC=H33 | IOSTANDARD=LVTTL;
|
---|
414 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin LOC=L33 | IOSTANDARD=LVTTL;
|
---|
415 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<0> LOC=E32 | IOSTANDARD = LVTTL;
|
---|
416 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<1> LOC=D27 | IOSTANDARD = LVTTL;
|
---|
417 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<2> LOC=E33 | IOSTANDARD = LVTTL;
|
---|
418 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<3> LOC=F34 | IOSTANDARD = LVTTL;
|
---|
419 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<4> LOC=F35 | IOSTANDARD = LVTTL;
|
---|
420 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<5> LOC=F33 | IOSTANDARD = LVTTL;
|
---|
421 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<6> LOC=D31 | IOSTANDARD = LVTTL;
|
---|
422 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<7> LOC=D30 | IOSTANDARD = LVTTL;
|
---|
423 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<8> LOC=E28 | IOSTANDARD = LVTTL;
|
---|
424 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<9> LOC=F36 | IOSTANDARD = LVTTL;
|
---|
425 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<10> LOC=G33 | IOSTANDARD = LVTTL;
|
---|
426 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<11> LOC=G35 | IOSTANDARD = LVTTL;
|
---|
427 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<12> LOC=D29 | IOSTANDARD = LVTTL;
|
---|
428 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<13> LOC=C29 | IOSTANDARD = LVTTL;
|
---|
429 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<14> LOC=D37 | IOSTANDARD = LVTTL;
|
---|
430 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<15> LOC=E37 | IOSTANDARD = LVTTL;
|
---|
431 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<0> LOC=D26 | IOSTANDARD = LVTTL;
|
---|
432 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<1> LOC=C27 | IOSTANDARD = LVTTL;
|
---|
433 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<2> LOC=G25 | IOSTANDARD = LVTTL;
|
---|
434 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<3> LOC=C25 | IOSTANDARD = LVTTL;
|
---|
435 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<4> LOC=F29 | IOSTANDARD = LVTTL;
|
---|
436 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<5> LOC=F24 | IOSTANDARD = LVTTL;
|
---|
437 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<6> LOC=E26 | IOSTANDARD = LVTTL;
|
---|
438 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<7> LOC=D32 | IOSTANDARD = LVTTL;
|
---|
439 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<8> LOC=F28 | IOSTANDARD = LVTTL;
|
---|
440 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<9> LOC=F31 | IOSTANDARD = LVTTL;
|
---|
441 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<10> LOC=E27 | IOSTANDARD = LVTTL;
|
---|
442 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<11> LOC=F26 | IOSTANDARD = LVTTL;
|
---|
443 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<12> LOC=H34 | IOSTANDARD = LVTTL;
|
---|
444 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<13> LOC=E31 | IOSTANDARD = LVTTL;
|
---|
445 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<14> LOC=F25 | IOSTANDARD = LVTTL;
|
---|
446 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<15> LOC=E29 | IOSTANDARD = LVTTL;
|
---|
447 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<0> LOC=K26 | IOSTANDARD = LVTTL;
|
---|
448 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<1> LOC=P30 | IOSTANDARD = LVTTL;
|
---|
449 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<2> LOC=M27 | IOSTANDARD = LVTTL;
|
---|
450 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<3> LOC=AF23 | IOSTANDARD = LVTTL;
|
---|
451 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<4> LOC=T29 | IOSTANDARD = LVTTL;
|
---|
452 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<5> LOC=R31 | IOSTANDARD = LVTTL;
|
---|
453 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<6> LOC=V30 | IOSTANDARD = LVTTL;
|
---|
454 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<7> LOC=M31 | IOSTANDARD = LVTTL;
|
---|
455 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<8> LOC=W26 | IOSTANDARD = LVTTL;
|
---|
456 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<9> LOC=K27 | IOSTANDARD = LVTTL;
|
---|
457 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<10> LOC=M26 | IOSTANDARD = LVTTL;
|
---|
458 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<11> LOC=L29 | IOSTANDARD = LVTTL;
|
---|
459 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<12> LOC=V25 | IOSTANDARD = LVTTL;
|
---|
460 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<13> LOC=W27 | IOSTANDARD = LVTTL;
|
---|
461 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<0> LOC=K28 | IOSTANDARD = LVTTL;
|
---|
462 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<1> LOC=J32 | IOSTANDARD = LVTTL;
|
---|
463 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<2> LOC=K33 | IOSTANDARD = LVTTL;
|
---|
464 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<3> LOC=H32 | IOSTANDARD = LVTTL;
|
---|
465 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<4> LOC=L30 | IOSTANDARD = LVTTL;
|
---|
466 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<5> LOC=M33 | IOSTANDARD = LVTTL;
|
---|
467 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<6> LOC=M35 | IOSTANDARD = LVTTL;
|
---|
468 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<7> LOC=P32 | IOSTANDARD = LVTTL;
|
---|
469 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<8> LOC=U28 | IOSTANDARD = LVTTL;
|
---|
470 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<9> LOC=N33 | IOSTANDARD = LVTTL;
|
---|
471 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<10> LOC=U27 | IOSTANDARD = LVTTL;
|
---|
472 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<11> LOC=L28 | IOSTANDARD = LVTTL;
|
---|
473 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<12> LOC=V28 | IOSTANDARD = LVTTL;
|
---|
474 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<13> LOC=M28 | IOSTANDARD = LVTTL;
|
---|
475 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<0> LOC=G30 | IOSTANDARD = LVTTL;
|
---|
476 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<1> LOC=U33 | IOSTANDARD = LVTTL;
|
---|
477 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<2> LOC=G32 | IOSTANDARD = LVTTL;
|
---|
478 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<3> LOC=J34 | IOSTANDARD = LVTTL;
|
---|
479 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<4> LOC=K29 | IOSTANDARD = LVTTL;
|
---|
480 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<5> LOC=J35 | IOSTANDARD = LVTTL;
|
---|
481 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<6> LOC=U32 | IOSTANDARD = LVTTL;
|
---|
482 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<0> LOC=U31 | IOSTANDARD=LVTTL;
|
---|
483 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<1> LOC=V29 | IOSTANDARD=LVTTL;
|
---|
484 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<0> LOC=U26 | IOSTANDARD=LVTTL;
|
---|
485 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<1> LOC=N35 | IOSTANDARD=LVTTL;
|
---|
486 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<2> LOC=N34 | IOSTANDARD=LVTTL;
|
---|
487 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<0> LOC=C30 | IOSTANDARD=LVTTL;
|
---|
488 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<1> LOC=H25 | IOSTANDARD=LVTTL;
|
---|
489 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<2> LOC=C24 | IOSTANDARD=LVTTL;
|
---|
490 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<3> LOC=J27 | IOSTANDARD=LVTTL;
|
---|
491 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<0> LOC=J36 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
492 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<1> LOC=C33 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
493 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<2> LOC=G37 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
494 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<3> LOC=C32 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
495 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<4> LOC=G36 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
496 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<5> LOC=D36 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
497 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<6> LOC=D34 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
498 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<7> LOC=E36 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
499 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<8> LOC=E34 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
500 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<9> LOC=H35 | IOSTANDARD=LVTTL | PULLDOWN;
|
---|
501 | Net fpga_0_radio_bridge_slot_4_radio_EEPROM_IO_pin LOC=L31 | IOSTANDARD=LVTTL | SLEW = SLOW | DRIVE = 8;
|
---|
502 | Net fpga_0_radio_bridge_slot_4_radio_spi_clk_pin LOC=J29 | IOSTANDARD=LVTTL;
|
---|
503 | Net fpga_0_radio_bridge_slot_4_radio_spi_data_pin LOC=D24 | IOSTANDARD=LVTTL;
|
---|
504 | Net fpga_0_radio_bridge_slot_4_radio_spi_cs_pin LOC=H28 | IOSTANDARD=LVTTL;
|
---|
505 | Net fpga_0_radio_bridge_slot_4_radio_SHDN_pin LOC=K34 | IOSTANDARD=LVTTL;
|
---|
506 | Net fpga_0_radio_bridge_slot_4_radio_TxEn_pin LOC=H30 | IOSTANDARD=LVTTL;
|
---|
507 | Net fpga_0_radio_bridge_slot_4_radio_RxEn_pin LOC=L34 | IOSTANDARD=LVTTL;
|
---|
508 | Net fpga_0_radio_bridge_slot_4_radio_RxHP_pin LOC=J26 | IOSTANDARD=LVTTL;
|
---|
509 | Net fpga_0_radio_bridge_slot_4_radio_24PA_pin LOC=H27 | IOSTANDARD=LVTTL;
|
---|
510 | Net fpga_0_radio_bridge_slot_4_radio_5PA_pin LOC=L26 | IOSTANDARD=LVTTL;
|
---|
511 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin LOC=K32 | IOSTANDARD=LVTTL;
|
---|
512 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin LOC=G31 | IOSTANDARD=LVTTL;
|
---|
513 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin LOC=U30 | IOSTANDARD=LVTTL;
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514 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin LOC=M32 | IOSTANDARD=LVTTL;
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515 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin LOC=J37 | IOSTANDARD=LVTTL;
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516 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin LOC=H37 | IOSTANDARD=LVTTL;
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517 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin LOC=C35 | IOSTANDARD=LVTTL;
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518 | Net fpga_0_radio_bridge_slot_4_radio_LD_pin LOC=E24 | IOSTANDARD=LVTTL;
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519 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin LOC=N32 | IOSTANDARD=LVTTL;
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520 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin LOC=V27 | IOSTANDARD=LVTTL;
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521 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin LOC=D35 | IOSTANDARD=LVTTL;
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522 | Net fpga_0_radio_bridge_slot_4_radio_DAC_PLL_LOCK_pin LOC=F30 | IOSTANDARD=LVTTL;
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523 | Net fpga_0_radio_bridge_slot_4_radio_DAC_RESET_pin LOC=G26 | IOSTANDARD=LVTTL;
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524 | Net fpga_0_radio_bridge_slot_4_dac_spi_data_pin LOC=C28 | IOSTANDARD=LVTTL;
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525 | Net fpga_0_radio_bridge_slot_4_dac_spi_cs_pin LOC=D25 | IOSTANDARD=LVTTL;
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526 | Net fpga_0_radio_bridge_slot_4_dac_spi_clk_pin LOC=G28 | IOSTANDARD=LVTTL;
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527 | Net fpga_0_eeprom_controller_DQ0_pin LOC=AH22 | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
|
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528 | Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
|
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529 | TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 40000 kHz;
|
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530 | Net fpga_0_clk_1_sys_clk_pin LOC=AN20 | IOSTANDARD = LVTTL;
|
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531 | Net fpga_0_rst_1_sys_rst_pin TIG;
|
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532 | Net fpga_0_rst_1_sys_rst_pin LOC=M21 | IOSTANDARD = LVCMOS25;
|
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533 |
|
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534 | ###### TriMode_MAC_GMII
|
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535 | #### Additional TriMode_MAC_GMII constraints
|
---|
536 |
|
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537 | NET "*tx_gmii_mii_clk_in_0*" TNM_NET = "clk_phy_tx_clk0";
|
---|
538 | NET "*tx_gmii_mii_clk_out_0*" TNM_NET = "clk_phy_tx_clk0";
|
---|
539 | TIMESPEC "TS_phy_tx_clk0" = PERIOD "clk_phy_tx_clk0" 7700 ps HIGH 50 %;
|
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540 |
|
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541 | NET "*gmii_rx_clk_0*" TNM_NET = "clk_phy_rx_clk0";
|
---|
542 | NET "*gmii_rx_clk_delay_0*" TNM_NET = "clk_phy_rx_clk0";
|
---|
543 | NET "*gmii_rx_clk_ibufg_0*" TNM_NET = "clk_phy_rx_clk0";
|
---|
544 | TIMESPEC "TS_phy_rx_clk0" = PERIOD "clk_phy_rx_clk0" 7700 ps HIGH 50 %;
|
---|
545 |
|
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546 | NET "*tx_client_clk_in_0*" TNM_NET = "clk_client_tx_clk0";
|
---|
547 | NET "*tx_client_clk_out_0*" TNM_NET = "clk_client_tx_clk0";
|
---|
548 | TIMESPEC "TS_client_tx_clk0" = PERIOD "clk_client_tx_clk0" 7700 ps HIGH 50 %;
|
---|
549 |
|
---|
550 | NET "*rx_client_clk_in_0*" TNM_NET = "clk_client_rx_clk0";
|
---|
551 | NET "*rx_client_clk_out_0*" TNM_NET = "clk_client_rx_clk0";
|
---|
552 | TIMESPEC "TS_client_rx_clk0" = PERIOD "clk_client_rx_clk0" 7700 ps HIGH 50 %;
|
---|
553 |
|
---|
554 | NET "*mii_tx_clk_0*" TNM_NET = "clk_mii_tx_clk0";
|
---|
555 | TIMESPEC "TS_mii_tx_clk0" = PERIOD "clk_mii_tx_clk0" 25000 ps HIGH 50 %;
|
---|
556 |
|
---|
557 |
|
---|
558 | #################### EMAC 0 GMII Constraints ########################
|
---|
559 | INST "*mii0?RXD_TO_MAC*" IOB = true;
|
---|
560 | INST "*mii0?RX_DV_TO_MAC" IOB = true;
|
---|
561 | INST "*mii0?RX_ER_TO_MAC" IOB = true;
|
---|
562 |
|
---|
563 | INST "*gmii0/*gmii_rxd?_delay" IOBDELAY_TYPE = FIXED;
|
---|
564 | INST "*gmii0/*gmii_rx_dv_delay" IOBDELAY_TYPE = FIXED;
|
---|
565 | INST "*gmii0/*gmii_rx_er_delay" IOBDELAY_TYPE = FIXED;
|
---|
566 | INST "*gmii0/*gmii_rxd?_delay" IOBDELAY_VALUE = 0;
|
---|
567 | INST "*gmii0/*gmii_rx_dv_delay" IOBDELAY_VALUE = 0;
|
---|
568 | INST "*gmii0/*gmii_rx_er_delay" IOBDELAY_VALUE = 0;
|
---|
569 | INST "*gmii_rx_clk_0_delay" IOBDELAY_TYPE = FIXED;
|
---|
570 | INST "*gmii_rx_clk_0_delay" IOBDELAY_VALUE = 30;
|
---|
571 |
|
---|
572 | INST "fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<?>" TNM = "sig_mii_tx_0";
|
---|
573 | INST "fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin" TNM = "sig_mii_tx_0";
|
---|
574 | INST "fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin" TNM = "sig_mii_tx_0";
|
---|
575 |
|
---|
576 | INST "fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<?>" TNM = "sig_mii_rx_0";
|
---|
577 | INST "fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin" TNM = "sig_mii_rx_0";
|
---|
578 | INST "fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin" TNM = "sig_mii_rx_0";
|
---|
579 |
|
---|
580 | # Need to TIG between the LocalLink clock and the rx_client and tx_client clocks
|
---|
581 | NET "*/LlinkTemac0_CLK*" TNM_NET = "LLCLK";
|
---|
582 | TIMESPEC "TS_LL_CLK_2_RX_CLIENT_CLK" = FROM LLCLK TO clk_client_rx_clk0 8000 ps DATAPATHONLY;
|
---|
583 | TIMESPEC "TS_LL_CLK_2_TX_CLIENT_CLK" = FROM LLCLK TO clk_client_tx_clk0 8000 ps DATAPATHONLY;
|
---|
584 | TIMESPEC "TS_RX_CLIENT_CLK_2_LL_CLK" = FROM clk_client_rx_clk0 TO LLCLK 10000 ps DATAPATHONLY;
|
---|
585 | TIMESPEC "TS_TX_CLIENT_CLK_2_LL_CLK" = FROM clk_client_tx_clk0 TO LLCLK 10000 ps DATAPATHONLY;
|
---|
586 |
|
---|
587 |
|
---|
588 |
|
---|
589 | ###### ppc405_0
|
---|
590 | NET "ppc405_0/C405RSTCHIPRESETREQ" TPTHRU = "ppc405_0_RST_GRP";
|
---|
591 | NET "ppc405_0/C405RSTCORERESETREQ" TPTHRU = "ppc405_0_RST_GRP";
|
---|
592 | NET "ppc405_0/C405RSTSYSRESETREQ" TPTHRU = "ppc405_0_RST_GRP";
|
---|
593 | TIMESPEC "TS_RST_ppc405_0" = FROM CPUS THRU ppc405_0_RST_GRP TO FFS TIG;
|
---|