Model { Name "wlan_phy_tx_pmd" Version 7.8 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.510" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" PostLoadFcn "wlan_phy_tx_init" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" FPTRunName "Run 1" MaxMDLFileLineLength 120 InitFcn "wlan_phy_tx_init" StartFcn "wlan_phy_tx_init" Created "Fri Jan 01 20:07:58 2016" Creator "murphpo" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "murphpo" ModifiedDateFormat "%" LastModifiedDate "Mon May 20 11:27:26 2019" RTWModifiedTimeStamp 480251645 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "disabled" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowDesignRanges off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off Object { $PropName "DataLoggingOverride" $ObjectID 1 $ClassName "Simulink.SimulationData.ModelLoggingInfo" model_ "wlan_phy_tx_pmd_11n" signals_ [] overrideMode_ [0.0] Array { Type "Cell" Dimension 1 Cell "wlan_phy_tx_pmd_11n" PropName "logAsSpecifiedByModels_" } Array { Type "Cell" Dimension 1 Cell [] PropName "logAsSpecifiedByModelsSSIDs_" } } RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { 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FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SignalLoggingSaveFormat "ModelDataLogs" SaveOutput on SaveState off SignalLogging on DSMLogging on InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 5 Version "1.11.1" Array { Type "Cell" Dimension 8 Cell "BooleansAsBitfields" Cell "PassReuseOutputArgsAs" Cell "PassReuseOutputArgsThreshold" Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" Cell "UseSpecifiedMinMax" PropName "DisabledProps" } BlockReduction on BooleanDataType on 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ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "ErrorLevel1" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" SFUnconditionalTransitionShadowingDiag "warning" } Simulink.HardwareCC { $ObjectID 7 Version "1.11.1" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 8 Version "1.11.1" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 9 Version "1.11.1" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 10 Version "1.11.1" Array { Type "Cell" Dimension 8 Cell "IncludeHyperlinkInReport" Cell "GenerateTraceInfo" Cell "GenerateTraceReport" Cell "GenerateTraceReportSl" Cell "GenerateTraceReportSf" Cell "GenerateTraceReportEml" Cell "GenerateSLWebview" Cell "GenerateCodeMetricsReport" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateSLWebview off GenerateCodeMetricsReport off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 11 Version "1.11.1" Array { Type "Cell" Dimension 21 Cell "IgnoreCustomStorageClasses" Cell "IgnoreTestpoints" Cell "InsertBlockDesc" Cell "InsertPolySpaceComments" Cell "SFDataObjDesc" Cell "MATLABFcnDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrFcnArg" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" Cell "ReqsInCode" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 12 Version "1.11.1" Array { Type "Cell" Dimension 16 Cell "GeneratePreprocessorConditionals" Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "CPPClassGenCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" CodeExecutionProfiling off ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on ConcurrentExecutionCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns off CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" CurrentDlgPage "Diagnostics" ConfigPrmDlgPosition [ 836, 462, 1724, 1119 ] } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 2 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType BusCreator Inputs "4" DisplayOption "none" OutDataTypeStr "Inherit: auto" NonVirtualBus off } Block { BlockType BusSelector OutputAsBus off } Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" PreserveConstantTs off } Block { BlockType Delay DelayLengthSource "Dialog" DelayLength "2" DelayLengthUpperLimit "100" InitialConditionSource "Dialog" InitialCondition "0.0" ExternalReset "None" PreventDirectFeedthrough off DiagnosticForOutOfRangeDelayLength "None" RemoveProtectionDelayLength off InputProcessing "Elements as channels (sample based)" UseCircularBuffer off SampleTime "-1" StateMustResolveToSignalObject off CodeGenStateStorageClass "Auto" } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Display Format "short" Decimation "10" Floating off SampleTime "-1" } Block { BlockType From IconDisplay "Tag" TagVisibility "local" } Block { BlockType Goto IconDisplay "Tag" } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Logic Operator "AND" Inputs "2" IconShape "rectangular" AllPortsSameDT on OutDataTypeStr "Inherit: Logical (see Configuration Parameters: Optimization)" SampleTime "-1" } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType RealImagToComplex Input "Real and imag" ConstantPart "0" SampleTime "-1" } Block { BlockType RelationalOperator Operator ">=" InputSameDT on OutDataTypeStr "Inherit: Logical (see Configuration Parameters: Optimization)" ZeroCross on SampleTime "-1" } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType Step Time "1" Before "0" After "1" SampleTime "-1" VectorParams1D on ZeroCross on } Block { BlockType Stop } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" SFBlockType "NONE" Variant off GeneratePreprocessorConditionals off } Block { BlockType Terminator } Block { BlockType ToWorkspace VariableName "simulink_output" MaxDataPoints "1000" Decimation "1" SampleTime "0" FixptAsFi off NumInputs "1" } } System { Name "wlan_phy_tx_pmd" Location [130, 120, 1961, 1222] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" ReportName "simulink-default.rpt" SIDHighWatermark "3611" Block { BlockType Reference Name " System Generator" SID "3448" Tag "genX" Ports [] Position [386, 355, 447, 418] ShowName off AttributesFormatString "System\\nGenerator" LibraryVersion "1.2" UserDataPersistent on UserData "DataTag0" SourceBlock "xbsIndex_r4/ System Generator" SourceType "Xilinx System Generator Block" infoedit " System Generator" xilinxfamily "virtex6" part "xc6vlx240t" speed "-2" package "ff1156" synthesis_tool "XST" clock_wrapper "Clock Enables" directory "./pcore_tx_v401a" proj_type "Project Navigator" Synth_file "XST Defaults" Impl_file "ISE Defaults" testbench off simulink_period "1" sysclk_period "6.25" dcm_input_clock_period "10" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" has_advanced_control "0" sggui_pos "326,241,464,470" block_type "sysgen" sg_icon_stat "61,63,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 61 61 0 0 ],[0 0 63 63 0 ],[1 1 1 ]" ");\npatch([3.3 20.64 32.64 44.64 56.64 32.64 15.3 3.3 ],[44.32 44.32 56.32 44.32 56.32 56.32 56.32 44.32 ],[0.93" "3333 0.203922 0.141176 ]);\npatch([15.3 32.64 20.64 3.3 15.3 ],[32.32 32.32 44.32 44.32 32.32 ],[0.698039 0.0313" "725 0.219608 ]);\npatch([3.3 20.64 32.64 15.3 3.3 ],[20.32 20.32 32.32 32.32 20.32 ],[0.933333 0.203922 0.141176" " ]);\npatch([15.3 56.64 44.64 32.64 20.64 3.3 15.3 ],[8.32 8.32 20.32 8.32 20.32 20.32 8.32 ],[0.698039 0.031372" "5 0.219608 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType SubSystem Name "Changelog" SID "1851" Ports [] Position [981, 355, 1038, 414] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Changelog" Location [1053, 683, 1557, 1100] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Annotation { Name "2.00.a:\n-First export as _pmd, with I/O for mac_hw integration\n\n2.00.b:\n-Changed pkt buf interface to" " 64b\n-Added pkt buf addr offset\n\n2.00.c:\n-Fixed puncturing timing\n-Enabled BPSK/QPSK 3/4 schemes\n\n2.00.d:\n-" "Attempting fix of bad pkt Tx (based on wireshark Rx checksum)\n at 3/4; suspected bug in not puncturing TAIL\n\n2." "00.e:\n-Reworked TxEn disable logic with programmable extension\n -Moved TX_END extension to new register\n\n2.00." "f:\n-Added longer Tx -> Rx delay (250 cycles) to reduce RSSI/ADC\n transients at Rx post Tx\n\n2.00.g:\n-Added RX_" "SIGS_INVALID output to supress post-Tx transients from\n ADCs at input to PHY Rx\n\n2.00.h:\n-Added 16QAM support\n" " -64QAM is trickier; interleaver will need new arch, since 1->6 isn't a supported DPRAM aspect ratio\n\n2.00.i:\n-" "Added 64QAM support\n\n2.00.j:\n-Fixed slip-by-1-per-symbol bug in FFT start timing (broke long-duration pkts)\n-Ad" "ded reg bit to not reset scrambling LFSR per pkt\n\n2.00.k:\n-Added RF B DAC outputs; A/B selection done via config" " register\n\n2.00.l:\n-Fixed zero sample between preamble and first OFDM symbol\n-Removed unused reset port\n\n2.00" ".m:\n-More output mux timing bug fixes (last sample of pkt was being dropped)\n\n2.00.n:\n-Added explicit DAC_TX_CL" "K input to replace upsampled T=8 constant as IQ clock enable\n-Replaced delays with registers in preamble output de" "lays\n-Added (x || FORCE_RESET) to SR latches in start ctrl (trying to fix very rare perma-Tx mode on download)\n-A" "dded (x || posedge(tx_start)) to output FIFO reset (trying to fix very rare extra sample between LTS - SIGNAL)\n\n-" "2.00.o:\n-Added RFC,D outputs\n\n2.00.p:\n-More pipeline registers throughput (sw regs and outputs mostly)\n\n2.00." "q:\n-Added logic to insert MAC timestamp in outgoing packets. Timestamp is 8 bytes. Start/stop byte\n indexes are " "set by sw. Timestamp must start on 8-byte boundary (true for standard beacon/probe frames)\n\n2.00.r:\n-Added passt" "hrough for Tx gain setting. Now MAC provides TxGain with each Tx (same as pkt buf sel). PHY\n passes this through " "to the radio controller user TxGain port.\n\n2.00.s:\n-Added Tx Ant Mask passthrough for MAC selection of active Tx" " antennas\n-Added ctrl bits for:\n -En/disable use of MAC ant mask\n -Endian swap MAC ant mask before output to R" "C (will be removed when correct endianess is determined in hw)\n\n2.00.t:\n-Made SIGNAL.LENGTH max value programmab" "le, in units of kB\n\n2.00.u - 2.00.w:\n-Added separate TX_GAIN paths per RF (MAC -> PHY -> radio_controller passth" "rough)\n-Added delayed TX_RUNNING signal, to trigger pkt det at other nodes\n\n2.00.x:\n-Merged TX_RUNNING outputs " "(delayed, not-delayed) with mux to select" Position [37, 545] HorizontalAlignment "left" BackgroundColor "[0.913725, 0.913725, 0.913725]" } Annotation { Name "2.01.a:\n-Cleaed up init script - no PHY design changes\n\n2.01.b:\n-Added pipeline regs between pkt buf " "and muxes\n\n2.01.c:\n-Fixed scaling of preamble/constellations to fix bad\n scaling of outer points for 64-QAM. N" "ew scaling will \n reduce effective Tx power 0.3dB; increase Tx_Scaling\n register value to compensate.\n-Updated" " values for pilot tones to use BSPK constellation\n definition in init script (+/-1 were hard coded previously)\n\n" "2.01.d:\n-Replaced upsampled-constants with TX_IQ_SAMP_CE from\n in both start/add extension subsystems" Position [547, 155] HorizontalAlignment "left" BackgroundColor "[0.913725, 0.913725, 0.913725]" } Annotation { Name "4.00.a:\n-Re-designed most of the Tx PHY pipeline\n -Added 11n SISO support\n -Replaced interleaver-per" "-mod with unified bits-in, syms-out interleaver\n -Replaced control logic with simpler generate-one-sym-at-a-time " "logic\n -Replcaed packet buffer addressing logic with simpler packet section slicing\n -Adopted external sample c" "lock enable, now supports 5/10/20/40 MSps modes\n -Unified configuration params for each OFDM symbol in one subsys" "tem\n\n-Added DFFs around output FIFO control signals, hoping to isolate apparent\n asychronous assertions\n-Quali" "fied PHY_Start by samp_ce, for fixed phase relationship between\n sample clock and PHY-MAC control\n\n4.00.b:\n-Fi" "xed missing posedge on software RC_RXEN\n\n4.00.c-e:\n-Debugging missing interleaver RAM netlist \n-Increased post-" "tx extension values to 10 bits\n\n4.00.f:\n-Added ping/pong interleaver RAMs, now supports 40MSps at all MCS\n\n4.0" "0.g:\n-Fixed enable generation logic for output registers (was asserting late, truncating\n STS portion of preambl" "e)\n\n4.00.h:\n-Fixed 11n pilot shifting sequence\n\n4.01.a:\n-Added pipeline regs to pkt_buf -> encoder path to cu" "t 8-stage combinational path" Position [967, 245] HorizontalAlignment "left" BackgroundColor "[0.913725, 0.913725, 0.913725]" } Annotation { Name "2XCLK Branch - since merged\n\n3.00.a:\nUpdated sim-only clock-enable gen to 4x\n\n3.00.b:\nUsed local cl" "k en gen (upsampled constant 4)\n\n3.00.c:\nAdded ILA\n\n3.00.d:\nRemoved ILA (debugging Rx)\nAdded DFF to DATA_IN," " WREN, RST inputs of DAC FIFO, testing\n theory that an async write or reset is responsible for hw mismatch\nNOTE:" " DFFs on FIFO inputs didn't resolve extra post-preamble sample. Observed\n good and bad Tx on multiple downloads o" "f same design with 3.00.d Tx PHY.\n\n3.00.e:\nQualified RC_PHY_TX_START by SAMP_CE (safe, since RC holds its output" "s\n high until reset at end of Tx)\nNOTE: didn't resolve issue; still see good/bad Tx on reconfig\n\n3.00.f:\nAdde" "d DFF to SAMP_CE before consumers in outputs block - testing theory that FIFO.RD\n somehow reacts one cycle late wh" "en generated by combinational logic\nRe-enabled CS ILA\n\n3.00.g:\nReplaced upsampled constant with samp_ce gateway" " in\n(this version has not exhibited any bad-Tx behavior in harware, yet)\n\n3.00.h:\nDisregarded ILA\nIncreased si" "ze of post-Tx timing values to 10 bits each (from 8)" Position [552, 485] HorizontalAlignment "left" BackgroundColor "[0.913725, 0.913725, 0.913725]" } } } Block { BlockType SubSystem Name "EDK Processor" SID "2703" Ports [] Position [665, 354, 723, 414] CopyFcn "xlProcBlockCopyCallback(gcbh);xlBlockMoveCallback(gcbh);" DeleteFcn "xlDestroyGui(gcbh);" LoadFcn "xlBlockLoadCallback(gcbh);" ModelCloseFcn "xlDestroyGui(gcbh);" PreSaveFcn "xlBlockPreSaveCallback(gcbh);" PostSaveFcn "xlBlockPostSaveCallback(gcbh);" DestroyFcn "xlDestroyGui(gcbh);" OpenFcn "bh=gcbh;xlProcBlockCallbacks('populatesharedmemorylistbox',bh);xlOpenGui(bh, 'edkprocessor_gui.x" "ml', @xlProcBlockEnablement, @xlProcBlockAction);" CloseFcn "xlDestroyGui(gcbh);" MoveFcn "xlBlockMoveCallback(gcbh);" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Xilinx EDK Processor Block" MaskDescription "Xilinx EDK Processor" MaskHelp "eval('');xlDoc('-book','sysgen','-topic','EDK_Processor');" MaskPromptString "Configure Processor for|XPS Project| |Available Memories| | |Bus Type|Base Address| |Loc" "k| |Dual Clocks| |Register Read-Back|Constraint File| |Inherit Device Type|Initial Program| |Enable Co-Debug wit" "h Xilinx SDK (Beta)| | | | | | | | | | | | | | | | " MaskStyleString "popup(EDK pcore generation|HDL netlisting),edit,edit,edit,edit,edit,popup(AXI|PLB),edit,e" "dit,checkbox,edit,checkbox,edit,checkbox,edit,edit,checkbox,edit,edit,checkbox,edit,edit,edit,edit,edit,edit,edi" "t,edit,edit,edit,edit,edit,edit,edit,edit,edit" MaskVariables "mode=&1;xmp=&2;MemVisToProc=&3;AvailableMemories=&4;portInterfaceTable=&5;bus_type_sgadvanc" "ed=&6;bus_type=&7;baseaddr=&8;baseaddr_lock_sgadvanced=&9;baseaddr_lock=@10;dual_clock_sgadvanced=&11;dual_clock" "=@12;reg_readback_sgadvanced=&13;reg_readback=@14;ucf_file=&15;inheritDeviceType_sgadvanced=&16;inheritDeviceTyp" "e=@17;elf_file=&18;codebug_sgadvanced=&19;codebug=@20;clock_name=&21;internalPortList=&22;resetPolarity=&23;memx" "table=&24;procinfo=&25;memmapdirty=&26;blockname=&27;xpsintstyle=&28;has_advanced_control=@29;sggui_pos=&30;bloc" "k_type=&31;block_version=&32;sg_icon_stat=&33;sg_mask_display=&34;sg_list_contents=&35;sg_blockgui_xml=&36;" MaskTunableValueString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on," "on,on,on,on,on,on,on" MaskCallbackString "|||||||||||||||||||||||||||||||||||" MaskEnableString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,o" "n,on,on,on,on,on,on" MaskVisibilityString "on,on,off,on,on,off,on,on,off,on,off,on,off,on,on,off,on,on,off,on,off,off,off,off,off," "off,off,off,off,off,off,off,off,off,off,off" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on," "on,on,on,on,on,on,on" MaskInitialization "try\n tmp_gcb = gcb;\n tmp_gcbh = gcbh;\n if (strcmp('SysGenIndex',get_param(bdroot(" "tmp_gcbh),'tag')) && ~isempty(regexp(bdroot(tmp_gcb), '^xbs', 'once')))\n return;\n end;\n xlMungeMaskParam" "s;\n\n block_type='edkprocessor';\n\n serialized_declarations = '{''block_type''=>''String''}';\n xledkproces" "sor_init();\n ptable_ = xlblockprep(get_param(tmp_gcb, 'MaskWSVariables'));\n try\n xlBlockMoveCallback(tmp" "_gcbh);\n catch \n clear global xl_updateicon_recursion_guard;\n end;\ncatch\n global dbgsysgen;\n if(~i" "sempty(dbgsysgen) && dbgsysgen)\n e = regexprep(lasterr, '\\n', '\\nError: ');\n disp(['Error: While runni" "ng MaskInit code on block ' tmp_gcb ': ' e]);\n error(e);\n end\nend\n" MaskSelfModifiable on MaskDisplay "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 58 58 0 0 ],[0 0 60 60 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[38.88 38.8" "8 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[30.88 30.88 38.88 38.88" " 30.88 ],[0.931 0.946 0.973 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);" "\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: " "end icon text');" MaskIconFrame off MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "EDK pcore generation||
<<Timing>>
<<Config>>
<<PKT_BUF_SEL>>
<<Output_Scaling>>
<<TX_START>>
<<FFT_Config>>
<<STATUS>>
||{'e" "xposed'=>[],'portdir'=>[],'portname'=>[],'shortname'=>[]}||AXI|0x80000000||off||on||on|||off|||on|plb|{}|0|{'mla" "ddr'=>[0.00000000000000000,1.00000000000000000,2.00000000000000000,3.00000000000000000,4.00000000000000000,5.000" "00000000000000,0.00000000000000000],'mlist'=>['wlan_phy_tx_pmd/Registers/From Register6','wlan_phy_tx_pmd/Regist" "ers/From Register5','wlan_phy_tx_pmd/Registers/From Register4','wlan_phy_tx_pmd/Registers/From Register3','wlan_" "phy_tx_pmd/Registers/From Register2','wlan_phy_tx_pmd/Registers/From Register1','wlan_phy_tx_pmd/Registers/To Re" "gister'],'mlname'=>['\\\\'Timing\\\\'','\\\\'Config\\\\'','\\\\'PKT_BUF_SEL\\\\'','\\\\'Output_Scaling\\\\'','\\" "\\'TX_START\\\\'','\\\\'FFT_Config\\\\'','\\\\'STATUS\\\\''],'mlstate'=>[0.00000000000000000,0.00000000000000000" ",0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000]}|{}|off||d" "efault|0|-1,-1,-1,-1|edkprocessor|2.7|58,60,-1,-1,white,blue,0,07734,right,,[ ],[ ]|fprintf('','COMMENT: begin i" "con graphics');\npatch([0 58 58 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91 ]);\nplot([0 58 58 0 0 ],[0 0 60 60 0 ]);\n" "patch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[38.88 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 " "]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[30.88 30.88 38.88 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([11.2 22" ".76 30.76 19.2 11.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2" " ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics')" ";\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');|{'table'=>{'AvailableMemories'" "=>'popup()'}}|" System { Name "EDK Processor" Location [514, 91, 900, 269] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "274" Block { BlockType Reference Name "AXI_ARESETN" SID "2703:204" Ports [1, 1] Position [145, 50, 210, 70] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Constant Name "Constant" SID "2703:203" Position [20, 50, 40, 70] ShowName off } Block { BlockType Constant Name "Constant1" SID "2703:205" Position [20, 120, 40, 140] ShowName off } Block { BlockType Constant Name "Constant10" SID "2703:223" Position [20, 730, 40, 750] ShowName off } Block { BlockType Constant Name "Constant11" SID "2703:225" Position [20, 800, 40, 820] ShowName off } Block { BlockType Constant Name "Constant12" SID "2703:227" Position [20, 865, 40, 885] ShowName off } Block { BlockType Constant Name "Constant13" SID "2703:229" Position [20, 935, 40, 955] ShowName off } Block { BlockType Constant Name "Constant14" SID "2703:231" Position [20, 1000, 40, 1020] ShowName off } Block { BlockType Constant Name "Constant15" SID "2703:233" Position [20, 1070, 40, 1090] ShowName off } Block { BlockType Constant Name "Constant16" SID "2703:235" Position [20, 1140, 40, 1160] ShowName off } Block { BlockType Constant Name "Constant17" SID "2703:237" Position [20, 1205, 40, 1225] ShowName off } Block { BlockType Constant Name "Constant18" SID "2703:239" Position [20, 1275, 40, 1295] ShowName off } Block { BlockType Constant Name "Constant19" SID "2703:241" Position [20, 1340, 40, 1360] ShowName off } Block { BlockType Constant Name "Constant2" SID "2703:207" Position [20, 185, 40, 205] ShowName off } Block { BlockType Constant Name "Constant20" SID "2703:243" Position [20, 1410, 40, 1430] ShowName off } Block { BlockType Constant Name "Constant21" SID "2703:245" Position [20, 1480, 40, 1500] ShowName off } Block { BlockType Constant Name "Constant22" SID "2703:247" Position [20, 1545, 40, 1565] ShowName off } Block { BlockType Constant Name "Constant23" SID "2703:249" Position [20, 1615, 40, 1635] ShowName off } Block { BlockType Constant Name "Constant24" SID "2703:251" Position [20, 1680, 40, 1700] ShowName off } Block { BlockType Constant Name "Constant3" SID "2703:209" Position [20, 255, 40, 275] ShowName off } Block { BlockType Constant Name "Constant4" SID "2703:211" Position [20, 320, 40, 340] ShowName off } Block { BlockType Constant Name "Constant5" SID "2703:213" Position [20, 390, 40, 410] ShowName off } Block { BlockType Constant Name "Constant6" SID "2703:215" Position [20, 460, 40, 480] ShowName off } Block { BlockType Constant Name "Constant7" SID "2703:217" Position [20, 525, 40, 545] ShowName off } Block { BlockType Constant Name "Constant8" SID "2703:219" Position [20, 595, 40, 615] ShowName off } Block { BlockType Constant Name "Constant9" SID "2703:221" Position [20, 660, 40, 680] ShowName off } Block { BlockType Reference Name "From Register" SID "2703:196" Ports [0, 1] Position [145, 1752, 205, 1808] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'STATUS'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "S_AXI_ARADDR" SID "2703:206" Ports [1, 1] Position [145, 120, 210, 140] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARBURST" SID "2703:208" Ports [1, 1] Position [145, 185, 210, 205] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARCACHE" SID "2703:210" Ports [1, 1] Position [145, 255, 210, 275] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARID" SID "2703:212" Ports [1, 1] Position [145, 320, 210, 340] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARLEN" SID "2703:214" Ports [1, 1] Position [145, 390, 210, 410] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARLOCK" SID "2703:216" Ports [1, 1] Position [145, 460, 210, 480] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARPROT" SID "2703:218" Ports [1, 1] Position [145, 525, 210, 545] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARREADY" SID "2703:254" Ports [1, 1] Position [660, 270, 720, 290] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_ARSIZE" SID "2703:220" Ports [1, 1] Position [145, 595, 210, 615] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_ARVALID" SID "2703:222" Ports [1, 1] Position [145, 660, 210, 680] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWADDR" SID "2703:224" Ports [1, 1] Position [145, 730, 210, 750] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWBURST" SID "2703:226" Ports [1, 1] Position [145, 800, 210, 820] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWCACHE" SID "2703:228" Ports [1, 1] Position [145, 865, 210, 885] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWID" SID "2703:230" Ports [1, 1] Position [145, 935, 210, 955] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWLEN" SID "2703:232" Ports [1, 1] Position [145, 1000, 210, 1020] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWLOCK" SID "2703:234" Ports [1, 1] Position [145, 1070, 210, 1090] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWPROT" SID "2703:236" Ports [1, 1] Position [145, 1140, 210, 1160] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWREADY" SID "2703:256" Ports [1, 1] Position [660, 335, 720, 355] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_AWSIZE" SID "2703:238" Ports [1, 1] Position [145, 1205, 210, 1225] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_AWVALID" SID "2703:240" Ports [1, 1] Position [145, 1275, 210, 1295] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_BID" SID "2703:258" Ports [1, 1] Position [660, 405, 720, 425] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_BREADY" SID "2703:242" Ports [1, 1] Position [145, 1340, 210, 1360] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_BRESP" SID "2703:260" Ports [1, 1] Position [660, 475, 720, 495] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_BVALID" SID "2703:262" Ports [1, 1] Position [660, 540, 720, 560] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RDATA" SID "2703:264" Ports [1, 1] Position [660, 610, 720, 630] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RID" SID "2703:266" Ports [1, 1] Position [660, 675, 720, 695] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RLAST" SID "2703:268" Ports [1, 1] Position [660, 745, 720, 765] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RREADY" SID "2703:244" Ports [1, 1] Position [145, 1410, 210, 1430] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_RRESP" SID "2703:270" Ports [1, 1] Position [660, 815, 720, 835] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_RVALID" SID "2703:272" Ports [1, 1] Position [660, 880, 720, 900] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_WDATA" SID "2703:246" Ports [1, 1] Position [145, 1480, 210, 1500] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_WLAST" SID "2703:248" Ports [1, 1] Position [145, 1545, 210, 1565] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_WREADY" SID "2703:274" Ports [1, 1] Position [660, 950, 720, 970] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "S_AXI_WSTRB" SID "2703:250" Ports [1, 1] Position [145, 1615, 210, 1635] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "S_AXI_WVALID" SID "2703:252" Ports [1, 1] Position [145, 1680, 210, 1700] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Terminator Name "Terminator" SID "2703:253" Position [820, 270, 840, 290] ShowName off } Block { BlockType Terminator Name "Terminator1" SID "2703:255" Position [820, 335, 840, 355] ShowName off } Block { BlockType Terminator Name "Terminator10" SID "2703:273" Position [820, 950, 840, 970] ShowName off } Block { BlockType Terminator Name "Terminator2" SID "2703:257" Position [820, 405, 840, 425] ShowName off } Block { BlockType Terminator Name "Terminator3" SID "2703:259" Position [820, 475, 840, 495] ShowName off } Block { BlockType Terminator Name "Terminator4" SID "2703:261" Position [820, 540, 840, 560] ShowName off } Block { BlockType Terminator Name "Terminator5" SID "2703:263" Position [820, 610, 840, 630] ShowName off } Block { BlockType Terminator Name "Terminator6" SID "2703:265" Position [820, 675, 840, 695] ShowName off } Block { BlockType Terminator Name "Terminator7" SID "2703:267" Position [820, 745, 840, 765] ShowName off } Block { BlockType Terminator Name "Terminator8" SID "2703:269" Position [820, 815, 840, 835] ShowName off } Block { BlockType Terminator Name "Terminator9" SID "2703:271" Position [820, 880, 840, 900] ShowName off } Block { BlockType Reference Name "To Register" SID "2703:197" Ports [2, 1] Position [660, 1017, 720, 1073] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Timing'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register1" SID "2703:198" Ports [2, 1] Position [660, 1122, 720, 1178] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Config'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register2" SID "2703:199" Ports [2, 1] Position [660, 1227, 720, 1283] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'PKT_BUF_SEL'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register3" SID "2703:200" Ports [2, 1] Position [660, 1332, 720, 1388] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Output_Scaling'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register4" SID "2703:201" Ports [2, 1] Position [660, 1437, 720, 1493] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'TX_START'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register5" SID "2703:202" Ports [2, 1] Position [660, 1542, 720, 1598] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'FFT_Config'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "memmap" SID "2703:195" Ports [32, 23] Position [310, 517, 560, 1483] LibraryVersion "1.2" SourceBlock "xbsEDKLib_r4/EDK Core" SourceType "Xilinx EDK Core Block" infoedit "For use with EDK Processor block." sim_method "Inactive" xl_use_area off xl_area "[0,0,0,0,0,0,0]" xmp "xmp" blockname "blockname" dual_clock "dual_clock" procinfo "procinfo" bus_type "bus_type" memxtable "memxtable" memmap_hdlcontent "library IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity axi_sgiface i" "s\n generic (\n -- AXI specific.\n -- TODO: need to figure out a way to pass these generics from o" "utside\n C_S_AXI_SUPPORT_BURST : integer := 0;\n -- TODO: fix the internal ID width to 8\n C" "_S_AXI_ID_WIDTH : integer := 8;\n C_S_AXI_DATA_WIDTH : integer := 32;\n C_S_AXI_ADDR_WIDT" "H : integer := 32;\n C_S_AXI_TOTAL_ADDR_LEN : integer := 12;\n C_S_AXI_LINEAR_ADDR_LEN : intege" "r := 8;\n C_S_AXI_BANK_ADDR_LEN : integer := 2;\n C_S_AXI_AWLEN_WIDTH : integer := 8;\n " "C_S_AXI_ARLEN_WIDTH : integer := 8\n );\n port (\n -- General.\n AXI_AClk : in std_lo" "gic;\n AXI_AResetN : in std_logic;\n -- not used\n AXI_Ce : in std_logic;\n \n " " -- AXI Port.\n S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);\n S_AXI_AWID" " : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n S_AXI_AWLEN : in std_logic_vector(C_S_AXI_AWLE" "N_WIDTH-1 downto 0);\n S_AXI_AWSIZE : in std_logic_vector(2 downto 0);\n S_AXI_AWBURST : in std_lo" "gic_vector(1 downto 0);\n S_AXI_AWLOCK : in std_logic_vector(1 downto 0);\n S_AXI_AWCACHE : in std" "_logic_vector(3 downto 0);\n S_AXI_AWPROT : in std_logic_vector(2 downto 0);\n S_AXI_AWVALID : in " "std_logic;\n S_AXI_AWREADY : out std_logic;\n \n S_AXI_WLAST : in std_logic;\n S_AXI" "_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n S_AXI_WSTRB : in std_logic_vector((C_S_" "AXI_DATA_WIDTH/8)-1 downto 0);\n S_AXI_WVALID : in std_logic;\n S_AXI_WREADY : out std_logic;\n " " \n S_AXI_BRESP : out std_logic_vector(1 downto 0);\n S_AXI_BID : out std_logic_vector(C_S_" "AXI_ID_WIDTH-1 downto 0);\n S_AXI_BVALID : out std_logic;\n S_AXI_BREADY : in std_logic;\n " "\n S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);\n S_AXI_ARID : in std_log" "ic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n S_AXI_ARLEN : in std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downto " "0);\n S_AXI_ARSIZE : in std_logic_vector(2 downto 0);\n S_AXI_ARBURST : in std_logic_vector(1 down" "to 0);\n S_AXI_ARLOCK : in std_logic_vector(1 downto 0);\n S_AXI_ARCACHE : in std_logic_vector(3 d" "ownto 0);\n S_AXI_ARPROT : in std_logic_vector(2 downto 0);\n S_AXI_ARVALID : in std_logic;\n " " S_AXI_ARREADY : out std_logic;\n \n -- 'From Register'\n -- 'STATUS'\n sm_STATUS_dou" "t : in std_logic_vector(32-1 downto 0);\n -- 'To Register'\n -- 'Timing'\n sm_Timing_dout : in" " std_logic_vector(32-1 downto 0);\n sm_Timing_din : out std_logic_vector(32-1 downto 0);\n sm_Timing" "_en : out std_logic;\n -- 'Config'\n sm_Config_dout : in std_logic_vector(32-1 downto 0);\n " "sm_Config_din : out std_logic_vector(32-1 downto 0);\n sm_Config_en : out std_logic;\n -- 'PKT_BUF" "_SEL'\n sm_PKT_BUF_SEL_dout : in std_logic_vector(32-1 downto 0);\n sm_PKT_BUF_SEL_din : out std_log" "ic_vector(32-1 downto 0);\n sm_PKT_BUF_SEL_en : out std_logic;\n -- 'Output_Scaling'\n sm_Ou" "tput_Scaling_dout : in std_logic_vector(32-1 downto 0);\n sm_Output_Scaling_din : out std_logic_vector(32-1" " downto 0);\n sm_Output_Scaling_en : out std_logic;\n -- 'TX_START'\n sm_TX_START_dout : in " "std_logic_vector(32-1 downto 0);\n sm_TX_START_din : out std_logic_vector(32-1 downto 0);\n sm_TX_ST" "ART_en : out std_logic;\n -- 'FFT_Config'\n sm_FFT_Config_dout : in std_logic_vector(32-1 downto 0)" ";\n sm_FFT_Config_din : out std_logic_vector(32-1 downto 0);\n sm_FFT_Config_en : out std_logic;\n" " -- 'From FIFO'\n -- 'To FIFO'\n -- 'Shared Memory'\n\n S_AXI_RLAST : out std_logic;\n" " S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n S_AXI_RDATA : out std_logic_v" "ector(C_S_AXI_DATA_WIDTH-1 downto 0);\n S_AXI_RRESP : out std_logic_vector(1 downto 0);\n S_AXI_RVA" "LID : out std_logic;\n S_AXI_RREADY : in std_logic\n );\nend entity axi_sgiface;\n\narchitecture IMP o" "f axi_sgiface is\n\n-- Internal signals for write channel.\nsignal S_AXI_BVALID_i : std_logic;\nsignal S_AXI_" "BID_i : std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\nsignal S_AXI_WREADY_i : std_logic;\n \n-- I" "nternal signals for read channels.\nsignal S_AXI_ARLEN_i : std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downto 0);" "\nsignal S_AXI_RLAST_i : std_logic;\nsignal S_AXI_RREADY_i : std_logic;\nsignal S_AXI_RVALID_i :" " std_logic;\nsignal S_AXI_RDATA_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal S_AXI_RID_i " " : std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n\n-- for read channel\nsignal read_bank_addr_i : std_lo" "gic_vector(C_S_AXI_BANK_ADDR_LEN-1 downto 0);\nsignal read_linear_addr_i : std_logic_vector(C_S_AXI_LINEAR_ADDR_L" "EN-1 downto 0);\n-- for write channel\nsignal write_bank_addr_i : std_logic_vector(C_S_AXI_BANK_ADDR_LEN-1 downt" "o 0);\nsignal write_linear_addr_i : std_logic_vector(C_S_AXI_LINEAR_ADDR_LEN-1 downto 0);\n\nsignal reg_bank_out_i" " : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal fifo_bank_out_i : std_logic_vector(C_S_AXI_D" "ATA_WIDTH-1 downto 0);\nsignal shmem_bank_out_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n \n-- 'F" "rom Register'\n-- 'STATUS'\nsignal sm_STATUS_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'To Reg" "ister'\n-- 'Timing'\nsignal sm_Timing_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_Timing_" "en_i : std_logic;\nsignal sm_Timing_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'Config'\nsig" "nal sm_Config_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_Config_en_i : std_logic;\nsi" "gnal sm_Config_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'PKT_BUF_SEL'\nsignal sm_PKT_BUF_SEL_" "din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_PKT_BUF_SEL_en_i : std_logic;\nsignal sm_P" "KT_BUF_SEL_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'Output_Scaling'\nsignal sm_Output_Scalin" "g_din_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_Output_Scaling_en_i : std_logic;\nsignal" " sm_Output_Scaling_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'TX_START'\nsignal sm_TX_START_di" "n_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_TX_START_en_i : std_logic;\nsignal sm_TX_STA" "RT_dout_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'FFT_Config'\nsignal sm_FFT_Config_din_i : std_" "logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_FFT_Config_en_i : std_logic;\nsignal sm_FFT_Config_dout_" "i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'From FIFO'\n-- 'To FIFO'\n-- 'Shared Memory'\n\ntype t_r" "ead_state is (IDLE, READ_PREP, READ_DATA);\nsignal read_state : t_read_state;\n\ntype t_write_state is (IDLE, WRITE" "_DATA, WRITE_RESPONSE);\nsignal write_state : t_write_state;\n\ntype t_memmap_state is (READ, WRITE);\nsignal memma" "p_state : t_memmap_state;\n\nconstant C_READ_PREP_DELAY : std_logic_vector(1 downto 0) := \"11\";\n\nsignal read_pr" "ep_counter : std_logic_vector(1 downto 0);\nsignal read_addr_counter : std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downt" "o 0);\nsignal read_data_counter : std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downto 0);\n\n-- enable of shared BRAMs\ns" "ignal s_shram_en : std_logic;\n\nsignal write_addr_valid : std_logic;\nsignal write_ready : std_logic;\n\n-- 're' o" "f From/To FIFOs\nsignal s_fifo_re : std_logic;\n-- 'we' of To FIFOs\nsignal s_fifo_we : std_logic;\n\nbegin\n\n-- e" "nable for 'Shared Memory' blocks\n\n-- conversion to match with the data bus width\n-- 'From Register'\n-- 'STATUS'" "\ngen_sm_STATUS_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_STATUS_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32)" " <= (others => '0');\nend generate gen_sm_STATUS_dout_i;\nsm_STATUS_dout_i(32-1 downto 0) <= sm_STATUS_dout;\n-- 'T" "o Register'\n-- 'Timing'\nsm_Timing_din <= sm_Timing_din_i(32-1 downto 0);\nsm_Timing_en <= sm_Timing_en_i" ";\ngen_sm_Timing_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_Timing_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32" ") <= (others => '0');\nend generate gen_sm_Timing_dout_i;\nsm_Timing_dout_i(32-1 downto 0) <= sm_Timing_dout;\n-- '" "Config'\nsm_Config_din <= sm_Config_din_i(32-1 downto 0);\nsm_Config_en <= sm_Config_en_i;\ngen_sm_Config_" "dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_Config_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '" "0');\nend generate gen_sm_Config_dout_i;\nsm_Config_dout_i(32-1 downto 0) <= sm_Config_dout;\n-- 'PKT_BUF_SEL'\nsm_" "PKT_BUF_SEL_din <= sm_PKT_BUF_SEL_din_i(32-1 downto 0);\nsm_PKT_BUF_SEL_en <= sm_PKT_BUF_SEL_en_i;\ngen_sm" "_PKT_BUF_SEL_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n sm_PKT_BUF_SEL_dout_i(C_S_AXI_DATA_WIDTH-1 downto 3" "2) <= (others => '0');\nend generate gen_sm_PKT_BUF_SEL_dout_i;\nsm_PKT_BUF_SEL_dout_i(32-1 downto 0) <= sm_PKT_BUF" "_SEL_dout;\n-- 'Output_Scaling'\nsm_Output_Scaling_din <= sm_Output_Scaling_din_i(32-1 downto 0);\nsm_Output_Sc" "aling_en <= sm_Output_Scaling_en_i;\ngen_sm_Output_Scaling_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n " "sm_Output_Scaling_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_Output_Scaling_do" "ut_i;\nsm_Output_Scaling_dout_i(32-1 downto 0) <= sm_Output_Scaling_dout;\n-- 'TX_START'\nsm_TX_START_din <= sm" "_TX_START_din_i(32-1 downto 0);\nsm_TX_START_en <= sm_TX_START_en_i;\ngen_sm_TX_START_dout_i: if (32 < C_S_AXI" "_DATA_WIDTH) generate\n sm_TX_START_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen" "_sm_TX_START_dout_i;\nsm_TX_START_dout_i(32-1 downto 0) <= sm_TX_START_dout;\n-- 'FFT_Config'\nsm_FFT_Config_din " " <= sm_FFT_Config_din_i(32-1 downto 0);\nsm_FFT_Config_en <= sm_FFT_Config_en_i;\ngen_sm_FFT_Config_dout_i: i" "f (32 < C_S_AXI_DATA_WIDTH) generate\n sm_FFT_Config_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\n" "end generate gen_sm_FFT_Config_dout_i;\nsm_FFT_Config_dout_i(32-1 downto 0) <= sm_FFT_Config_dout;\n-- 'From FIFO'\n" "-- 'To FIFO'\n-- 'Shared Memory'\n\nReadWriteSelect: process(memmap_state) is begin\n if (memmap_state = READ) t" "hen\n else\n end if;\nend process ReadWriteSelect;\n\n-------------------------------------------------------" "----------------------\n-- address for 'Shared Memory'\n-----------------------------------------------------------" "------------------\nSharedMemory_Addr_ResetN : process(AXI_AClk) is begin\n if (AXI_AClk'event and AXI_AClk = '1" "') then\n if (AXI_AResetN = '0') then\n memmap_state <= READ;\n else\n if (S_AX" "I_AWVALID = '1') then\n -- write operation\n memmap_state <= WRITE;\n elsi" "f (S_AXI_ARVALID = '1') then\n -- read operation\n memmap_state <= READ;\n " " end if;\n end if;\n end if;\nend process SharedMemory_Addr_ResetN;\n\n----------------------------------" "-------------------------------------------\n-- WRITE Command Control\n--------------------------------------------" "---------------------------------\nS_AXI_BID <= S_AXI_BID_i;\nS_AXI_BVALID <= S_AXI_BVALID_i;\nS_AXI_WREADY <" "= S_AXI_WREADY_i;\n-- No error checking\nS_AXI_BRESP <= (others=>'0');\n\nPROC_AWREADY_ACK: process(read_state, wr" "ite_state, S_AXI_ARVALID, S_AXI_AWVALID) is begin\n if (write_state = IDLE and S_AXI_AWVALID = '1' and read_stat" "e = IDLE) then\n S_AXI_AWREADY <= S_AXI_AWVALID;\n else\n S_AXI_AWREADY <= '0';\n end if;\nend " "process PROC_AWREADY_ACK;\n\nCmd_Decode_Write: process(AXI_AClk) is begin\n if (AXI_AClk'event and AXI_AClk = '1" "') then\n if (AXI_AResetN = '0') then\n write_addr_valid <= '0';\n write_ready " " <= '0';\n s_fifo_we <= '0';\n S_AXI_BVALID_i <= '0';\n S_AXI_BI" "D_i <= (others => '0');\n write_bank_addr_i <= (others => '0');\n write_linear_addr" "_i <= (others => '0');\n else\n if (write_state = IDLE) then\n if (S_AXI_AWVALID =" " '1' and read_state = IDLE) then\n -- reflect awid\n S_AXI_BID_i <= S_AXI_AWI" "D;\n\n -- latch bank and linear addresses\n write_bank_addr_i <= S_AXI_AWAD" "DR(C_S_AXI_TOTAL_ADDR_LEN-1 downto C_S_AXI_LINEAR_ADDR_LEN+2);\n write_linear_addr_i <= S_AXI_AW" "ADDR(C_S_AXI_LINEAR_ADDR_LEN+1 downto 2);\n write_addr_valid <= '1';\n s_fifo" "_we <= '1';\n\n -- write state transition\n write_state <= WRITE_DATA;\n " " end if;\n elsif (write_state = WRITE_DATA) then\n write_ready <= '1';\n " " s_fifo_we <= '0';\n write_addr_valid <= S_AXI_WVALID;\n \n if" " (S_AXI_WVALID = '1' and write_ready = '1') then\n write_linear_addr_i <= Std_Logic_Vector(unsig" "ned(write_linear_addr_i) + 1);\n end if;\n\n if (S_AXI_WLAST = '1' and write_ready = " "'1') then\n -- start responding through B channel upon the last write data sample\n " " S_AXI_BVALID_i <= '1';\n -- write data is over\n write_addr_valid <= '" "0';\n write_ready <= '0';\n -- write state transition\n wr" "ite_state <= WRITE_RESPONSE;\n end if;\n elsif (write_state = WRITE_RESPONSE) then\n\n " " if (S_AXI_BREADY = '1') then\n -- write respond is over\n S_AXI_" "BVALID_i <= '0';\n S_AXI_BID_i <= (others => '0');\n\n -- write state transit" "ion\n write_state <= IDLE;\n end if;\n end if;\n end if;\n e" "nd if;\nend process Cmd_Decode_Write;\n\nWrite_Linear_Addr_Decode : process(AXI_AClk) is \n\nbegin\n if (AXI_ACl" "k'event and AXI_AClk = '1') then\n if (AXI_AResetN = '0') then\n -- 'To Register'\n --" " Timing din/en\n sm_Timing_din_i <= (others => '0');\n sm_Timing_en_i <= '0';\n --" " Config din/en\n sm_Config_din_i <= (others => '0');\n sm_Config_en_i <= '0';\n --" " PKT_BUF_SEL din/en\n sm_PKT_BUF_SEL_din_i <= (others => '0');\n sm_PKT_BUF_SEL_en_i <= '0';\n" " -- Output_Scaling din/en\n sm_Output_Scaling_din_i <= (others => '0');\n sm_Outpu" "t_Scaling_en_i <= '0';\n -- TX_START din/en\n sm_TX_START_din_i <= (others => '0');\n " " sm_TX_START_en_i <= '0';\n -- FFT_Config din/en\n sm_FFT_Config_din_i <= (others => '0');" "\n sm_FFT_Config_en_i <= '0';\n -- 'To FIFO'\n -- 'Shared Memory'\n else\n " " -- default assignments\n\n -- 'To Register'\n if (unsigned(write_bank_addr_i) = 2)" " then\n if (unsigned(write_linear_addr_i) = 0) then\n -- Timing din/en\n " " sm_Timing_din_i <= S_AXI_WDATA;\n sm_Timing_en_i <= write_addr_valid;\n " " elsif (unsigned(write_linear_addr_i) = 1) then\n -- Config din/en\n sm_Con" "fig_din_i <= S_AXI_WDATA;\n sm_Config_en_i <= write_addr_valid;\n elsif (unsigne" "d(write_linear_addr_i) = 2) then\n -- PKT_BUF_SEL din/en\n sm_PKT_BUF_SEL_din" "_i <= S_AXI_WDATA;\n sm_PKT_BUF_SEL_en_i <= write_addr_valid;\n elsif (unsigned(" "write_linear_addr_i) = 3) then\n -- Output_Scaling din/en\n sm_Output_Scaling" "_din_i <= S_AXI_WDATA;\n sm_Output_Scaling_en_i <= write_addr_valid;\n elsif (un" "signed(write_linear_addr_i) = 4) then\n -- TX_START din/en\n sm_TX_START_din_" "i <= S_AXI_WDATA;\n sm_TX_START_en_i <= write_addr_valid;\n elsif (unsigned(writ" "e_linear_addr_i) = 5) then\n -- FFT_Config din/en\n sm_FFT_Config_din_i <= S_" "AXI_WDATA;\n sm_FFT_Config_en_i <= write_addr_valid;\n end if;\n end " "if; \n \n \n end if;\n end if;\nend process Write_Linear_Addr_Decode;\n \n----------" "-------------------------------------------------------------------\n-- READ Control\n-----------------------------" "------------------------------------------------\n\nS_AXI_RDATA <= S_AXI_RDATA_i;\nS_AXI_RVALID <= S_AXI_RVALID_i" ";\nS_AXI_RLAST <= S_AXI_RLAST_i;\nS_AXI_RID <= S_AXI_RID_i;\n-- TODO: no error checking\nS_AXI_RRESP <= (othe" "rs=>'0');\n\nPROC_ARREADY_ACK: process(read_state, S_AXI_ARVALID, write_state, S_AXI_AWVALID) is begin\n -- Note" ": WRITE has higher priority than READ\n if (read_state = IDLE and S_AXI_ARVALID = '1' and write_state = IDLE and" " S_AXI_AWVALID /= '1') then\n S_AXI_ARREADY <= S_AXI_ARVALID;\n else\n S_AXI_ARREADY <= '0';\n " "end if;\nend process PROC_ARREADY_ACK;\n\nS_AXI_WREADY_i <= write_ready;\n\nProcess_Sideband: process(write_state, " "read_state) is begin\n if (read_state = READ_PREP) then\n s_shram_en <= '1';\n elsif (read_state = REA" "D_DATA) then\n s_shram_en <= S_AXI_RREADY;\n elsif (write_state = WRITE_DATA) then\n s_shram_en <=" " S_AXI_WVALID;\n else\n s_shram_en <= '0';\n end if;\nend process Process_Sideband;\n\nCmd_Decode_Read" ": process(AXI_AClk) is begin\n if (AXI_AClk'event and AXI_AClk = '1') then\n if (AXI_AResetN = '0') then\n" " S_AXI_RVALID_i <= '0';\n read_bank_addr_i <= (others => '0');\n read_linear_ad" "dr_i <= (others => '0');\n S_AXI_ARLEN_i <= (others => '0');\n S_AXI_RLAST_i <= " "'0';\n S_AXI_RID_i <= (others => '0');\n read_state <= IDLE;\n re" "ad_prep_counter <= (others => '0');\n read_addr_counter <= (others => '0');\n read_data_c" "ounter <= (others => '0');\n else\n -- default assignments\n s_fifo_re <= '0';\n\n " " if (read_state = IDLE) then\n -- Note WRITE has higher priority than READ\n " " if (S_AXI_ARVALID = '1' and write_state = IDLE and S_AXI_AWVALID /= '1') then\n -- extract bank" " and linear addresses\n read_bank_addr_i <= S_AXI_ARADDR(C_S_AXI_TOTAL_ADDR_LEN-1 downto C_S_" "AXI_LINEAR_ADDR_LEN+2);\n read_linear_addr_i <= S_AXI_ARADDR(C_S_AXI_LINEAR_ADDR_LEN+1 downto 2" ");\n s_fifo_re <= '1';\n\n -- reflect arid\n S_AXI_RID_i <" "= S_AXI_ARID;\n\n -- load read liner address and data counter\n read_addr_cou" "nter <= S_AXI_ARLEN;\n read_data_counter <= S_AXI_ARLEN;\n\n -- load read pre" "paration counter\n read_prep_counter <= C_READ_PREP_DELAY;\n -- read state tr" "ansition\n read_state <= READ_PREP;\n end if;\n elsif (read_state = RE" "AD_PREP) then\n if (unsigned(read_prep_counter) = 0) then\n if (unsigned(read_dat" "a_counter) = 0) then\n -- tag the last data generated by the slave\n " "S_AXI_RLAST_i <= '1';\n end if;\n -- valid data appears\n " "S_AXI_RVALID_i <= '1';\n -- read state transition\n read_state <= READ_DATA;\n" " else\n -- decrease read preparation counter\n read_prep_count" "er <= Std_Logic_Vector(unsigned(read_prep_counter) - 1);\n end if;\n\n if (unsigned(r" "ead_prep_counter) /= 3 and unsigned(read_addr_counter) /= 0) then\n -- decrease address counter\n" " read_addr_counter <= Std_Logic_Vector(unsigned(read_addr_counter) - 1);\n --" " increase linear address (no band crossing)\n read_linear_addr_i <= Std_Logic_Vector(unsigned(re" "ad_linear_addr_i) + 1);\n end if;\n elsif (read_state = READ_DATA) then\n " "if (S_AXI_RREADY = '1') then\n if (unsigned(read_data_counter) = 1) then\n " " -- tag the last data generated by the slave\n S_AXI_RLAST_i <= '1';\n e" "nd if;\n\n if (unsigned(read_data_counter) = 0) then\n -- arid\n " " S_AXI_RID_i <= (others => '0');\n -- rlast\n S_AXI_RLA" "ST_i <= '0';\n -- no more valid data\n S_AXI_RVALID_i <= '0';\n " " -- read state transition\n read_state <= IDLE;\n else\n" " -- decrease read preparation counter\n read_data_counter <= Std_Logi" "c_Vector(unsigned(read_data_counter) - 1);\n\n if (unsigned(read_addr_counter) /= 0) then\n " " -- decrease address counter\n read_addr_counter <= Std_Logic_" "Vector(unsigned(read_addr_counter) - 1);\n -- increase linear address (no band crossing)" "\n read_linear_addr_i <= Std_Logic_Vector(unsigned(read_linear_addr_i) + 1);\n " " end if;\n end if;\n end if;\n end if;\n\n end if;" "\n end if;\nend process Cmd_Decode_Read;\n\nRead_Linear_Addr_Decode : process(AXI_AClk) is begin\n if (AXI_AC" "lk'event and AXI_AClk = '1') then\n if (AXI_AResetN = '0') then\n reg_bank_out_i <= (others => " "'0');\n fifo_bank_out_i <= (others => '0');\n shmem_bank_out_i <= (others => '0');\n " " S_AXI_RDATA_i <= (others => '0');\n else\n if (unsigned(read_bank_addr_i) = 2) then\n " " -- 'From Register'\n if (unsigned(read_linear_addr_i) = 6) then\n -- '" "STATUS' dout\n reg_bank_out_i <= sm_STATUS_dout_i;\n end if;\n -- " "'To Register' (with register readback)\n if (unsigned(read_linear_addr_i) = 0) then\n " " -- 'Timing' dout\n reg_bank_out_i <= sm_Timing_dout_i;\n elsif (unsigned(rea" "d_linear_addr_i) = 1) then\n -- 'Config' dout\n reg_bank_out_i <= sm_Config_d" "out_i;\n elsif (unsigned(read_linear_addr_i) = 2) then\n -- 'PKT_BUF_SEL' dout\n " " reg_bank_out_i <= sm_PKT_BUF_SEL_dout_i;\n elsif (unsigned(read_linear_addr_i) = " "3) then\n -- 'Output_Scaling' dout\n reg_bank_out_i <= sm_Output_Scaling_dout" "_i;\n elsif (unsigned(read_linear_addr_i) = 4) then\n -- 'TX_START' dout\n " " reg_bank_out_i <= sm_TX_START_dout_i;\n elsif (unsigned(read_linear_addr_i) = 5) then\n" " -- 'FFT_Config' dout\n reg_bank_out_i <= sm_FFT_Config_dout_i;\n " " end if;\n\n S_AXI_RDATA_i <= reg_bank_out_i;\n elsif (unsigned(read_bank_addr_i) = 1)" " then\n -- 'From FIFO'\n -- 'To FIFO'\n\n S_AXI_RDATA_i <= fifo_bank_o" "ut_i;\n elsif (unsigned(read_bank_addr_i) = 0 and s_shram_en = '1') then\n -- 'Shared Mem" "ory'\n\n S_AXI_RDATA_i <= shmem_bank_out_i;\n end if;\n end if;\n end if;\nend " "process Read_Linear_Addr_Decode;\n\nend architecture IMP;\n" config "{'inports'=>[{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'AXI_ARESETN','wid" "th'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARADDR','width'=>32},{'arit" "h_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARBURST','width'=>2},{'arith_type'=>2.000" "00000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARCACHE','width'=>4},{'arith_type'=>2.00000000000000000" ",'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARID','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.0000" "0000000000000,'name'=>'S_AXI_ARLEN','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'n" "ame'=>'S_AXI_ARLOCK','width'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AR" "PROT','width'=>3},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARSIZE','width'=>" "3},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARVALID','width'=>0},{'arith_typ" "e'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWADDR','width'=>32},{'arith_type'=>2.00000000" "000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWBURST','width'=>2},{'arith_type'=>2.00000000000000000,'bin" "_pt'=>0.00000000000000000,'name'=>'S_AXI_AWCACHE','width'=>4},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.000000" "00000000000,'name'=>'S_AXI_AWID','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name" "'=>'S_AXI_AWLEN','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWLOCK" "','width'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWPROT','width'=>3},{" "'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWSIZE','width'=>3},{'arith_type'=>2" ".00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWVALID','width'=>0},{'arith_type'=>2.0000000000000" "0000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_BREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>" "0.00000000000000000,'name'=>'S_AXI_RREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.0000000000000" "0000,'name'=>'S_AXI_WDATA','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S" "_AXI_WLAST','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_WSTRB','wid" "th'=>4},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_WVALID','width'=>0},{'arith" "_type'=>2,'bin_pt'=>0,'name'=>'sm_STATUS_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_Timing_dout','" "width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_Config_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=" ">'sm_PKT_BUF_SEL_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_Output_Scaling_dout','width'=>32},{'ar" "ith_type'=>2,'bin_pt'=>0,'name'=>'sm_TX_START_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_FFT_Confi" "g_dout','width'=>32}],'outports'=>[{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_" "ARREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWREADY','widt" "h'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_BID','width'=>8},{'arith_typ" "e'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_BRESP','width'=>2},{'arith_type'=>2.0000000000" "0000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_BVALID','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt" "'=>0.00000000000000000,'name'=>'S_AXI_RDATA','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.0000000000" "0000000,'name'=>'S_AXI_RID','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S" "_AXI_RLAST','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_RRESP','wid" "th'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_RVALID','width'=>0},{'arith" "_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_WREADY','width'=>0},{'arith_type'=>2,'bin_" "pt'=>0,'name'=>'sm_Timing_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'" "=>'sm_Timing_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_Config_din','width'=>32},{'" "arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_Config_en','width'=>0.00000000000000000}" ",{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_PKT_BUF_SEL_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'" "=>0.00000000000000000,'name'=>'sm_PKT_BUF_SEL_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'" "=>'sm_Output_Scaling_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm" "_Output_Scaling_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_TX_START_din','width'=>3" "2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_TX_START_en','width'=>0.00000000000" "000000},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_FFT_Config_din','width'=>32},{'arith_type'=>2.00000000000000000,'b" "in_pt'=>0.00000000000000000,'name'=>'sm_FFT_Config_en','width'=>0.00000000000000000}]}" inheritDeviceType "inheritDeviceType" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "edkcore" sg_icon_stat "250,966,32,23,white,blue,0,0db5fece,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 250 250 0 0 ],[0 0 966 966 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 250 250 0 0 ],[0 0 966 966 0 ]);\npatch([47.125 97.7 132.7 167.7 202.7 132.7 82.125 47.125 ],[521" ".85 521.85 556.85 521.85 556.85 556.85 556.85 521.85 ],[1 1 1 ]);\npatch([82.125 132.7 97.7 47.125 82.125 ],[486.85" " 486.85 521.85 521.85 486.85 ],[0.931 0.946 0.973 ]);\npatch([47.125 97.7 132.7 82.125 47.125 ],[451.85 451.85 486." "85 486.85 451.85 ],[1 1 1 ]);\npatch([82.125 202.7 167.7 132.7 97.7 47.125 82.125 ],[416.85 416.85 451.85 416.85 45" "1.85 451.85 416.85 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin " "icon text');\ncolor('black');port_label('input',1,'AXI_ARESETN');\ncolor('black');port_label('input',2,'S_AXI_ARADD" "R');\ncolor('black');port_label('input',3,'S_AXI_ARBURST');\ncolor('black');port_label('input',4,'S_AXI_ARCACHE');\n" "color('black');port_label('input',5,'S_AXI_ARID');\ncolor('black');port_label('input',6,'S_AXI_ARLEN');\ncolor('bla" "ck');port_label('input',7,'S_AXI_ARLOCK');\ncolor('black');port_label('input',8,'S_AXI_ARPROT');\ncolor('black');po" "rt_label('input',9,'S_AXI_ARSIZE');\ncolor('black');port_label('input',10,'S_AXI_ARVALID');\ncolor('black');port_la" "bel('input',11,'S_AXI_AWADDR');\ncolor('black');port_label('input',12,'S_AXI_AWBURST');\ncolor('black');port_label(" "'input',13,'S_AXI_AWCACHE');\ncolor('black');port_label('input',14,'S_AXI_AWID');\ncolor('black');port_label('input" "',15,'S_AXI_AWLEN');\ncolor('black');port_label('input',16,'S_AXI_AWLOCK');\ncolor('black');port_label('input',17,'" "S_AXI_AWPROT');\ncolor('black');port_label('input',18,'S_AXI_AWSIZE');\ncolor('black');port_label('input',19,'S_AXI" "_AWVALID');\ncolor('black');port_label('input',20,'S_AXI_BREADY');\ncolor('black');port_label('input',21,'S_AXI_RRE" "ADY');\ncolor('black');port_label('input',22,'S_AXI_WDATA');\ncolor('black');port_label('input',23,'S_AXI_WLAST');\n" "color('black');port_label('input',24,'S_AXI_WSTRB');\ncolor('black');port_label('input',25,'S_AXI_WVALID');\ncolor(" "'black');port_label('input',26,'sm_STATUS_dout');\ncolor('black');port_label('input',27,'sm_Timing_dout');\ncolor('" "black');port_label('input',28,'sm_Config_dout');\ncolor('black');port_label('input',29,'sm_PKT_BUF_SEL_dout');\ncol" "or('black');port_label('input',30,'sm_Output_Scaling_dout');\ncolor('black');port_label('input',31,'sm_TX_START_dou" "t');\ncolor('black');port_label('input',32,'sm_FFT_Config_dout');\ncolor('black');port_label('output',1,'S_AXI_ARRE" "ADY');\ncolor('black');port_label('output',2,'S_AXI_AWREADY');\ncolor('black');port_label('output',3,'S_AXI_BID');\n" "color('black');port_label('output',4,'S_AXI_BRESP');\ncolor('black');port_label('output',5,'S_AXI_BVALID');\ncolor(" "'black');port_label('output',6,'S_AXI_RDATA');\ncolor('black');port_label('output',7,'S_AXI_RID');\ncolor('black');" "port_label('output',8,'S_AXI_RLAST');\ncolor('black');port_label('output',9,'S_AXI_RRESP');\ncolor('black');port_la" "bel('output',10,'S_AXI_RVALID');\ncolor('black');port_label('output',11,'S_AXI_WREADY');\ncolor('black');port_label" "('output',12,'sm_Timing_din');\ncolor('black');port_label('output',13,'sm_Timing_en');\ncolor('black');port_label('" "output',14,'sm_Config_din');\ncolor('black');port_label('output',15,'sm_Config_en');\ncolor('black');port_label('ou" "tput',16,'sm_PKT_BUF_SEL_din');\ncolor('black');port_label('output',17,'sm_PKT_BUF_SEL_en');\ncolor('black');port_l" "abel('output',18,'sm_Output_Scaling_din');\ncolor('black');port_label('output',19,'sm_Output_Scaling_en');\ncolor('" "black');port_label('output',20,'sm_TX_START_din');\ncolor('black');port_label('output',21,'sm_TX_START_en');\ncolor" "('black');port_label('output',22,'sm_FFT_Config_din');\ncolor('black');port_label('output',23,'sm_FFT_Config_en');\n" "fprintf('','COMMENT: end icon text');" } Line { SrcBlock "memmap" SrcPort 13 DstBlock "To Register" DstPort 2 } Line { SrcBlock "memmap" SrcPort 12 DstBlock "To Register" DstPort 1 } Line { SrcBlock "memmap" SrcPort 21 DstBlock "To Register4" DstPort 2 } Line { SrcBlock "memmap" SrcPort 20 DstBlock "To Register4" DstPort 1 } Line { SrcBlock "memmap" SrcPort 17 DstBlock "To Register2" DstPort 2 } Line { SrcBlock "memmap" SrcPort 16 DstBlock "To Register2" DstPort 1 } Line { SrcBlock "memmap" SrcPort 19 DstBlock "To Register3" DstPort 2 } Line { SrcBlock "memmap" SrcPort 18 DstBlock "To Register3" DstPort 1 } Line { SrcBlock "memmap" SrcPort 23 DstBlock "To Register5" DstPort 2 } Line { SrcBlock "memmap" SrcPort 22 DstBlock "To Register5" DstPort 1 } Line { SrcBlock "memmap" SrcPort 15 DstBlock "To Register1" DstPort 2 } Line { SrcBlock "memmap" SrcPort 14 DstBlock "To Register1" DstPort 1 } Line { SrcBlock "memmap" SrcPort 11 DstBlock "S_AXI_WREADY" DstPort 1 } Line { SrcBlock "memmap" SrcPort 10 DstBlock "S_AXI_RVALID" DstPort 1 } Line { SrcBlock "memmap" SrcPort 9 DstBlock "S_AXI_RRESP" DstPort 1 } Line { SrcBlock "memmap" SrcPort 8 DstBlock "S_AXI_RLAST" DstPort 1 } Line { SrcBlock "memmap" SrcPort 7 DstBlock "S_AXI_RID" DstPort 1 } Line { SrcBlock "memmap" SrcPort 6 DstBlock "S_AXI_RDATA" DstPort 1 } Line { SrcBlock "memmap" SrcPort 5 DstBlock "S_AXI_BVALID" DstPort 1 } Line { SrcBlock "memmap" SrcPort 4 DstBlock "S_AXI_BRESP" DstPort 1 } Line { SrcBlock "memmap" SrcPort 3 DstBlock "S_AXI_BID" DstPort 1 } Line { SrcBlock "memmap" SrcPort 2 DstBlock "S_AXI_AWREADY" DstPort 1 } Line { SrcBlock "memmap" SrcPort 1 DstBlock "S_AXI_ARREADY" DstPort 1 } Line { SrcBlock "S_AXI_WVALID" SrcPort 1 DstBlock "memmap" DstPort 25 } Line { SrcBlock "S_AXI_WSTRB" SrcPort 1 DstBlock "memmap" DstPort 24 } Line { SrcBlock "S_AXI_WLAST" SrcPort 1 DstBlock "memmap" DstPort 23 } Line { SrcBlock "S_AXI_WDATA" SrcPort 1 DstBlock "memmap" DstPort 22 } Line { SrcBlock "S_AXI_RREADY" SrcPort 1 DstBlock "memmap" DstPort 21 } Line { SrcBlock "S_AXI_BREADY" SrcPort 1 DstBlock "memmap" DstPort 20 } Line { SrcBlock "S_AXI_AWVALID" SrcPort 1 DstBlock "memmap" DstPort 19 } Line { SrcBlock "S_AXI_AWSIZE" SrcPort 1 DstBlock "memmap" DstPort 18 } Line { SrcBlock "S_AXI_AWPROT" SrcPort 1 DstBlock "memmap" DstPort 17 } Line { SrcBlock "S_AXI_AWLOCK" SrcPort 1 DstBlock "memmap" DstPort 16 } Line { SrcBlock "S_AXI_AWLEN" SrcPort 1 DstBlock "memmap" DstPort 15 } Line { SrcBlock "S_AXI_AWID" SrcPort 1 DstBlock "memmap" DstPort 14 } Line { SrcBlock "S_AXI_AWCACHE" SrcPort 1 DstBlock "memmap" DstPort 13 } Line { SrcBlock "S_AXI_AWBURST" SrcPort 1 DstBlock "memmap" DstPort 12 } Line { SrcBlock "S_AXI_AWADDR" SrcPort 1 DstBlock "memmap" DstPort 11 } Line { SrcBlock "S_AXI_ARVALID" SrcPort 1 DstBlock "memmap" DstPort 10 } Line { SrcBlock "S_AXI_ARSIZE" SrcPort 1 DstBlock "memmap" DstPort 9 } Line { SrcBlock "S_AXI_ARPROT" SrcPort 1 DstBlock "memmap" DstPort 8 } Line { SrcBlock "S_AXI_ARLOCK" SrcPort 1 DstBlock "memmap" DstPort 7 } Line { SrcBlock "S_AXI_ARLEN" SrcPort 1 DstBlock "memmap" DstPort 6 } Line { SrcBlock "S_AXI_ARID" SrcPort 1 DstBlock "memmap" DstPort 5 } Line { SrcBlock "S_AXI_ARCACHE" SrcPort 1 DstBlock "memmap" DstPort 4 } Line { SrcBlock "S_AXI_ARBURST" SrcPort 1 DstBlock "memmap" DstPort 3 } Line { SrcBlock "S_AXI_ARADDR" SrcPort 1 DstBlock "memmap" DstPort 2 } Line { SrcBlock "AXI_ARESETN" SrcPort 1 DstBlock "memmap" DstPort 1 } Line { SrcBlock "To Register" SrcPort 1 DstBlock "memmap" DstPort 27 } Line { SrcBlock "To Register4" SrcPort 1 DstBlock "memmap" DstPort 31 } Line { SrcBlock "From Register" SrcPort 1 DstBlock "memmap" DstPort 26 } Line { SrcBlock "To Register2" SrcPort 1 DstBlock "memmap" DstPort 29 } Line { SrcBlock "To Register3" SrcPort 1 DstBlock "memmap" DstPort 30 } Line { SrcBlock "To Register5" SrcPort 1 DstBlock "memmap" DstPort 32 } Line { SrcBlock "To Register1" SrcPort 1 DstBlock "memmap" DstPort 28 } Line { SrcBlock "S_AXI_WREADY" SrcPort 1 DstBlock "Terminator10" DstPort 1 } Line { SrcBlock "S_AXI_RVALID" SrcPort 1 DstBlock "Terminator9" DstPort 1 } Line { SrcBlock "S_AXI_RRESP" SrcPort 1 DstBlock "Terminator8" DstPort 1 } Line { SrcBlock "S_AXI_RLAST" SrcPort 1 DstBlock "Terminator7" DstPort 1 } Line { SrcBlock "S_AXI_RID" SrcPort 1 DstBlock "Terminator6" DstPort 1 } Line { SrcBlock "S_AXI_RDATA" SrcPort 1 DstBlock "Terminator5" DstPort 1 } Line { SrcBlock "S_AXI_BVALID" SrcPort 1 DstBlock "Terminator4" DstPort 1 } Line { SrcBlock "S_AXI_BRESP" SrcPort 1 DstBlock "Terminator3" DstPort 1 } Line { SrcBlock "S_AXI_BID" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "S_AXI_AWREADY" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "S_AXI_ARREADY" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "Constant24" SrcPort 1 DstBlock "S_AXI_WVALID" DstPort 1 } Line { SrcBlock "Constant23" SrcPort 1 DstBlock "S_AXI_WSTRB" DstPort 1 } Line { SrcBlock "Constant22" SrcPort 1 DstBlock "S_AXI_WLAST" DstPort 1 } Line { SrcBlock "Constant21" SrcPort 1 DstBlock "S_AXI_WDATA" DstPort 1 } Line { SrcBlock "Constant20" SrcPort 1 DstBlock "S_AXI_RREADY" DstPort 1 } Line { SrcBlock "Constant19" SrcPort 1 DstBlock "S_AXI_BREADY" DstPort 1 } Line { SrcBlock "Constant18" SrcPort 1 DstBlock "S_AXI_AWVALID" DstPort 1 } Line { SrcBlock "Constant17" SrcPort 1 DstBlock "S_AXI_AWSIZE" DstPort 1 } Line { SrcBlock "Constant16" SrcPort 1 DstBlock "S_AXI_AWPROT" DstPort 1 } Line { SrcBlock "Constant15" SrcPort 1 DstBlock "S_AXI_AWLOCK" DstPort 1 } Line { SrcBlock "Constant14" SrcPort 1 DstBlock "S_AXI_AWLEN" DstPort 1 } Line { SrcBlock "Constant13" SrcPort 1 DstBlock "S_AXI_AWID" DstPort 1 } Line { SrcBlock "Constant12" SrcPort 1 DstBlock "S_AXI_AWCACHE" DstPort 1 } Line { SrcBlock "Constant11" SrcPort 1 DstBlock "S_AXI_AWBURST" DstPort 1 } Line { SrcBlock "Constant10" SrcPort 1 DstBlock "S_AXI_AWADDR" DstPort 1 } Line { SrcBlock "Constant9" SrcPort 1 DstBlock "S_AXI_ARVALID" DstPort 1 } Line { SrcBlock "Constant8" SrcPort 1 DstBlock "S_AXI_ARSIZE" DstPort 1 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "S_AXI_ARPROT" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "S_AXI_ARLOCK" DstPort 1 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "S_AXI_ARLEN" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "S_AXI_ARID" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "S_AXI_ARCACHE" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "S_AXI_ARBURST" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "S_AXI_ARADDR" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "AXI_ARESETN" DstPort 1 } } } Block { BlockType SubSystem Name "HT Preamble Gen" SID "56" Ports [3, 2] Position [435, 124, 575, 186] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "HT Preamble Gen" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Sym Cfg" SID "57" Position [250, 308, 280, 322] IconDisplay "Port number" } Block { BlockType Inport Name "Start" SID "58" Position [250, 488, 280, 502] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ FIFO tready" SID "2152" Position [250, 598, 280, 612] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType BusCreator Name "Bus Creator" SID "59" Ports [4, 1] Position [1735, 464, 1745, 626] ZOrder -2 ShowName off DisplayOption "bar" } Block { BlockType Reference Name "Concat" SID "60" Ports [2, 1] Position [1450, 455, 1490, 510] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at ze" "ro." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "40,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 55 55 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 55 55 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[32.55 32.55 37.55" " 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[27.55 27.55 32.55 32.55 27.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[22.55 22.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant9" SID "61" Ports [0, 1] Position [1420, 564, 1450, 586] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "ceil(length(ht_preamble_rom)/2) - 1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(length(ht_preamble_rom)))-1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,346a66ac,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14.33" " 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\n" "patch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outp" "ut',1,'63');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "62" Ports [2, 1] Position [1325, 490, 1365, 550] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(length(ht_preamble_rom)))-1" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "40,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 60 60 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[35.55 35.55 40.55" " 35.55 40.55 40.55 40.55 35.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[30.55 30.55 35.55 35.55 30.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[25.55 25.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 20.55 25.55 25.55 20.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "63" Ports [1, 1] Position [1555, 739, 1590, 761] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,22,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "64" Ports [1, 1] Position [1555, 629, 1590, 651] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,22,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IQ tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Delay2" SID "65" Ports [1, 1] Position [1555, 674, 1590, 696] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,22,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IQ tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Delay3" SID "2560" Ports [1, 1] Position [1150, 294, 1185, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,22,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From5" SID "66" Position [905, 512, 990, 528] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "HT Training I" SID "67" Ports [1, 1] Position [1555, 467, 1625, 503] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(ht_preamble_rom)" initVector "real(ht_preamble_rom)" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "70,36,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 70 70 0 0 ],[0 0 36 36 0 ]);\npatch([23.875 31.1 36.1 41.1 46.1 36.1 28.875 23.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([28.875 36.1 31.1 23.875 28.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([23.875 31.1 36.1 28.875 23.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\np" "atch([28.875 46.1 41.1 36.1 31.1 23.875 28.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "HT Training Q" SID "68" Ports [1, 1] Position [1555, 507, 1625, 543] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(ht_preamble_rom)" initVector "imag(ht_preamble_rom)" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "70,36,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 70 70 0 0 ],[0 0 36 36 0 ]);\npatch([23.875 31.1 36.1 41.1 46.1 36.1 28.875 23.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([28.875 36.1 31.1 23.875 28.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([23.875 31.1 36.1 28.875 23.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\np" "atch([28.875 46.1 41.1 36.1 31.1 23.875 28.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter1" SID "69" Ports [1, 1] Position [1225, 496, 1250, 514] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Logical1" SID "70" Ports [2, 1] Position [760, 447, 800, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "71" Ports [2, 1] Position [1020, 512, 1060, 543] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "72" Ports [2, 1] Position [855, 450, 890, 510] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 60 60 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[35.55 35.55 40.55" " 35.55 40.55 40.55 40.55 35.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[30.55 30.55 35.55 35.55 30.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[25.55 25.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 20.55 25.55 25.55 20.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "2151" Ports [2, 1] Position [1225, 517, 1265, 548] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "MCode" SID "2583" Ports [1, 8] Position [415, 255, 665, 370] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of t" "he block are input arguments of the function. The output ports of the block are output arguments of the function." mfname "sym_config_decode" explicit_period on period "1" inputsTable "{'boundInpExpr'=>[''],'inputs'=>['sym_cfg']}" outputsTable "{'outputs'=>['load_base_rate','rotate_bpsk','load_htstf','load_htltf','load_full_rate','pilot_shif" "t','cyclic_prefix','cyclic_shift'],'suppressOut'=>['off','off','off','off','off','off','off','off']}" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "250,115,1,8,white,blue,0,d3620376,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 250 250 0 0 ],[0 0 115 115 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 250 250 0 0 ],[0 0 115 115 0 ]);\npatch([89.4 112.52 128.52 144.52 160.52 128.52 105.4 89.4 ],[74" ".76 74.76 90.76 74.76 90.76 90.76 90.76 74.76 ],[1 1 1 ]);\npatch([105.4 128.52 112.52 89.4 105.4 ],[58.76 58.76 74" ".76 74.76 58.76 ],[0.931 0.946 0.973 ]);\npatch([89.4 112.52 128.52 105.4 89.4 ],[42.76 42.76 58.76 58.76 42.76 ],[" "1 1 1 ]);\npatch([105.4 160.52 144.52 128.52 112.52 89.4 105.4 ],[26.76 26.76 42.76 26.76 42.76 42.76 26.76 ],[0.93" "1 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'sym_cfg');\ncolor('black');port_label('output',1,'load_base_rate');\ncolor('black');port_l" "abel('output',2,'rotate_bpsk');\ncolor('black');port_label('output',3,'load_htstf');\ncolor('black');port_label('ou" "tput',4,'load_htltf');\ncolor('black');port_label('output',5,'load_full_rate');\ncolor('black');port_label('output'" ",6,'pilot_shift');\ncolor('black');port_label('output',7,'cyclic_prefix');\ncolor('black');port_label('output',8,'c" "yclic_shift');\ncolor('black');disp('\\bf{sym\\_config\\_decode}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType Reference Name "Relational2" SID "73" Ports [2, 1] Position [1325, 550, 1365, 585] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,35,2,1,white,blue,0,6218dc92,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22.55 27.55" " 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 22.55 17.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a" "');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmode','on'" ");\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "74" Ports [2, 1] Position [1105, 508, 1135, 537] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "75" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "76" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "77" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "78" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "79" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "80" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "81" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name " Sym Cfg" SID "98" Position [1675, 743, 1705, 757] IconDisplay "Port number" } Block { BlockType Outport Name "IQ stream" SID "99" Position [1830, 538, 1860, 552] Port "2" IconDisplay "Port number" } Line { SrcBlock "Counter1" SrcPort 1 Points [40, 0] Branch { Points [0, -25] DstBlock "Concat" DstPort 2 } Branch { Points [0, 40] DstBlock "Relational2" DstPort 1 } } Line { SrcBlock "Constant9" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [35, 0] Branch { Points [0, -20] DstBlock "Inverter1" DstPort 1 } Branch { Points [0, 115] DstBlock "Delay1" DstPort 1 } Branch { DstBlock "Logical4" DstPort 1 } } Line { SrcBlock "From5" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 Points [-335, 0] Branch { Points [0, -35] DstBlock "Logical2" DstPort 2 } Branch { Points [0, 115] DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 Points [15, 0] Branch { DstBlock "HT Training I" DstPort 1 } Branch { Points [0, 40] DstBlock "HT Training Q" DstPort 1 } } Line { SrcBlock "MCode" SrcPort 4 Points [50, 0] Branch { Points [0, 150] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Delay3" DstPort 1 } } Line { Name "I" Labels [0, 0] SrcBlock "HT Training I" SrcPort 1 DstBlock "Bus Creator" DstPort 1 } Line { Name "Q" Labels [0, 0] SrcBlock "HT Training Q" SrcPort 1 DstBlock "Bus Creator" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 Points [175, 0; 0, 35] DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Sym Cfg" SrcPort 1 Points [90, 0] Branch { Points [0, 435] DstBlock "Delay" DstPort 1 } Branch { DstBlock "MCode" DstPort 1 } } Line { SrcBlock "MCode" SrcPort 3 Points [40, 0; 0, 180] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Sym Cfg" DstPort 1 } Line { Name "IQ tvalid" Labels [2, 0] SrcBlock "Delay1" SrcPort 1 Points [45, 0; 0, -75] DstBlock "Bus Creator" DstPort 3 } Line { Name "IQ tlast" Labels [3, 0] SrcBlock "Delay2" SrcPort 1 Points [50, 0; 0, -80] DstBlock "Bus Creator" DstPort 4 } Line { SrcBlock "Bus Creator" SrcPort 1 DstBlock "IQ stream" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Counter1" DstPort 2 } Line { SrcBlock "IQ FIFO tready" SrcPort 1 Points [900, 0; 0, -65] DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Delay3" SrcPort 1 Points [35, 0; 0, 165] DstBlock "Concat" DstPort 1 } } } Block { BlockType SubSystem Name "IFFT and Cyclic Prefix" SID "100" Ports [5, 4] Position [830, 119, 930, 251] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "IFFT and Cyclic Prefix" Location [622, 224, 1122, 396] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Sym Cfg" SID "105" Position [170, 333, 200, 347] IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "101" Position [170, 363, 200, 377] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "102" Position [170, 393, 200, 407] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "103" Position [170, 423, 200, 437] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "IQ tlast" SID "104" Position [170, 453, 200, 467] Port "5" IconDisplay "Port number" } Block { BlockType SubSystem Name "Buffer and Cyclic Prefix" SID "106" Ports [6, 3] Position [810, 315, 905, 435] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Buffer and Cyclic Prefix" Location [887, 219, 1417, 436] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "107" Position [560, 253, 590, 267] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "108" Position [560, 268, 590, 282] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "xkindex" SID "109" Position [560, 223, 590, 237] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "tvalid" SID "110" Position [560, 303, 590, 317] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "tlast" SID "111" Position [200, 498, 230, 512] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Sym Cfg" SID "112" Position [200, 608, 230, 622] Port "6" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "113" Ports [2, 1] Position [680, 328, 715, 372] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55" " 27.55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27" ".55 27.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "114" Ports [2, 1] Position [475, 302, 510, 373] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "MAX_NUM_SC" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,71,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 71 71 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 71 71 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[40.55" " 40.55 45.55 40.55 45.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[35.55 35.55 40" ".55 40.55 35.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[30.55 30.55 35.55 35.55 30.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[25.55 25.55 30.55 25.55 30.55 30.55 25.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bf{a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');d" "isp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "115" Ports [0, 1] Position [755, 381, 770, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "116" Ports [0, 1] Position [755, 421, 770, 439] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Control" SID "117" Ports [1, 2] Position [485, 484, 565, 526] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Control" Location [202, 556, 902, 894] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "tlast" SID "118" Position [230, 333, 260, 347] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "119" Ports [2, 1] Position [630, 391, 665, 444] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,53,2,1,white,blue,0,e85d8a90,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 53 53 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[31.55 31.55 36." "55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[26.55 26.55 31.55 31.55 26." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texm" "ode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "120" Ports [2, 1] Position [515, 268, 570, 377] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "47" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC + MAX_CP_LEN) + 1)" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,109,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 109 109 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 55 55 0 0 ],[0 0 109 109 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[61.7" "7 61.77 68.77 61.77 68.77 68.77 68.77 61.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[54.77 54.77 6" "1.77 61.77 54.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[47.77 47.77 54.77 54.77 47.7" "7 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[40.77 40.77 47.77 40.77 47.77 47.77 40.77 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\font" "size{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "121" Position [740, 419, 835, 441] ZOrder -9 BlockMirror on NamePlacement "alternate" ShowName off GotoTag "regTx_CP_LEN" TagVisibility "global" } Block { BlockType From Name "From2" SID "122" Position [740, 394, 835, 416] ZOrder -9 BlockMirror on NamePlacement "alternate" ShowName off GotoTag "regTx_NUM_SC" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "123" Ports [1, 1] Position [440, 286, 465, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "124" Ports [1, 1] Position [465, 471, 490, 489] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "125" Ports [2, 1] Position [525, 449, 565, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "126" Ports [2, 1] Position [520, 389, 565, 431] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,6218dc92,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "127" Ports [2, 1] Position [335, 333, 365, 362] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "128" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "129" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "130" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "131" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "132" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "133" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "134" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name "Rd Addr" SID "135" Position [660, 318, 690, 332] IconDisplay "Port number" } Block { BlockType Outport Name "Valid" SID "136" Position [645, 463, 675, 477] Port "2" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [35, 0] Branch { DstBlock "Counter" DstPort 2 } Branch { Points [0, -55] DstBlock "Inverter1" DstPort 1 } Branch { Points [0, 110] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [15, 0] Branch { Points [0, 75] DstBlock "Relational3" DstPort 1 } Branch { DstBlock "Rd Addr" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 Points [-215, 0] Branch { Points [0, -55] DstBlock "S-R Latch1" DstPort 2 } Branch { Points [0, 70] DstBlock "Inverter2" DstPort 1 } } Line { SrcBlock "Inverter2" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "tlast" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Valid" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Relational3" DstPort 2 } Annotation { Name "Hacky way to skip last cycle of counter. Avoids\nhaving to compute SC+CP-1." Position [510, 516] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Delay" SID "137" Ports [1, 1] Position [865, 468, 890, 492] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "138" Ports [1, 1] Position [865, 503, 890, 527] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bl" "ack');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Dual Port RAM" SID "139" Ports [6, 2] Position [825, 212, 900, 448] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "MAX_NUM_SC * 1" initVector "0" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b off en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" sg_icon_stat "75,236,6,2,white,blue,0,28af736d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 75 75 0 0 ],[0 0 236 236 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 75 75 0 0 ],[0 0 236 236 0 ]);\npatch([14.75 29.2 39.2 49.2 59.2 39.2 24.75 14.75 ],[12" "9.1 129.1 139.1 129.1 139.1 139.1 139.1 129.1 ],[1 1 1 ]);\npatch([24.75 39.2 29.2 14.75 24.75 ],[119.1 119.1 1" "29.1 129.1 119.1 ],[0.931 0.946 0.973 ]);\npatch([14.75 29.2 39.2 24.75 14.75 ],[109.1 109.1 119.1 119.1 109.1 " "],[1 1 1 ]);\npatch([24.75 59.2 49.2 39.2 29.2 14.75 24.75 ],[99.1 99.1 109.1 99.1 109.1 109.1 99.1 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'addra');\ncolor('black');port_label('input',2,'dina');\ncolor('black');port_label('inp" "ut',3,'wea');\ncolor('black');port_label('input',4,'addrb');\ncolor('black');port_label('input',5,'dinb');\ncol" "or('black');port_label('input',6,'web');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_label" "('output',2,'B');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From3" SID "140" Position [305, 344, 400, 366] ZOrder -9 ShowName off GotoTag "regTx_CP_LEN" TagVisibility "global" } Block { BlockType From Name "From4" SID "141" Position [305, 309, 400, 331] ZOrder -9 ShowName off GotoTag "regTx_NUM_SC" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "142" Ports [1, 1] Position [1305, 89, 1340, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IN tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "143" Ports [1, 1] Position [1305, 114, 1340, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IN xkindex" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "144" Ports [1, 1] Position [1305, 139, 1340, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IN tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "145" Ports [1, 1] Position [1305, 164, 1340, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Rd Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "146" Ports [1, 1] Position [1305, 189, 1340, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "147" Ports [1, 1] Position [1305, 214, 1340, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "148" Ports [1, 1] Position [1305, 264, 1340, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "149" Ports [1, 1] Position [1305, 239, 1340, 251] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "I/Q Concat" SID "150" Ports [2, 1] Position [640, 252, 685, 283] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Concat" Location [522, 447, 879, 615] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "151" Position [105, 123, 135, 137] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "152" Position [105, 158, 135, 172] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "153" Ports [2, 1] Position [315, 110, 350, 185] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,75,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 75 75 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 75 75 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[42.55 42.55 47." "55 42.55 47.55 47.55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 42.55 37." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[32.55 32.55 37.55 37.55 32.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 27.55 32.55 32.55 27.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "154" Ports [1, 1] Position [205, 119, 245, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "155" Ports [1, 1] Position [205, 154, 245, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ" SID "156" Position [420, 143, 450, 157] IconDisplay "Port number" } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "IQ" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } } } Block { BlockType SubSystem Name "I/Q Slice" SID "157" Ports [1, 2] Position [1020, 370, 1070, 405] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Slice" Location [1155, 565, 1558, 696] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "158" Position [190, 123, 220, 137] IconDisplay "Port number" } Block { BlockType Reference Name "Reinterpret2" SID "159" Ports [1, 1] Position [350, 119, 390, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "160" Ports [1, 1] Position [350, 144, 390, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "161" Ports [1, 1] Position [265, 119, 300, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "162" Ports [1, 1] Position [265, 144, 300, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "163" Position [450, 123, 480, 137] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "164" Position [450, 148, 480, 162] Port "2" IconDisplay "Port number" } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 Points [15, 0] Branch { DstBlock "Slice" DstPort 1 } Branch { Points [0, 25] DstBlock "Slice1" DstPort 1 } } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } } } Block { BlockType Scope Name "IFFT Buffer" SID "165" Ports [8] Position [1430, 78, 1465, 287] ZOrder -3 Floating off Location [30, 201, 1808, 1160] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "12000" YMin "0~0~0~0~0~-0.5~-0.5~0" YMax "1~100~1~100~1~0.5~0.5~100" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Terminator Name "Terminator" SID "166" Position [940, 262, 955, 278] ZOrder -5 ShowName off } Block { BlockType Outport Name " I" SID "167" Position [1165, 373, 1195, 387] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "168" Position [1165, 388, 1195, 402] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " valid" SID "169" Position [1165, 508, 1195, 522] Port "3" IconDisplay "Port number" } Line { SrcBlock "I/Q Concat" SrcPort 1 DstBlock "Dual Port RAM" DstPort 2 } Line { SrcBlock "Dual Port RAM" SrcPort 2 DstBlock "I/Q Slice" DstPort 1 } Line { SrcBlock "I" SrcPort 1 DstBlock "I/Q Concat" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "I/Q Concat" DstPort 2 } Line { SrcBlock "xkindex" SrcPort 1 Points [175, 0] Branch { DstBlock "Dual Port RAM" DstPort 1 } Branch { Points [0, -110] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "tvalid" SrcPort 1 Points [170, 0] Branch { DstBlock "Dual Port RAM" DstPort 3 } Branch { Points [0, -215] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "tlast" SrcPort 1 Points [30, 0] Branch { Points [0, -360] DstBlock "Gateway Out3" DstPort 1 } Branch { Labels [0, 0] DstBlock "Control" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [10, 0] Branch { Points [55, 0] Branch { DstBlock "Dual Port RAM" DstPort 4 } Branch { Points [0, -180] DstBlock "Gateway Out4" DstPort 1 } } Branch { Points [0, 130] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "From4" SrcPort 1 DstBlock "AddSub2" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "AddSub2" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Dual Port RAM" DstPort 5 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Dual Port RAM" DstPort 6 } Line { SrcBlock "Dual Port RAM" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "I/Q Slice" SrcPort 1 Points [35, 0] Branch { DstBlock " I" DstPort 1 } Branch { Points [0, -160] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "I/Q Slice" SrcPort 2 Points [40, 0] Branch { DstBlock " Q" DstPort 1 } Branch { Points [0, -150] DstBlock "Gateway Out8" DstPort 1 } } Line { Name "IN tvalid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "IFFT Buffer" DstPort 1 } Line { Name "IN xkindex" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "IFFT Buffer" DstPort 2 } Line { Name "IN tlast" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "IFFT Buffer" DstPort 3 } Line { Name "Rd Addr" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "IFFT Buffer" DstPort 4 } Line { Name "OUT valid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "IFFT Buffer" DstPort 5 } Line { Name "OUT I" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "IFFT Buffer" DstPort 6 } Line { Name "OUT index" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "IFFT Buffer" DstPort 8 } Line { SrcBlock "Control" SrcPort 2 DstBlock "Delay3" DstPort 1 } Line { Name "OUT Q" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "IFFT Buffer" DstPort 7 } Line { SrcBlock "Delay" SrcPort 1 Points [80, 0; 0, -210] DstBlock "Gateway Out7" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 Points [210, 0] Branch { DstBlock " valid" DstPort 1 } Branch { Points [0, -320] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Control" SrcPort 1 Points [75, 0; 0, -135] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Sym Cfg" SrcPort 1 Points [135, 0] } Annotation { Name "TODO: Use Sym Cfg values for Cyclic Prefix\nand Cyclic Shift. Will require buffering through\nFFT " "somehow, to keep cfg aligned with corresponding\nsamples. Can't assume upstream logic wil hold cfg\nconstant fo" "r duration of IFFT processing..." Position [200, 686] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "FFT Core" SID "170" Ports [4, 6] Position [565, 295, 725, 415] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FFT Core" Location [322, 117, 2239, 1139] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I " SID "171" Position [225, 238, 255, 252] IconDisplay "Port number" } Block { BlockType Inport Name "Q " SID "172" Position [225, 203, 255, 217] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ In Valid" SID "173" Position [175, 273, 205, 287] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ tlast" SID "174" Position [175, 308, 205, 322] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "176" Ports [0, 1] Position [360, 129, 380, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22" " 13.22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 " "13.22 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]" ");\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "177" Ports [0, 1] Position [385, 339, 400, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13" ".22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.2" "2 11.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\np" "atch([4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outpu" "t',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "178" Ports [0, 1] Position [385, 374, 400, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "15,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 22 22 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[13.22 13" ".22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[11.22 11.22 13.22 13.2" "2 11.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\np" "atch([4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outpu" "t',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "179" Ports [0, 1] Position [360, 164, 380, 186] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22" " 13.22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 " "13.22 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]" ");\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "181" Ports [1, 1] Position [1240, 370, 1285, 400] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display4" SID "182" Ports [1] Position [430, 27, 505, 53] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Scope Name "FFT Ctrl" SID "183" Ports [8] Position [1385, 583, 1420, 792] ZOrder -3 Floating off Location [-1919, 45, 1, 1199] Open off NumInputPorts "8" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "4500" YMin "0~0~0~0~0~0~-1~-1" YMax "1~1~1~1~1~80~1~1" SaveName "ScopeData12" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Scope Name "FFT Status" SID "184" Ports [8] Position [860, 603, 895, 812] ZOrder -3 Floating off Location [137, 232, 1915, 1378] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~0~-1~-1~0~0~0" YMax "1~1~1~1~1~6~6~1" SaveName "ScopeData13" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Fast Fourier Transform 8.0 " SID "185" Ports [10, 17] Position [505, 75, 720, 445] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Fast Fourier Transform 8.0 " SourceType "Xilinx Fast Fourier Transform 8.0 Block" transform_length "64" target_clock_frequency "160" target_data_throughput "50" implementation_options "radix_4_burst_io" run_time_configurable_transform_length off phase_factor_width "16" scaling_options "scaled" rounding_modes "truncation" aclken off aresetn on cyclic_prefix_insertion off output_ordering "bit_reversed_order" throttle_scheme "nonrealtime" xk_index on ovflo on trim_axipin_name on memory_options_data "block_ram" memory_options_phase_factors "block_ram" number_of_stages_using_block_ram_for_data_and_phase_factors "0" memory_options_reorder "block_ram" memory_options_hybrid off complex_mult_type "use_mults_performance" butterfly_type "use_xtremedsp_slices" xl_use_area off xl_area "[0,0,0,0,0,0,0]" channels "1" input_ordering "natural_order" input_width "16" ip_name "Fast Fourier Transform" ip_version "8.0" dsptool_ready "true" ipcore_usecache "true" ipcore_useipmodelcache "true" wrapper_available "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst'}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "xfft_v8_0" sg_icon_stat "215,370,10,17,white,blue,0,d636f25c,right,,[2 2 2 3 3 3 3 4 5 1 ],[2 3 4 4 5 5 5 5 5 5 1 1 " "1 1 1 1 1 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 4 4 ],[352 258 258 352 ],[6.3600" "00e-001 6.760000e-001 7.480000e-001 ]);\npatch([0 0 4 4 ],[247 118 118 247 ],[5.020000e-001 5.320000e-001 5.860" "000e-001 ]);\npatch([0 0 4 4 ],[107 83 83 107 ],[3.680000e-001 3.880000e-001 4.240000e-001 ]);\npatch([0 0 4 4 " "],[72 48 48 72 ],[2.340000e-001 2.440000e-001 2.620000e-001 ]);\npatch([0 0 4 4 ],[37 13 13 37 ],[7.700000e-001" " 8.200000e-001 9.100000e-001 ]);\npatch([211 211 215 215 ],[352 338 338 352 ],[6.360000e-001 6.760000e-001 7.48" "0000e-001 ]);\npatch([211 211 215 215 ],[332 318 318 332 ],[5.020000e-001 5.320000e-001 5.860000e-001 ]);\npatc" "h([211 211 215 215 ],[312 278 278 312 ],[3.680000e-001 3.880000e-001 4.240000e-001 ]);\npatch([211 211 215 215 " "],[272 158 158 272 ],[2.340000e-001 2.440000e-001 2.620000e-001 ]);\npatch([211 211 215 215 ],[152 18 18 152 ]," "[7.700000e-001 8.200000e-001 9.100000e-001 ]);\npatch([4 210 210 4 4 ],[0 0 370 370 0 ],[7.700000e-001 8.200000" "e-001 9.100000e-001 ]);\nplot([4 210 210 4 4 ],[0 0 370 370 0 ]);\n\n\npatch([40.25 83.6 113.6 143.6 173.6 113." "6 70.25 40.25 ],[218.3 218.3 248.3 218.3 248.3 248.3 248.3 218.3 ],[1 1 1 ]);\npatch([70.25 113.6 83.6 40.25 70" ".25 ],[188.3 188.3 218.3 218.3 188.3 ],[0.931 0.946 0.973 ]);\npatch([40.25 83.6 113.6 70.25 40.25 ],[158.3 158" ".3 188.3 188.3 158.3 ],[1 1 1 ]);\npatch([70.25 173.6 143.6 113.6 83.6 40.25 70.25 ],[128.3 128.3 158.3 128.3 1" "58.3 158.3 128.3 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\ncolor('black');port_label('input',1,' config_tdata_scale_sch ');\ncolor('black');port_label('" "input',2,' config_tdata_fwd_inv ');\ncolor('black');port_label('input',3,' config_tvalid ');\ncolor('black'" ");port_label('input',4,' data_tdata_xn_im ');\ncolor('black');port_label('input',5,' data_tdata_xn_re ');\n" "color('black');port_label('input',6,' data_tvalid ');\ncolor('black');port_label('input',7,' data_tlast ');" "\ncolor('black');port_label('input',8,' status_tready ');\ncolor('black');port_label('input',9,' data_tready" " ');\ncolor('black');port_label('input',10,' aresetn ');\ncolor('black');port_label('output',1,' config_tre" "ady ');\ncolor('black');port_label('output',2,' data_tready ');\ncolor('black');port_label('output',3,' sta" "tus_tvalid ');\ncolor('black');port_label('output',4,' status_tdata_ovflo ');\ncolor('black');port_label('ou" "tput',5,' data_tdata_xk_im ');\ncolor('black');port_label('output',6,' data_tdata_xk_re ');\ncolor('black')" ";port_label('output',7,' data_tuser_ovflo ');\ncolor('black');port_label('output',8,' data_tuser_xk_index '" ");\ncolor('black');port_label('output',9,' data_tvalid ');\ncolor('black');port_label('output',10,' data_tla" "st ');\ncolor('black');port_label('output',11,' event_frame_started ');\ncolor('black');port_label('output'," "12,' event_tlast_unexpected ');\ncolor('black');port_label('output',13,' event_tlast_missing ');\ncolor('bl" "ack');port_label('output',14,' event_fft_overflow ');\ncolor('black');port_label('output',15,' event_data_in" "_channel_halt ');\ncolor('black');port_label('output',16,' event_status_channel_halt ');\ncolor('black');por" "t_label('output',17,' event_data_out_channel_halt ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "3558" Position [1020, 743, 1185, 757] ZOrder -9 ShowName off GotoTag "FFT_OUT_xk_re" } Block { BlockType From Name "From10" SID "186" Position [1020, 618, 1185, 632] ZOrder -9 ShowName off GotoTag "FFT_IN_tvalid" } Block { BlockType From Name "From11" SID "187" Position [1020, 643, 1185, 657] ZOrder -9 ShowName off GotoTag "FFT_IN_tlast" } Block { BlockType From Name "From12" SID "188" Position [1020, 668, 1185, 682] ZOrder -9 ShowName off GotoTag "FFT_OUT_data_tvalid" } Block { BlockType From Name "From13" SID "189" Position [1020, 693, 1185, 707] ZOrder -9 ShowName off GotoTag "FFT_OUT_data_tlast" } Block { BlockType From Name "From14" SID "190" Position [1020, 718, 1185, 732] ZOrder -9 ShowName off GotoTag "FFT_OUT_xk_index" } Block { BlockType From Name "From15" SID "191" Position [505, 613, 670, 627] ZOrder -9 ShowName off GotoTag "FFT_IN_tvalid" } Block { BlockType From Name "From16" SID "192" Position [505, 638, 670, 652] ZOrder -9 ShowName off GotoTag "FFT_IN_tlast" } Block { BlockType From Name "From17" SID "193" Position [505, 663, 670, 677] ZOrder -9 ShowName off GotoTag "FFT_event_frame_started" } Block { BlockType From Name "From18" SID "194" Position [505, 688, 670, 702] ZOrder -9 ShowName off GotoTag "FFT_event_tlast_unexpected" } Block { BlockType From Name "From19" SID "195" Position [505, 713, 670, 727] ZOrder -9 ShowName off GotoTag "FFT_event_tlast_missnig" } Block { BlockType From Name "From2" SID "196" Position [65, 409, 160, 431] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType From Name "From20" SID "3559" Position [1020, 768, 1185, 782] ZOrder -9 ShowName off GotoTag "FFT_OUT_xk_im" } Block { BlockType From Name "From23" SID "197" Position [1040, 303, 1205, 317] ZOrder -9 ShowName off GotoTag "FFT_OUT_xk_index" } Block { BlockType From Name "From25" SID "198" Position [505, 763, 670, 777] ZOrder -9 ShowName off GotoTag "FFT_status_tdata_ovflo" } Block { BlockType From Name "From27" SID "199" Position [505, 788, 670, 802] ZOrder -9 ShowName off GotoTag "FFT_OUT_data_tvalid" } Block { BlockType From Name "From28" SID "200" Position [505, 738, 670, 752] ZOrder -9 ShowName off GotoTag "FFT_data_tuser_ovflo" } Block { BlockType From Name "From3" SID "201" Position [140, 95, 280, 115] ShowName off CloseFcn "tagdialog Close" GotoTag "regTx_FFT_SCALING" TagVisibility "global" } Block { BlockType From Name "From4" SID "202" Position [1040, 108, 1205, 122] ZOrder -9 ShowName off GotoTag "FFT_IN_data_tready" } Block { BlockType From Name "From5" SID "203" Position [1040, 153, 1205, 167] ZOrder -9 ShowName off GotoTag "FFT_OUT_xk_re" } Block { BlockType From Name "From6" SID "204" Position [1040, 168, 1205, 182] ZOrder -9 ShowName off GotoTag "FFT_OUT_xk_im" } Block { BlockType From Name "From7" SID "205" Position [1040, 213, 1205, 227] ZOrder -9 ShowName off GotoTag "FFT_OUT_data_tvalid" } Block { BlockType From Name "From8" SID "206" Position [1040, 268, 1205, 282] ZOrder -9 ShowName off GotoTag "FFT_OUT_data_tlast" } Block { BlockType From Name "From9" SID "207" Position [1020, 593, 1185, 607] ZOrder -9 ShowName off GotoTag "FFT_IN_data_tready" } Block { BlockType Reference Name "Gateway Out" SID "208" Ports [1, 1] Position [1235, 619, 1270, 631] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IN tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out1" SID "209" Ports [1, 1] Position [1235, 594, 1270, 606] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IN tready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "210" Ports [1, 1] Position [1235, 694, 1270, 706] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "211" Ports [1, 1] Position [1235, 719, 1270, 731] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT xkindex" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "212" Ports [1, 1] Position [715, 639, 750, 651] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IN tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out13" SID "213" Ports [1, 1] Position [715, 614, 750, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IN tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out14" SID "214" Ports [1, 1] Position [715, 764, 750, 776] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tdata_ovflo" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out15" SID "215" Ports [1, 1] Position [715, 789, 750, 801] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out16" SID "3560" Ports [1, 1] Position [1235, 769, 1270, 781] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "216" Ports [1, 1] Position [715, 739, 750, 751] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tuser_ovflo" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "217" Ports [1, 1] Position [1235, 669, 1270, 681] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "218" Ports [1, 1] Position [715, 664, 750, 676] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "frame started" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "219" Ports [1, 1] Position [715, 689, 750, 701] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast_unexpected" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "220" Ports [1, 1] Position [715, 714, 750, 726] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast_missing" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "221" Ports [1, 1] Position [1235, 644, 1270, 656] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IN tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "222" Ports [1, 1] Position [350, 34, 385, 46] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out9" SID "3557" Ports [1, 1] Position [1235, 744, 1270, 756] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "OUT I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "223" Position [790, 113, 960, 127] ZOrder -10 ShowName off GotoTag "FFT_IN_data_tready" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "224" Position [790, 93, 960, 107] ZOrder -10 ShowName off GotoTag "FFT_config_tready" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "225" Position [790, 293, 960, 307] ZOrder -10 ShowName off GotoTag "FFT_event_frame_started" TagVisibility "local" } Block { BlockType Goto Name "Goto11" SID "226" Position [790, 313, 960, 327] ZOrder -10 ShowName off GotoTag "FFT_event_tlast_unexpected" TagVisibility "local" } Block { BlockType Goto Name "Goto12" SID "227" Position [790, 333, 960, 347] ZOrder -10 ShowName off GotoTag "FFT_event_tlast_missnig" TagVisibility "local" } Block { BlockType Goto Name "Goto13" SID "228" Position [790, 353, 960, 367] ZOrder -10 ShowName off GotoTag "FFT_event_fft_overflow" TagVisibility "local" } Block { BlockType Goto Name "Goto14" SID "229" Position [260, 284, 370, 296] ZOrder -10 ShowName off GotoTag "FFT_IN_tvalid" TagVisibility "local" } Block { BlockType Goto Name "Goto15" SID "230" Position [260, 324, 370, 336] ZOrder -10 ShowName off GotoTag "FFT_IN_tlast" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "231" Position [790, 133, 960, 147] ZOrder -10 ShowName off GotoTag "FFT_status_tvalid" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "232" Position [790, 153, 960, 167] ZOrder -10 ShowName off GotoTag "FFT_status_tdata_ovflo" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "233" Position [790, 173, 960, 187] ZOrder -10 ShowName off GotoTag "FFT_OUT_xk_im" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "234" Position [790, 193, 960, 207] ZOrder -10 ShowName off GotoTag "FFT_OUT_xk_re" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "235" Position [790, 213, 960, 227] ZOrder -10 ShowName off GotoTag "FFT_data_tuser_ovflo" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "236" Position [790, 233, 960, 247] ZOrder -10 ShowName off GotoTag "FFT_OUT_xk_index" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "237" Position [790, 253, 960, 267] ZOrder -10 ShowName off GotoTag "FFT_OUT_data_tvalid" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "238" Position [790, 273, 960, 287] ZOrder -10 ShowName off GotoTag "FFT_OUT_data_tlast" TagVisibility "local" } Block { BlockType Reference Name "Inverter" SID "239" Ports [1, 1] Position [285, 413, 315, 427] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');d" "isp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "3435" Ports [1, 1] Position [415, 405, 445, 435] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "240" Ports [1, 1] Position [1335, 369, 1385, 401] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal be" "tween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs n" "othing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is fo" "rced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an o" "utput of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "50,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "data_in_tready" SID "241" Position [1260, 108, 1290, 122] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "I out" SID "242" Position [1260, 153, 1290, 167] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Q out" SID "243" Position [1260, 168, 1290, 182] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "data_xk_index" SID "244" Position [1260, 303, 1290, 317] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "data_out_tvalid" SID "245" Position [1260, 213, 1290, 227] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "data_out_tlast" SID "246" Position [1260, 268, 1290, 282] Port "6" IconDisplay "Port number" } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Display4" DstPort 1 } Line { Labels [1, 0] SrcBlock "From3" SrcPort 1 Points [40, 0] Branch { Points [0, -65] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "Fast Fourier Transform 8.0 " DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "IQ In Valid" SrcPort 1 Points [25, 0] Branch { Points [0, 10] DstBlock "Goto14" DstPort 1 } Branch { DstBlock "Fast Fourier Transform 8.0 " DstPort 6 } } Line { SrcBlock "IQ tlast" SrcPort 1 Points [25, 0] Branch { Points [0, 15] DstBlock "Goto15" DstPort 1 } Branch { DstBlock "Fast Fourier Transform 8.0 " DstPort 7 } } Line { Name "IN tlast" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "FFT Ctrl" DstPort 3 } Line { Name "tlast_missing" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FFT Status" DstPort 5 } Line { Name "tlast_unexpected" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "FFT Status" DstPort 4 } Line { Name "frame started" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FFT Status" DstPort 3 } Line { Name "IN tready" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FFT Ctrl" DstPort 1 } Line { Name "IN tvalid" Labels [0, 0] SrcBlock "Gateway Out" SrcPort 1 DstBlock "FFT Ctrl" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 DstBlock "data_in_tready" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "I out" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Q out" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "data_out_tvalid" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "data_out_tlast" DstPort 1 } Line { Name "OUT tvalid" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FFT Ctrl" DstPort 4 } Line { Name "OUT tlast" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "FFT Ctrl" DstPort 5 } Line { Name "OUT xkindex" Labels [0, 0] SrcBlock "Gateway Out11" SrcPort 1 DstBlock "FFT Ctrl" DstPort 6 } Line { Name "IN tlast" Labels [0, 0] SrcBlock "Gateway Out12" SrcPort 1 DstBlock "FFT Status" DstPort 2 } Line { Name "IN tvalid" Labels [0, 0] SrcBlock "Gateway Out13" SrcPort 1 DstBlock "FFT Status" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Gateway Out1" DstPort 1 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Gateway Out" DstPort 1 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Gateway Out7" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Gateway Out3" DstPort 1 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Gateway Out10" DstPort 1 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Gateway Out11" DstPort 1 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Gateway Out13" DstPort 1 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Gateway Out12" DstPort 1 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Gateway Out4" DstPort 1 } Line { SrcBlock "From18" SrcPort 1 DstBlock "Gateway Out5" DstPort 1 } Line { SrcBlock "From19" SrcPort 1 DstBlock "Gateway Out6" DstPort 1 } Line { SrcBlock "From23" SrcPort 1 Points [15, 0] Branch { DstBlock "data_xk_index" DstPort 1 } Branch { DstBlock "Convert" DstPort 1 } } Line { Name "OUT tvalid" Labels [0, 0] SrcBlock "Gateway Out15" SrcPort 1 DstBlock "FFT Status" DstPort 8 } Line { SrcBlock "From27" SrcPort 1 DstBlock "Gateway Out15" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 3 } Line { SrcBlock "Q " SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 4 } Line { SrcBlock "I " SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 5 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 8 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 9 } Line { SrcBlock "From28" SrcPort 1 DstBlock "Gateway Out2" DstPort 1 } Line { Name "tuser_ovflo" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FFT Status" DstPort 6 } Line { Name "tdata_ovflo" Labels [0, 0] SrcBlock "Gateway Out14" SrcPort 1 DstBlock "FFT Status" DstPort 7 } Line { SrcBlock "From25" SrcPort 1 DstBlock "Gateway Out14" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 2 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 3 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 4 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 5 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 6 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 7 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 8 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 9 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 10 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 11 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 12 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 13 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "Fast Fourier Transform 8.0 " SrcPort 14 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 Points [50, 0] } Line { SrcBlock "Register" SrcPort 1 DstBlock "Fast Fourier Transform 8.0 " DstPort 10 } Line { Name "OUT I" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "FFT Ctrl" DstPort 7 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Gateway Out9" DstPort 1 } Line { SrcBlock "From20" SrcPort 1 DstBlock "Gateway Out16" DstPort 1 } Line { Name "OUT Q" Labels [0, 0] SrcBlock "Gateway Out16" SrcPort 1 DstBlock "FFT Ctrl" DstPort 8 } Annotation { Name "Use this signal as I or Q output\nto debug indexing downstream" Position [1515, 387] } } } Block { BlockType SubSystem Name "FIFO" SID "4" Ports [6, 6] Position [320, 292, 450, 478] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FIFO" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "FFT tready" SID "5" Position [355, 328, 385, 342] IconDisplay "Port number" } Block { BlockType Inport Name "Sym Cfg" SID "6" Position [220, 448, 250, 462] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "7" Position [105, 373, 135, 387] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "8" Position [105, 398, 135, 412] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "IQ tvalid" SID "9" Position [355, 358, 385, 372] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "IQ tlast " SID "10" Position [325, 418, 355, 432] Port "6" IconDisplay "Port number" } Block { BlockType Reference Name "AXI FIFO" SID "11" Ports [6, 6] Position [450, 283, 650, 477] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AXI FIFO" SourceType "Xilinx AXI FIFO Block Block" input_depth_axis "128" actual_fifo_depth_label "130" enable_tdata on enable_tdest off enable_tstrb off enable_tready on enable_tid off enable_tuser on enable_tkeep off enable_tlast on has_aresetn on enable_data_counts_axis on fifo_implementation_type_axis "Common Clock Block RAM" trim_axipin_name on programmable_full_type_axis "Full" full_threshold_assert_value_axis "0" programmable_empty_type_axis "Empty" empty_threshold_assert_value_axis "1022" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "axi_fifo" sg_icon_stat "200,194,6,6,white,blue,0,1f5dad1a,right,,[1 2 3 3 3 3 ],[2 2 2 2 3 1 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 4 4 ],[183 161 161 183 ],[7.7000" "00e-001 8.200000e-001 9.100000e-001 ]);\npatch([0 0 4 4 ],[153 131 131 153 ],[5.466667e-001 5.800000e-001 6.400" "000e-001 ]);\npatch([0 0 4 4 ],[123 11 11 123 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]);\npatch([196 196 " "200 200 ],[183 71 71 183 ],[5.466667e-001 5.800000e-001 6.400000e-001 ]);\npatch([196 196 200 200 ],[63 41 41 6" "3 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]);\npatch([196 196 200 200 ],[33 11 11 33 ],[7.700000e-001 8.20" "0000e-001 9.100000e-001 ]);\npatch([4 195 195 4 4 ],[0 0 194 194 0 ],[7.700000e-001 8.200000e-001 9.100000e-001" " ]);\nplot([4 195 195 4 4 ],[0 0 194 194 0 ]);\n\n\npatch([39.925 78.94 105.94 132.94 159.94 105.94 66.925 39.9" "25 ],[126.97 126.97 153.97 126.97 153.97 153.97 153.97 126.97 ],[1 1 1 ]);\npatch([66.925 105.94 78.94 39.925 6" "6.925 ],[99.97 99.97 126.97 126.97 99.97 ],[0.931 0.946 0.973 ]);\npatch([39.925 78.94 105.94 66.925 39.925 ],[" "72.97 72.97 99.97 99.97 72.97 ],[1 1 1 ]);\npatch([66.925 159.94 132.94 105.94 78.94 39.925 66.925 ],[45.97 45." "97 72.97 45.97 72.97 72.97 45.97 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('" "','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' aresetn ');\ncolor('black');port_label(" "'input',2,' tready ');\ncolor('black');port_label('input',3,' tvalid ');\ncolor('black');port_label('input'" ",4,' tdata ');\ncolor('black');port_label('input',5,' tlast ');\ncolor('black');port_label('input',6,' tus" "er ');\ncolor('black');port_label('output',1,' tvalid ');\ncolor('black');port_label('output',2,' tdata ')" ";\ncolor('black');port_label('output',3,' tlast ');\ncolor('black');port_label('output',4,' tuser ');\ncolo" "r('black');port_label('output',5,' tready ');\ncolor('black');port_label('output',6,' data_count ');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "12" Ports [1, 1] Position [170, 372, 200, 388] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "13" Ports [1, 1] Position [170, 397, 200, 413] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "FFT IN FIFO" SID "14" Ports [7] Position [1365, 188, 1400, 282] ZOrder -3 Floating off Location [1, 45, 1833, 1199] Open off NumInputPorts "7" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "30000" YMin "0~0~0~-0.1~0~-0.1~-0.1" YMax "300~300~1~1.1~4000~1.1~1.1" SaveName "ScopeData20" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Scope Name "FIFO Ctrl" SID "15" Ports [8] Position [1380, 613, 1415, 742] ZOrder -3 Floating off Location [1255, 123, 2246, 1467] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "12000" YMin "0~0~0~0~0~0~0~-5" YMax "1~1~5000~1~1~5000~1~5" SaveName "ScopeData21" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType From Name "From1" SID "16" Position [95, 294, 190, 316] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "17" Ports [1, 1] Position [1205, 199, 1240, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FIFO out valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "18" Ports [1, 1] Position [1220, 664, 1255, 676] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "VALID out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "19" Ports [1, 1] Position [1220, 679, 1255, 691] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TLAST out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "20" Ports [1, 1] Position [1220, 694, 1255, 706] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TUSER out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out13" SID "21" Ports [1, 1] Position [1220, 709, 1255, 721] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out14" SID "22" Ports [1, 1] Position [1220, 619, 1255, 631] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "VALID In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out15" SID "3449" Ports [1, 1] Position [1220, 724, 1255, 736] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FIFO Occ" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "23" Ports [1, 1] Position [1205, 214, 1240, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Q out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "24" Ports [1, 1] Position [1205, 229, 1240, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "25" Ports [1, 1] Position [1205, 244, 1240, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FIFO ready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "26" Ports [1, 1] Position [1205, 259, 1240, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "valid in" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "27" Ports [1, 1] Position [1205, 274, 1240, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast in" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "28" Ports [1, 1] Position [1220, 634, 1255, 646] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TLAST In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "29" Ports [1, 1] Position [1205, 184, 1240, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FFT ready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "30" Ports [1, 1] Position [1220, 649, 1255, 661] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TUSER In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "31" Position [810, 445, 955, 465] ZOrder -10 ShowName off GotoTag "IFFT_FIFO_OCC" TagVisibility "global" } Block { BlockType SubSystem Name "I/Q Concat" SID "32" Ports [2, 1] Position [250, 367, 290, 418] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Concat" Location [522, 447, 879, 615] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "33" Position [105, 123, 135, 137] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "34" Position [105, 158, 135, 172] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "35" Ports [2, 1] Position [315, 110, 350, 185] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,75,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 75 75 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 75 75 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[42.55 42.55 47." "55 42.55 47.55 47.55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 42.55 37." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[32.55 32.55 37.55 37.55 32.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 27.55 32.55 32.55 27.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "36" Ports [1, 1] Position [205, 119, 245, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "37" Ports [1, 1] Position [205, 154, 245, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ" SID "38" Position [420, 143, 450, 157] IconDisplay "Port number" } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "IQ" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } } } Block { BlockType SubSystem Name "I/Q Slice" SID "39" Ports [1, 2] Position [785, 315, 835, 350] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Slice" Location [1155, 565, 1558, 696] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "40" Position [190, 123, 220, 137] IconDisplay "Port number" } Block { BlockType Reference Name "Reinterpret2" SID "41" Ports [1, 1] Position [350, 119, 390, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "42" Ports [1, 1] Position [350, 144, 390, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "43" Ports [1, 1] Position [265, 119, 300, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "44" Ports [1, 1] Position [265, 144, 300, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "45" Position [450, 123, 480, 137] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "46" Position [450, 148, 480, 162] Port "2" IconDisplay "Port number" } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 Points [15, 0] Branch { DstBlock "Slice" DstPort 1 } Branch { Points [0, 25] DstBlock "Slice1" DstPort 1 } } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } } } Block { BlockType Reference Name "Inverter" SID "47" Ports [1, 1] Position [220, 297, 255, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "48" Ports [2, 1] Position [1040, 334, 1080, 376] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "2640" Ports [1, 1] Position [305, 292, 330, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " I" SID "49" Position [905, 318, 935, 332] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "50" Position [905, 333, 935, 347] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " IQ tvalid" SID "51" Position [730, 298, 760, 312] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "IQ tlast" SID "52" Position [1155, 348, 1185, 362] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Sym cfg" SID "53" Position [1155, 388, 1185, 402] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "FIFO tready" SID "54" Position [730, 418, 760, 432] Port "6" IconDisplay "Port number" } Line { SrcBlock "FFT tready" SrcPort 1 Points [30, 0] Branch { Points [0, -145] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "AXI FIFO" DstPort 2 } } Line { SrcBlock "IQ tvalid" SrcPort 1 Points [40, 0] Branch { DstBlock "AXI FIFO" DstPort 3 } Branch { Points [0, 150] Branch { Points [550, 0; 0, -250] DstBlock "Gateway Out5" DstPort 1 } Branch { Points [0, 110] DstBlock "Gateway Out14" DstPort 1 } } } Line { SrcBlock "IQ tlast " SrcPort 1 Points [60, 0] Branch { DstBlock "AXI FIFO" DstPort 5 } Branch { Points [0, 95] Branch { Points [575, 0; 0, -240] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, 120] DstBlock "Gateway Out7" DstPort 1 } } } Line { SrcBlock "I" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "I/Q Concat" SrcPort 1 DstBlock "AXI FIFO" DstPort 4 } Line { SrcBlock "From1" SrcPort 1 Points [5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 410] DstBlock "Gateway Out13" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "I/Q Concat" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "I/Q Concat" DstPort 2 } Line { SrcBlock "Sym Cfg" SrcPort 1 Points [145, 0] Branch { DstBlock "AXI FIFO" DstPort 6 } Branch { Points [0, 200] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "AXI FIFO" SrcPort 5 Points [45, 0] Branch { DstBlock "FIFO tready" DstPort 1 } Branch { Points [0, 50; 315, 0; 0, -225] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "AXI FIFO" SrcPort 2 DstBlock "I/Q Slice" DstPort 1 } Line { SrcBlock "AXI FIFO" SrcPort 1 Points [35, 0] Branch { DstBlock " IQ tvalid" DstPort 1 } Branch { Points [0, -30] Branch { Points [0, -70] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [265, 0; 0, 70] DstBlock "Logical2" DstPort 1 } } Branch { Points [0, 365] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "AXI FIFO" SrcPort 3 Points [25, 0] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, 320] DstBlock "Gateway Out11" DstPort 1 } } Line { Name "FFT ready" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "FFT IN FIFO" DstPort 1 } Line { SrcBlock "I/Q Slice" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "I/Q Slice" SrcPort 2 Points [10, 0] Branch { DstBlock " Q" DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out2" DstPort 1 } } Line { Name "FIFO out valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FFT IN FIFO" DstPort 2 } Line { Name "Q out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FFT IN FIFO" DstPort 3 } Line { Name "tlast out" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FFT IN FIFO" DstPort 4 } Line { Name "FIFO ready" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FFT IN FIFO" DstPort 5 } Line { Name "valid in" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "FFT IN FIFO" DstPort 6 } Line { Name "tlast in" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FFT IN FIFO" DstPort 7 } Line { SrcBlock "Logical2" SrcPort 1 Points [40, 0] Branch { DstBlock "IQ tlast" DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AXI FIFO" SrcPort 4 Points [20, 0] Branch { Points [0, 305] DstBlock "Gateway Out12" DstPort 1 } Branch { DstBlock "Sym cfg" DstPort 1 } } Line { Name "VALID In" Labels [0, 0] SrcBlock "Gateway Out14" SrcPort 1 DstBlock "FIFO Ctrl" DstPort 1 } Line { Name "TLAST In" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "FIFO Ctrl" DstPort 2 } Line { Name "TUSER In" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "FIFO Ctrl" DstPort 3 } Line { Name "VALID out" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "FIFO Ctrl" DstPort 4 } Line { Name "TLAST out" Labels [0, 0] SrcBlock "Gateway Out11" SrcPort 1 DstBlock "FIFO Ctrl" DstPort 5 } Line { Name "TUSER out" Labels [0, 0] SrcBlock "Gateway Out12" SrcPort 1 DstBlock "FIFO Ctrl" DstPort 6 } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out13" SrcPort 1 DstBlock "FIFO Ctrl" DstPort 7 } Line { SrcBlock "AXI FIFO" SrcPort 6 Points [75, 0] Branch { DstBlock "Goto" DstPort 1 } Branch { Points [0, 275] DstBlock "Gateway Out15" DstPort 1 } } Line { SrcBlock "Register" SrcPort 1 DstBlock "AXI FIFO" DstPort 1 } Line { Name "FIFO Occ" Labels [0, 0] SrcBlock "Gateway Out15" SrcPort 1 DstBlock "FIFO Ctrl" DstPort 8 } Annotation { Name "AND not strictly necessary, since FFT\nonly honors tlast when tvalid is asserted.\nExplicit AND he" "re makes scopes\nmuch easier to understand." Position [1031, 501] HorizontalAlignment "left" } Annotation { Name "This FIFO aids in synchronizing sample generation\nand feeding the FFT. It would be possible to de" "sign\nthe sample buffer control logic not to require\nthis FIFO, but then the logic would need tweaking\nif the" " FFT timing or sample processing timing\never change. This FIFO isolates those blocks,\nat the cost of a little" " memory" Position [447, 121] HorizontalAlignment "left" } } } Block { BlockType Outport Name " I" SID "248" Position [970, 328, 1000, 342] IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "249" Position [970, 368, 1000, 382] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " IQ Valid" SID "250" Position [970, 408, 1000, 422] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "FIFO tready" SID "2324" Position [545, 453, 575, 467] ZOrder -23 Port "4" IconDisplay "Port number" } Line { SrcBlock "FFT Core" SrcPort 2 DstBlock "Buffer and Cyclic Prefix" DstPort 1 } Line { SrcBlock "FFT Core" SrcPort 3 DstBlock "Buffer and Cyclic Prefix" DstPort 2 } Line { SrcBlock "FFT Core" SrcPort 4 DstBlock "Buffer and Cyclic Prefix" DstPort 3 } Line { SrcBlock "FFT Core" SrcPort 5 DstBlock "Buffer and Cyclic Prefix" DstPort 4 } Line { SrcBlock "FFT Core" SrcPort 6 DstBlock "Buffer and Cyclic Prefix" DstPort 5 } Line { SrcBlock "FFT Core" SrcPort 1 Points [30, 0; 0, -20; -455, 0] DstBlock "FIFO" DstPort 1 } Line { SrcBlock "FIFO" SrcPort 1 DstBlock "FFT Core" DstPort 1 } Line { SrcBlock "Buffer and Cyclic Prefix" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Buffer and Cyclic Prefix" SrcPort 2 DstBlock " Q" DstPort 1 } Line { SrcBlock "FIFO" SrcPort 3 DstBlock "FFT Core" DstPort 3 } Line { SrcBlock "Buffer and Cyclic Prefix" SrcPort 3 DstBlock " IQ Valid" DstPort 1 } Line { SrcBlock "FIFO" SrcPort 4 DstBlock "FFT Core" DstPort 4 } Line { SrcBlock "FIFO" SrcPort 5 Points [340, 0] DstBlock "Buffer and Cyclic Prefix" DstPort 6 } Line { SrcBlock "Sym Cfg" SrcPort 1 DstBlock "FIFO" DstPort 2 } Line { SrcBlock "I" SrcPort 1 DstBlock "FIFO" DstPort 3 } Line { SrcBlock "Q" SrcPort 1 DstBlock "FIFO" DstPort 4 } Line { SrcBlock "IQ Valid" SrcPort 1 DstBlock "FIFO" DstPort 5 } Line { SrcBlock "IQ tlast" SrcPort 1 DstBlock "FIFO" DstPort 6 } Line { SrcBlock "FIFO" SrcPort 2 DstBlock "FFT Core" DstPort 2 } Line { SrcBlock "FIFO" SrcPort 6 DstBlock "FIFO tready" DstPort 1 } } } Block { BlockType SubSystem Name "Mux" SID "251" Ports [4, 5] Position [645, 123, 765, 247] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mux" Location [1234, 258, 1467, 439] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Preamble Sym Cfg" SID "252" Position [165, 638, 195, 652] ZOrder -1 NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Preamble IQ" SID "253" Position [100, 293, 130, 307] ZOrder -1 Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "PSDU Sym Cfg" SID "254" Position [165, 658, 195, 672] ZOrder -1 Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "PSDU IQ" SID "255" Position [100, 393, 130, 407] ZOrder -1 Port "4" IconDisplay "Port number" } Block { BlockType BusSelector Name "Bus Selector" SID "256" Ports [1, 4] Position [190, 262, 195, 338] ZOrder -3 ShowName off OutputSignals "I,Q,IQ tvalid,IQ tlast" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType BusSelector Name "Bus Selector1" SID "257" Ports [1, 4] Position [190, 362, 195, 438] ZOrder -3 ShowName off OutputSignals "I,Q,IQ tvalid,IQ tlast" Port { PortNumber 1 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Mux1" SID "258" Ports [3, 1] Position [350, 318, 370, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.5" "5 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32.22 " "34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ],[1 " "1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "259" Ports [3, 1] Position [350, 398, 370, 462] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.5" "5 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32.22 " "34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ],[1 " "1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "260" Ports [3, 1] Position [350, 478, 370, 542] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.5" "5 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32.22 " "34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ],[1 " "1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "261" Ports [3, 1] Position [350, 613, 370, 677] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.5" "5 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32.22 " "34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ],[1 " "1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux6" SID "262" Ports [3, 1] Position [350, 238, 370, 302] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.5" "5 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32.22 " "34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ],[1 " "1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sym Cfg" SID "263" Position [440, 638, 470, 652] IconDisplay "Port number" } Block { BlockType Outport Name " I" SID "264" Position [440, 263, 470, 277] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "265" Position [440, 343, 470, 357] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " IQ tvalid" SID "266" Position [440, 423, 470, 437] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "IQ tlast" SID "267" Position [440, 503, 470, 517] Port "5" IconDisplay "Port number" } Line { SrcBlock "Mux6" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock " Q" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock " IQ tvalid" DstPort 1 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "IQ tlast" DstPort 1 } Line { SrcBlock "Preamble IQ" SrcPort 1 DstBlock "Bus Selector" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus Selector" SrcPort 1 DstBlock "Mux6" DstPort 2 } Line { Name "" Labels [0, 0] SrcBlock "Bus Selector" SrcPort 2 Points [65, 0; 0, 60] DstBlock "Mux1" DstPort 2 } Line { Name "" Labels [0, 0] SrcBlock "Bus Selector" SrcPort 3 Points [35, 0; 0, 120] DstBlock "Mux2" DstPort 2 } Line { Name "" Labels [0, 0] SrcBlock "Bus Selector" SrcPort 4 Points [20, 0; 0, 180] DstBlock "Mux3" DstPort 2 } Line { SrcBlock "PSDU IQ" SrcPort 1 DstBlock "Bus Selector1" DstPort 1 } Line { Name "" Labels [0, 0] SrcBlock "Bus Selector1" SrcPort 4 Points [10, 0; 0, 100] DstBlock "Mux3" DstPort 3 } Line { Name "" Labels [0, 0] SrcBlock "Bus Selector1" SrcPort 1 Points [95, 0; 0, -80] DstBlock "Mux6" DstPort 3 } Line { Name "" Labels [0, 0] SrcBlock "Bus Selector1" SrcPort 2 Points [135, 0] DstBlock "Mux1" DstPort 3 } Line { Name "" Labels [0, 0] SrcBlock "Bus Selector1" SrcPort 3 Points [115, 0] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, -80] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, -80] DstBlock "Mux6" DstPort 1 } } Branch { Points [0, 40] Branch { DstBlock "Mux2" DstPort 3 } Branch { Points [0, 40] Branch { DstBlock "Mux3" DstPort 1 } Branch { Points [0, 135] DstBlock "Mux4" DstPort 1 } } } } Line { SrcBlock "PSDU Sym Cfg" SrcPort 1 DstBlock "Mux4" DstPort 3 } Line { SrcBlock "Preamble Sym Cfg" SrcPort 1 DstBlock "Mux4" DstPort 2 } Line { SrcBlock "Mux4" SrcPort 1 DstBlock "Sym Cfg" DstPort 1 } } } Block { BlockType SubSystem Name "OFDM Symbol Ctrl" SID "268" Ports [3, 2] Position [250, 184, 355, 246] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "OFDM Symbol Ctrl" Location [12, 217, 1786, 1329] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "83" Block { BlockType Inport Name "Start Tx" SID "269" Position [475, 393, 505, 407] IconDisplay "Port number" } Block { BlockType Inport Name "Sym Done" SID "2173" Position [475, 468, 505, 482] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Data Done" SID "2360" Position [480, 773, 510, 787] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "2296" Ports [0, 1] Position [400, 534, 430, 556] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "180" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,92ae5dd2,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14.33" " 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\n" "patch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outp" "ut',1,'180');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "3556" Ports [0, 1] Position [685, 429, 715, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14.33" " 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\n" "patch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outp" "ut',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "2193" Ports [0, 1] Position [640, 429, 670, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "20" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,a4afb800,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14.33" " 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\n" "patch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('outp" "ut',1,'20');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "2182" Position [1480, 249, 1620, 261] ZOrder -9 ShowName off GotoTag "OUTPUT_FIFO_OCC" TagVisibility "global" } Block { BlockType From Name "From1" SID "2288" Position [240, 514, 395, 536] ZOrder -9 ShowName off GotoTag "OUTPUT_FIFO_OCC" TagVisibility "global" } Block { BlockType From Name "From3" SID "2367" Position [345, 842, 430, 858] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "2184" Ports [1, 1] Position [1660, 249, 1695, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "DAC FIFO Occ" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "2179" Ports [1, 1] Position [1660, 219, 1695, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Sym Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "2297" Ports [1, 1] Position [1660, 189, 1695, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Tx Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "2298" Ports [1, 1] Position [1660, 204, 1695, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Data Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "2310" Ports [1, 1] Position [1660, 279, 1695, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Sym Cfg" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "2180" Ports [1, 1] Position [1660, 234, 1695, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Sym Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "2311" Ports [1, 1] Position [1660, 264, 1695, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Sym Index" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter1" SID "2377" Ports [1, 1] Position [880, 783, 910, 797] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([12.55 19" ".44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "2708" Ports [1, 1] Position [825, 538, 855, 552] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([12.55 19" ".44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2314" Ports [2, 1] Position [890, 561, 930, 619] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "2286" Ports [4, 1] Position [995, 369, 1030, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,227,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 227 227 0 ],[0.77 0.82 0." "91 ]);\nplot([0 35 35 0 0 ],[0 0 227 227 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[118.55 118.55" " 123.55 118.55 123.55 123.55 123.55 118.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[113.55 113.55 118." "55 118.55 113.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[108.55 108.55 113.55 113.55 108.5" "5 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[103.55 103.55 108.55 103.55 108.55 108.55 103.55 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "2287" Ports [2, 1] Position [890, 408, 925, 497] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,89,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 89 89 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 89 89 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[49.55 49.55 54.55" " 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[44.55 44.55 49.55 49.55 44.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[39.55 39.55 44.55 44.55 39.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[34.55 34.55 39.55 34.55 39.55 39.55 34.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "2376" Ports [3, 1] Position [1410, 485, 1445, 575] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,90,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 90 90 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[50.55 50.55 55.55" " 50.55 55.55 55.55 55.55 50.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[45.55 45.55 50.55 50.55 45.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[40.55 40.55 45.55 45.55 40.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[35.55 35.55 40.55 35.55 40.55 40.55 35.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "2707" Ports [2, 1] Position [890, 501, 930, 559] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,58,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "314" Ports [1, 1] Position [540, 393, 585, 407] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [13, 209, 1798, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "315" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "316" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "317" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "318" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "319" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge2" SID "2316" Ports [1, 1] Position [520, 528, 565, 542] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge2" Location [13, 209, 1798, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "2317" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "2318" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "2319" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2320" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2321" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge3" SID "2361" Ports [1, 1] Position [555, 773, 600, 787] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge3" Location [13, 209, 1798, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "2362" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "2363" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "2364" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2365" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2366" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } } } Block { BlockType Reference Name "Relational1" SID "2195" Ports [2, 1] Position [755, 411, 790, 449] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2372" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "2373" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2374" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2375" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "2630" Ports [2, 1] Position [735, 828, 765, 857] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "2631" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "2632" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "2633" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2634" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "2635" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2636" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2637" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "S-R Latch3" SID "2690" Ports [2, 1] Position [735, 528, 765, 557] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch3" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "2691" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "2692" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "2693" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2694" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "2695" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2696" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2697" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "Slice" SID "2562" Ports [1, 1] Position [1560, 277, 1595, 293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "5" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Sym Config Encode" SID "2174" Ports [1, 1] Position [1295, 445, 1395, 485] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sym Config Encode" Location [993, 231, 1609, 1140] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OFDM Sym Ind" SID "2178" Position [170, 273, 200, 287] ZOrder -1 IconDisplay "Port number" } Block { BlockType Reference Name "2LSB" SID "2593" Ports [1, 1] Position [335, 1117, 375, 1133] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "2597" Ports [2, 1] Position [495, 1115, 535, 1150] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "2" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "40,35,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "270" Ports [9, 1] Position [1335, 273, 1405, 457] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "9" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "70,184,9,1,white,blue,0,d6469a80,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 184 184 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 70 70 0 0 ],[0 0 184 184 0 ]);\npatch([12.75 27.2 37.2 47.2 57.2 37.2 22.75 12.75 ],[10" "3.1 103.1 113.1 103.1 113.1 113.1 113.1 103.1 ],[1 1 1 ]);\npatch([22.75 37.2 27.2 12.75 22.75 ],[93.1 93.1 103" ".1 103.1 93.1 ],[0.931 0.946 0.973 ]);\npatch([12.75 27.2 37.2 22.75 12.75 ],[83.1 83.1 93.1 93.1 83.1 ],[1 1 1" " ]);\npatch([22.75 57.2 47.2 37.2 27.2 12.75 22.75 ],[73.1 73.1 83.1 73.1 83.1 83.1 73.1 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_lab" "el('input',1,'hi');\n\n\n\n\n\n\n\ncolor('black');port_label('input',9,'lo');\n\ncolor('black');disp('\\fontsiz" "e{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "271" Ports [0, 1] Position [400, 1224, 430, 1246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "16" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,eafdfd08,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'16');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant10" SID "272" Ports [0, 1] Position [405, 724, 435, 746] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant11" SID "273" Ports [0, 1] Position [1235, 314, 1265, 336] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant12" SID "2596" Ports [0, 1] Position [495, 1084, 525, 1106] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant13" SID "2598" Ports [0, 1] Position [410, 1131, 435, 1149] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,18,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "274" Ports [0, 1] Position [400, 1264, 430, 1286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "275" Ports [0, 1] Position [405, 289, 435, 311] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "276" Ports [0, 1] Position [405, 354, 435, 376] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "277" Ports [0, 1] Position [405, 834, 435, 856] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "278" Ports [0, 1] Position [405, 924, 435, 946] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "279" Ports [0, 1] Position [405, 469, 435, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant8" SID "280" Ports [0, 1] Position [405, 504, 435, 526] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant9" SID "281" Ports [0, 1] Position [405, 619, 435, 641] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "2594" Position [1090, 337, 1265, 353] ZOrder -9 ShowName off GotoTag "Pilot_Shift" } Block { BlockType From Name "From10" SID "283" Position [335, 872, 510, 888] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11ag" TagVisibility "global" } Block { BlockType From Name "From11" SID "284" Position [335, 552, 510, 568] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType From Name "From12" SID "285" Position [335, 657, 510, 673] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType From Name "From13" SID "286" Position [335, 762, 510, 778] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType From Name "From14" SID "287" Position [1090, 397, 1265, 413] ZOrder -9 ShowName off GotoTag "Load_HTSTF" } Block { BlockType From Name "From15" SID "288" Position [1090, 377, 1265, 393] ZOrder -9 ShowName off GotoTag "Load_HTLTF" } Block { BlockType From Name "From16" SID "289" Position [1090, 437, 1265, 453] ZOrder -9 ShowName off GotoTag "Load_Base_Rate" } Block { BlockType From Name "From17" SID "290" Position [1090, 417, 1265, 433] ZOrder -9 ShowName off GotoTag "Rotate_BPSK" } Block { BlockType From Name "From18" SID "291" Position [1090, 357, 1265, 373] ZOrder -9 ShowName off GotoTag "Load_Full_Rate" } Block { BlockType From Name "From2" SID "292" Position [1090, 297, 1265, 313] ZOrder -9 ShowName off GotoTag "Cyclic_Prefix_Len" } Block { BlockType From Name "From4" SID "294" Position [1090, 277, 1265, 293] ZOrder -9 ShowName off GotoTag "Cyclic_Shift" } Block { BlockType From Name "From5" SID "295" Position [335, 392, 510, 408] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n_ac" TagVisibility "global" } Block { BlockType From Name "From9" SID "296" Position [335, 962, 510, 978] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType Goto Name "Goto" SID "297" Position [795, 292, 980, 308] ZOrder -10 ShowName off GotoTag "Load_Base_Rate" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "298" Position [800, 861, 980, 879] ZOrder -10 ShowName off GotoTag "Load_Full_Rate" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "299" Position [795, 532, 980, 548] ZOrder -10 ShowName off GotoTag "Rotate_BPSK" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "300" Position [795, 637, 980, 653] ZOrder -10 ShowName off GotoTag "Load_HTSTF" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "301" Position [795, 742, 980, 758] ZOrder -10 ShowName off GotoTag "Load_HTLTF" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "302" Position [800, 1226, 980, 1244] ZOrder -10 ShowName off GotoTag "Cyclic_Prefix_Len" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "303" Position [800, 1266, 980, 1284] ZOrder -10 ShowName off GotoTag "Cyclic_Shift" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "2592" Position [800, 1086, 980, 1104] ZOrder -10 ShowName off GotoTag "Pilot_Shift" TagVisibility "local" } Block { BlockType Reference Name "Logical10" SID "304" Ports [2, 1] Position [685, 598, 720, 687] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,89,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 89 89 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 89 89 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[49.55" " 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[44.55 44.55 49" ".55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[39.55 39.55 44.55 44.55 39.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[34.55 34.55 39.55 34.55 39.55 39.55 34.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical11" SID "305" Ports [2, 1] Position [685, 703, 720, 792] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,89,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 89 89 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 89 89 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[49.55" " 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[44.55 44.55 49" ".55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[39.55 39.55 44.55 44.55 39.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[34.55 34.55 39.55 34.55 39.55 39.55 34.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "307" Ports [2, 1] Position [685, 282, 725, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "308" Ports [2, 1] Position [575, 333, 610, 422] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,89,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 89 89 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 89 89 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[49.55" " 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[44.55 44.55 49" ".55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[39.55 39.55 44.55 44.55 39.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[34.55 34.55 39.55 34.55 39.55 39.55 34.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "309" Ports [2, 1] Position [685, 852, 725, 883] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "310" Ports [2, 1] Position [575, 903, 610, 992] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,89,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 89 89 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 89 89 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[49.55" " 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[44.55 44.55 49" ".55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[39.55 39.55 44.55 44.55 39.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[34.55 34.55 39.55 34.55 39.55 39.55 34.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "311" Ports [2, 1] Position [575, 813, 610, 902] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,89,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 89 89 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 89 89 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[49.55" " 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[44.55 44.55 49" ".55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[39.55 39.55 44.55 44.55 39.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[34.55 34.55 39.55 34.55 39.55 39.55 34.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "312" Ports [2, 1] Position [685, 493, 720, 582] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,89,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 89 89 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 89 89 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[49.55" " 49.55 54.55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[44.55 44.55 49" ".55 49.55 44.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[39.55 39.55 44.55 44.55 39.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[34.55 34.55 39.55 34.55 39.55 39.55 34.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical9" SID "313" Ports [2, 1] Position [575, 453, 605, 522] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,69,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 69 69 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 69 69 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[38.44 " "38.44 42.44 38.44 42.44 42.44 42.44 38.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[34.44 34.44 38.44 3" "8.44 34.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[30.44 30.44 34.44 34.44 30.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[26.44 26.44 30.44 26.44 30.44 30.44 26.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('blac" "k');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "2595" Ports [3, 1] Position [580, 1036, 610, 1154] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,118,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 16.8571 101.143 118" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 16.8571 101.143 118 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 " "15.88 10.1 6.1 ],[63.44 63.44 67.44 63.44 67.44 67.44 67.44 63.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10." "1 ],[59.44 59.44 63.44 63.44 59.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[55.44 55.44 59." "44 59.44 55.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[51.44 51.44 55.44 51.44 55.44 55.4" "4 51.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Relational" SID "320" Ports [2, 1] Position [480, 271, 515, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "321" Ports [2, 1] Position [480, 336, 515, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "322" Ports [2, 1] Position [480, 816, 515, 854] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "323" Ports [2, 1] Position [480, 906, 515, 944] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "324" Ports [2, 1] Position [480, 451, 515, 489] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "325" Ports [2, 1] Position [480, 486, 515, 524] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "326" Ports [2, 1] Position [480, 601, 515, 639] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational7" SID "327" Ports [2, 1] Position [480, 706, 515, 744] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sym Cfg" SID "2176" Position [1510, 358, 1540, 372] IconDisplay "Port number" } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 Points [25, 0; 0, -75] DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical6" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 Points [30, 0] Branch { Points [0, -75] DstBlock "Logical5" DstPort 2 } Branch { Points [0, 60; -100, 0; 0, 45] DstBlock "Mux" DstPort 1 } } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical7" DstPort 1 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Logical7" DstPort 2 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Logical8" DstPort 2 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "Constant8" SrcPort 1 DstBlock "Relational5" DstPort 2 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical9" DstPort 1 } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Logical9" DstPort 2 } Line { SrcBlock "Logical9" SrcPort 1 Points [25, 0; 0, 25] DstBlock "Logical8" DstPort 1 } Line { SrcBlock "Logical8" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Logical10" DstPort 2 } Line { SrcBlock "Constant9" SrcPort 1 DstBlock "Relational6" DstPort 2 } Line { SrcBlock "Relational6" SrcPort 1 DstBlock "Logical10" DstPort 1 } Line { SrcBlock "Logical10" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Logical11" DstPort 2 } Line { SrcBlock "Constant10" SrcPort 1 DstBlock "Relational7" DstPort 2 } Line { SrcBlock "Relational7" SrcPort 1 DstBlock "Logical11" DstPort 1 } Line { SrcBlock "Logical11" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "OFDM Sym Ind" SrcPort 1 Points [80, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 115] Branch { Points [0, 35] Branch { DstBlock "Relational5" DstPort 1 } Branch { Points [0, 115] Branch { DstBlock "Relational6" DstPort 1 } Branch { Points [0, 105] Branch { DstBlock "Relational7" DstPort 1 } Branch { Points [0, 110] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 90] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 210] DstBlock "2LSB" DstPort 1 } } } } } } Branch { DstBlock "Relational4" DstPort 1 } } } } Line { SrcBlock "From18" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Concat" DstPort 8 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Concat" DstPort 9 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Constant11" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Sym Cfg" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "2LSB" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "Constant12" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Constant13" SrcPort 1 DstBlock "AddSub" DstPort 2 } Annotation { Name "Sym Config fields:\n 0: Load Base Rate - base-rate in 48 subcarriers (SIGNAL/HT-SIG fields)\n 1:" " Rotate BPSK - use QBPSK (+/- j) (HT-SIG fields)\n 2: Load HT-STF - no data bits\n 3: Load HT-LTF - no data b" "its\n 4: Load Full Rate - full-rate in 48 (a/g) or 52 (n/ac) subcarriers\n6:5: Pilot shift (Rotate negative pi" "lot 0,1,2,3 places)\n 7: Reserved\n\n12: 8: Cyclic prefix length (samples)\n15:13: Cyclic shift (samples)" Position [873, 155] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } Annotation { Name "OFDM Symbols in 11ac SISO:\n0: L-SIG (BPSK - 48sc)\n1: VHT-SIGA1 (BPSK - 48sc)\n2: VHT-SIGA2 (QBPS" "K - 48sc)\n3: VHT-STF (Partial BSPK - 52sc)\n4: VHT-LFT1 (BPSK - 52sc)\n5: VHT-SIGB (52sc)\n6-N: Data (52sc)" Position [599, 163] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11n SISO:\n0: L-SIG (BPSK - 48sc)\n1: HT-SIG1 (QBPSK - 48sc)\n2: HT-SIG2 (QBPSK - " "48sc)\n3: HT-STF (Partial BSPK - 52sc)\n4: HT-LTF1 (BPSK - 52sc)\n5-N: Data (52sc)" Position [424, 158] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11a/g:\n0: SIG (BPSK - 48sc)\n1-N: Data (48sc)" Position [279, 133] HorizontalAlignment "left" } Annotation { Name "All PHY modes:\n-Pilot tones in subcarriers [-21,-7,7,21]\n-Subcarriers [-7,-21] are x_ind [57,43]" "\n-One pilot per OFDM sybmol is opposite sign of other 3\n\n11a/g:\n-Opposite sign always in subcarrier 21\n\n1" "1n/ac:\n-Syms 0:4: Same as a/g\n-Syms 5:6: No pilot tones in HT-STF, HT-LTF\n-Syms 7:N: Opposite sign pilot rot" "ates across 4 subcarriers sequentially:\n 7: 21\n 8: 7\n 9: -21\n 10: -7\n ...\nLogic uses 2LSB of s" "ym index to select current negative pilot subcarrier" Position [1668, 533] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Sym Counter" SID "2282" Ports [1, 2] Position [1095, 447, 1205, 518] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sym Counter" Location [489, 401, 1094, 602] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Start Sym" SID "2284" Position [205, 218, 235, 232] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "2172" Ports [1, 1] Position [585, 310, 625, 340] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "282" Position [435, 197, 520, 213] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType From Name "From3" SID "293" Position [255, 262, 340, 278] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Logical2" SID "306" Ports [2, 1] Position [485, 216, 520, 254] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolo" "r('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "328" Ports [2, 1] Position [400, 228, 430, 257] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "329" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "330" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "331" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "332" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "333" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "334" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "335" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Reference Name "Sym Counter" SID "336" Ports [2, 1] Position [575, 190, 635, 250] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "47" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SYMS))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsiz" "e{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Sym Ind" SID "2283" Position [745, 213, 775, 227] IconDisplay "Port number" } Block { BlockType Outport Name " Start Sym" SID "2285" Position [745, 318, 775, 332] Port "2" IconDisplay "Port number" } Line { SrcBlock "From1" SrcPort 1 DstBlock "Sym Counter" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Sym Counter" DstPort 2 } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 Points [20, 0; 0, -20] DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Start Sym" SrcPort 1 Points [140, 0] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 10] Branch { DstBlock "S-R Latch1" DstPort 1 } Branch { Points [0, 90] DstBlock "Delay" DstPort 1 } } } Line { SrcBlock "Sym Counter" SrcPort 1 DstBlock "Sym Ind" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Start Sym" DstPort 1 } Annotation { Name "Use SR latch to skip counter increment\non first sym (indexes syms by 0)" Position [466, 169] } } } Block { BlockType SubSystem Name "Sym Samp Counter" SID "2646" Ports [2, 1] Position [890, 633, 995, 682] BlockMirror on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sym Samp Counter" Location [352, 1245, 1458, 1470] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Sym Started" SID "2660" Position [405, 358, 435, 372] IconDisplay "Port number" } Block { BlockType Inport Name "Sym Cfg" SID "2652" Position [405, 143, 435, 157] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "2645" Ports [3, 1] Position [1015, 156, 1075, 214] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en on latency "1" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,3,1,white,blue,0,96ed0f94,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.8" "8 37.88 45.88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.8" "8 37.88 29.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3," "'en');\ncolor('black');port_label('output',1,'\\bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newli" "ne ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType From Name "From3" SID "2661" Position [310, 317, 395, 333] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType From Name "From4" SID "2644" Position [840, 158, 965, 172] ZOrder -9 ShowName off GotoTag "regTx_NUM_SC" TagVisibility "global" } Block { BlockType From Name "From6" SID "2677" Position [655, 427, 790, 443] ZOrder -9 ShowName off GotoTag "TX_IQ_SAMP_CE" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "2680" Ports [1, 1] Position [755, 329, 790, 351] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.3" "3 11.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 " "11.33 8.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "2678" Ports [2, 1] Position [850, 366, 890, 404] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolo" "r('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2687" Ports [2, 1] Position [555, 401, 590, 434] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "2688" Ports [2, 1] Position [855, 316, 890, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "MCode" SID "2643" Ports [1, 8] Position [520, 90, 770, 205] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input po" "rts of the block are input arguments of the function. The output ports of the block are output arguments of the" " function." mfname "sym_config_decode" explicit_period on period "1" inputsTable "{'boundInpExpr'=>[''],'inputs'=>['sym_cfg']}" outputsTable "{'outputs'=>['load_base_rate','rotate_bpsk','load_htstf','load_htltf','load_full_rate','pil" "ot_shift','cyclic_prefix','cyclic_shift'],'suppressOut'=>['off','off','off','off','off','off','off','off']}" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "250,115,1,8,white,blue,0,d3620376,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 250 250 0 0 ],[0 0 115 115 0 ],[0." "77 0.82 0.91 ]);\nplot([0 250 250 0 0 ],[0 0 115 115 0 ]);\npatch([89.4 112.52 128.52 144.52 160.52 128.52 105." "4 89.4 ],[74.76 74.76 90.76 74.76 90.76 90.76 90.76 74.76 ],[1 1 1 ]);\npatch([105.4 128.52 112.52 89.4 105.4 ]" ",[58.76 58.76 74.76 74.76 58.76 ],[0.931 0.946 0.973 ]);\npatch([89.4 112.52 128.52 105.4 89.4 ],[42.76 42.76 5" "8.76 58.76 42.76 ],[1 1 1 ]);\npatch([105.4 160.52 144.52 128.52 112.52 89.4 105.4 ],[26.76 26.76 42.76 26.76 4" "2.76 42.76 26.76 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\ncolor('black');port_label('input',1,'sym_cfg');\ncolor('black');port_label('output',1,'load_bas" "e_rate');\ncolor('black');port_label('output',2,'rotate_bpsk');\ncolor('black');port_label('output',3,'load_hts" "tf');\ncolor('black');port_label('output',4,'load_htltf');\ncolor('black');port_label('output',5,'load_full_rat" "e');\ncolor('black');port_label('output',6,'pilot_shift');\ncolor('black');port_label('output',7,'cyclic_prefix" "');\ncolor('black');port_label('output',8,'cyclic_shift');\ncolor('black');disp('\\bf{sym\\_config\\_decode}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "2671" Ports [1, 1] Position [470, 358, 515, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [13, 209, 1798, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "2672" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "2673" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "2674" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2675" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2676" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge2" SID "2681" Ports [1, 1] Position [1245, 368, 1290, 382] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge2" Location [13, 209, 1798, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "2682" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "2683" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "2684" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2685" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2686" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } } } Block { BlockType Reference Name "Relational2" SID "2662" Ports [2, 1] Position [1145, 347, 1195, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "50,51,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[" "32.77 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 2" "5.77 32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25." "77 18.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.7" "7 11.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');por" "t_label('output',1,'\\bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType SubSystem Name "S-R Latch2" SID "2663" Ports [2, 1] Position [630, 358, 660, 387] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "2664" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "2665" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "2666" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2667" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "2668" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2669" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "2670" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "Samp Counter" SID "2642" Ports [2, 1] Position [945, 308, 1010, 412] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "47" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SYMS))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "65,104,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 104 104 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 65 65 0 0 ],[0 0 104 104 0 ]);\npatch([11.975 24.98 33.98 42.98 51.98 33.98 20.975 11.9" "75 ],[61.99 61.99 70.99 61.99 70.99 70.99 70.99 61.99 ],[1 1 1 ]);\npatch([20.975 33.98 24.98 11.975 20.975 ],[" "52.99 52.99 61.99 61.99 52.99 ],[0.931 0.946 0.973 ]);\npatch([11.975 24.98 33.98 20.975 11.975 ],[43.99 43.99 " "52.99 52.99 43.99 ],[1 1 1 ]);\npatch([20.975 51.98 42.98 33.98 24.98 11.975 20.975 ],[34.99 34.99 43.99 34.99 " "43.99 43.99 34.99 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg" "in icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncol" "or('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Start Next" SID "2656" Position [1400, 368, 1430, 382] IconDisplay "Port number" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Samp Counter" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Sym Cfg" SrcPort 1 DstBlock "MCode" DstPort 1 } Line { SrcBlock "Samp Counter" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "MCode" SrcPort 7 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Sym Started" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "S-R Latch2" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 Points [50, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, -35] DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "From6" SrcPort 1 Points [20, 0; 0, -40] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Posedge2" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 Points [0, 200] DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Posedge2" SrcPort 1 Points [30, 0] Branch { DstBlock "Start Next" DstPort 1 } Branch { Points [0, 90; -785, 0] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Logical1" SrcPort 1 Points [10, 0; 0, -40] DstBlock "S-R Latch2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Samp Counter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 Points [140, 0] Branch { DstBlock "Logical2" DstPort 1 } Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, -60; 280, 0; 0, -60] DstBlock "AddSub" DstPort 3 } } } } Block { BlockType Scope Name "Sym Start Ctrl" SID "2181" Ports [7] Position [1815, 193, 1850, 287] ZOrder -3 Floating off Location [23, 204, 1703, 1208] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "20000" YMin "0~0~0~0~0~0~0" YMax "1~1~1~1~250~7~16" SaveName "ScopeData3" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "Sym Cfg" SID "337" Position [1515, 458, 1545, 472] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " Start Sym" SID "338" Position [1515, 523, 1545, 537] Port "2" IconDisplay "Port number" } Line { SrcBlock "Sym Config Encode" SrcPort 1 Points [70, 0] Branch { DstBlock "Sym Cfg" DstPort 1 } Branch { Points [0, 205] DstBlock "Sym Samp Counter" DstPort 2 } Branch { Points [0, -180] DstBlock "Slice" DstPort 1 } } Line { Labels [0, 0] SrcBlock "Sym Counter" SrcPort 1 Points [15, 0] Branch { Points [0, -105; -500, 0; 0, 60] DstBlock "Relational1" DstPort 1 } Branch { Points [35, 0] Branch { DstBlock "Sym Config Encode" DstPort 1 } Branch { Points [0, -195] DstBlock "Gateway Out6" DstPort 1 } } } Line { Name "Sym Start" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Sym Start Ctrl" DstPort 3 } Line { Name "Sym Done" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Sym Start Ctrl" DstPort 4 } Line { SrcBlock "From" SrcPort 1 DstBlock "Gateway Out1" DstPort 1 } Line { Name "DAC FIFO Occ" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Sym Start Ctrl" DstPort 5 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Start Tx" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Sym Counter" SrcPort 2 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 Points [30, 0] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, -205] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [0, 435] DstBlock "S-R Latch2" DstPort 1 } } Line { SrcBlock "Sym Done" SrcPort 1 Points [340, 0] Branch { Points [0, -235] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Logical3" DstPort 2 } } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Posedge2" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { Name "Tx Start" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Sym Start Ctrl" DstPort 1 } Line { Name "Data Done" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Sym Start Ctrl" DstPort 2 } Line { Name "Sym Cfg" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Sym Start Ctrl" DstPort 7 } Line { Name "Sym Index" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Sym Start Ctrl" DstPort 6 } Line { SrcBlock "S-R Latch3" SrcPort 1 Points [20, 0] Branch { Points [0, 30] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Inverter2" DstPort 1 } } Line { SrcBlock "Posedge3" SrcPort 1 Points [25, 0] Branch { DstBlock "S-R Latch1" DstPort 1 } Branch { Points [0, -570] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Data Done" SrcPort 1 DstBlock "Posedge3" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 Points [15, 0] Branch { DstBlock " Start Sym" DstPort 1 } Branch { Points [0, 115] DstBlock "Sym Samp Counter" DstPort 1 } Branch { Points [0, -310] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "Inverter1" SrcPort 1 Points [355, 0; 0, -260] DstBlock "Logical4" DstPort 2 } Line { SrcBlock "S-R Latch2" SrcPort 1 Points [510, 0; 0, -285] DstBlock "Logical4" DstPort 3 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Sym Counter" DstPort 1 } Line { SrcBlock "Posedge2" SrcPort 1 Points [105, 0] Branch { DstBlock "S-R Latch3" DstPort 1 } Branch { Points [0, -20] DstBlock "Logical5" DstPort 1 } } Line { SrcBlock "Sym Samp Counter" SrcPort 1 Points [-95, 0; 0, -55] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [0, -25] DstBlock "Logical2" DstPort 4 } Line { SrcBlock "From3" SrcPort 1 Points [245, 0] Branch { DstBlock "S-R Latch2" DstPort 2 } Branch { Points [0, -55] Branch { Points [0, -245] DstBlock "S-R Latch3" DstPort 2 } Branch { DstBlock "S-R Latch1" DstPort 2 } } } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Gateway Out4" DstPort 1 } Line { SrcBlock "Logical5" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical2" DstPort 3 } Line { SrcBlock "Inverter2" SrcPort 1 DstBlock "Logical5" DstPort 2 } Annotation { Name "Stop generating symbols after DATA field is complete" Position [1078, 780] } Annotation { Name "Stop generating symbols if TX_RESET asserts early" Position [1080, 833] } Annotation { Name "This block generates two outputs:\nStart Sym: triggers generation of one OFDM symbol from the Tx pipeline" "\nSym Cfg: parameters required to generate the new OFDM symbol\n\nTiming of Start Sym is critical:\nImmediately aft" "er \"Start Tx\" this block triggers computation of 3 OFDM symbols. The resulting\nsamples are stored in the FIFO in" " the \"Outputs\" block. Samples will be read from this FIFO after\nthe preamble. Once the FIFO occupancy drops belo" "w 180 samples (first 3 symbols occupy 240 \nsamples), the next OFDM symbol is started. From this point forward a ne" "w OFDM symbol is\nstarted every N sample periods, where N is the number of samples in the previous OFDM symbol\n(N " "= num_subcarriers + cyclic_prefix_length). This timing ensures the output FIFO always has\nenough samples to sustai" "n a constant stream to the DACs, while adapting to changes in the\nsampling rate and number of samples in each OFDM" " symbol / cyclic prefix.\n\nThe Start Sym signal stops asserting after the final OFDM symbol is computed, indicated" " by the\nDATA field being complete.\n\nThe selection of the 180 sample threshold above is critical. A higher thresh" "old will overflow the FIFO\nwith low MCS and low Tx sample rate. A lower thrshold will underflow the FIFO for high " "MCS and high\nsample rate. This threshold will need tweaking for any big changes in Tx pipeline latency." Position [345, 1021] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "PSDU Syms Gen" SID "339" Ports [3, 3] Position [435, 186, 575, 274] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "PSDU Syms Gen" Location [327, 247, 1142, 406] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Sym Cfg" SID "340" Position [315, 388, 345, 402] IconDisplay "Port number" } Block { BlockType Inport Name "Start Sym" SID "341" Position [315, 438, 345, 452] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "IQ FIFO tready" SID "2150" Position [1060, 483, 1090, 497] Port "3" IconDisplay "Port number" } Block { BlockType BusCreator Name "Bus Creator" SID "342" Ports [4, 1] Position [1460, 399, 1470, 496] ZOrder -2 ShowName off DisplayOption "bar" } Block { BlockType SubSystem Name "Convolutional Encoder" SID "343" Ports [4, 5] Position [805, 370, 940, 450] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Convolutional Encoder" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Sym Cfg" SID "344" Position [180, 688, 210, 702] IconDisplay "Port number" } Block { BlockType Inport Name "Tx Bit" SID "345" Position [180, 408, 210, 422] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Tx Bit tvalid" SID "346" Position [180, 493, 210, 507] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Tx Bit tlast" SID "347" Position [180, 608, 210, 622] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "A XOR" SID "348" Ports [6, 1] Position [895, 239, 940, 301] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "5" en on latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,62,6,1,white,blue,0,020e1222,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 62 62 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 62 62 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[37." "66 37.66 43.66 37.66 43.66 43.66 43.66 37.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[31.66 31.66 3" "7.66 37.66 31.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[25.66 25.66 31.66 31.66 25.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[19.66 19.66 25.66 19.66 25.66 25.66 19.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "\n\ncolor('black');port_label('input',6,'en');\n\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolo" "r('black');disp(' \\nxor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B XOR" SID "349" Ports [6, 1] Position [895, 318, 940, 382] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "5" en on latency "1" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,64,6,1,white,blue,0,020e1222,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 64 64 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 64 64 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[38." "66 38.66 44.66 38.66 44.66 44.66 44.66 38.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[32.66 32.66 3" "8.66 38.66 32.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[26.66 26.66 32.66 32.66 26.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[20.66 20.66 26.66 20.66 26.66 26.66 20.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "\n\ncolor('black');port_label('input',6,'en');\n\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolo" "r('black');disp(' \\nxor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Conv Enc" SID "3567" Ports [8] Position [1360, 68, 1395, 277] ZOrder -3 Floating off Location [-1919, 45, 1, 1199] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "25000" YMin "0~0~0~0~0~-1~-1~-1" YMax "1~1~500~500~1~1~1~1" SaveName "ScopeData15" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Convert" SID "350" Ports [1, 1] Position [235, 465, 260, 485] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.2" "2 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.2" "2 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 " "1 ]);\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port" "_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "351" Ports [1, 1] Position [235, 490, 260, 510] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.2" "2 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.2" "2 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 " "1 ]);\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port" "_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "352" Ports [1, 1] Position [905, 681, 935, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "353" Ports [1, 1] Position [905, 601, 935, 629] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "354" Ports [1, 1] Position [905, 541, 935, 569] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "355" Position [70, 464, 165, 486] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "3566" Ports [1, 1] Position [1225, 79, 1260, 91] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Bit In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "3568" Ports [1, 1] Position [1225, 104, 1260, 116] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Bit In Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3569" Ports [1, 1] Position [1225, 129, 1260, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Enc Bit A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "3570" Ports [1, 1] Position [1225, 154, 1260, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Enc Bit B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "3571" Ports [1, 1] Position [1225, 179, 1260, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Enc Bit Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register" SID "356" Ports [3, 1] Position [330, 406, 375, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "357" Ports [3, 1] Position [415, 406, 460, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "358" Ports [3, 1] Position [505, 406, 550, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "359" Ports [3, 1] Position [595, 406, 640, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "360" Ports [3, 1] Position [695, 406, 740, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "361" Ports [3, 1] Position [785, 406, 830, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Sym Cfg" SID "362" Position [1095, 688, 1125, 702] IconDisplay "Port number" } Block { BlockType Outport Name "Enc Bit A" SID "363" Position [1095, 263, 1125, 277] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Enc Bit B" SID "364" Position [1095, 343, 1125, 357] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Enc Bits tvalid" SID "365" Position [1095, 548, 1125, 562] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Enc Bits tlast" SID "366" Position [1095, 608, 1125, 622] Port "5" IconDisplay "Port number" } Line { SrcBlock "Tx Bit tvalid" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "B XOR" SrcPort 1 Points [70, 0] Branch { DstBlock "Enc Bit B" DstPort 1 } Branch { Points [0, -190] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "A XOR" SrcPort 1 Points [65, 0] Branch { DstBlock "Enc Bit A" DstPort 1 } Branch { Points [0, -135] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Register5" SrcPort 1 Points [15, 0; 0, -65] Branch { DstBlock "B XOR" DstPort 5 } Branch { Points [0, -80] DstBlock "A XOR" DstPort 5 } } Line { SrcBlock "Tx Bit" SrcPort 1 Points [75, 0] Branch { Points [0, -90] Branch { DstBlock "B XOR" DstPort 1 } Branch { Points [0, -80] Branch { DstBlock "A XOR" DstPort 1 } Branch { Points [0, -160] DstBlock "Gateway Out1" DstPort 1 } } } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "Register4" SrcPort 1 Points [10, 0; 0, -15] Branch { Points [0, -140] DstBlock "A XOR" DstPort 4 } Branch { DstBlock "Register5" DstPort 1 } } Line { SrcBlock "Register3" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 Points [10, 0; 0, -15] Branch { Points [0, -60] Branch { DstBlock "B XOR" DstPort 4 } Branch { Points [0, -90] DstBlock "A XOR" DstPort 3 } } Branch { DstBlock "Register3" DstPort 1 } } Line { SrcBlock "Register1" SrcPort 1 Points [0, -15] Branch { Points [0, -70] Branch { DstBlock "B XOR" DstPort 3 } Branch { Points [0, -90] DstBlock "A XOR" DstPort 2 } } Branch { DstBlock "Register2" DstPort 1 } } Line { SrcBlock "Register" SrcPort 1 Points [5, 0; 0, -15] Branch { Points [0, -80] DstBlock "B XOR" DstPort 2 } Branch { DstBlock "Register1" DstPort 1 } } Line { SrcBlock "Convert" SrcPort 1 Points [30, 0] Branch { Points [0, -45] DstBlock "Register" DstPort 2 } Branch { Points [95, 0] Branch { Points [0, -45] DstBlock "Register1" DstPort 2 } Branch { Points [80, 0] Branch { Points [0, -45] DstBlock "Register2" DstPort 2 } Branch { Points [100, 0] Branch { Points [0, -45] DstBlock "Register3" DstPort 2 } Branch { Points [90, 0] Branch { Points [100, 0; 0, -45] DstBlock "Register5" DstPort 2 } Branch { Points [0, -45] DstBlock "Register4" DstPort 2 } } } } } } Line { SrcBlock "Convert2" SrcPort 1 Points [40, 0] Branch { Points [0, -55] Branch { DstBlock "Register" DstPort 3 } Branch { Points [0, -150] Branch { Points [565, 0] Branch { Points [0, 80] DstBlock "B XOR" DstPort 6 } Branch { DstBlock "A XOR" DstPort 6 } } Branch { Points [0, -185] DstBlock "Gateway Out2" DstPort 1 } } } Branch { Points [95, 0] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [80, 0] Branch { Points [0, -55] DstBlock "Register2" DstPort 3 } Branch { Points [100, 0] Branch { DstBlock "Register3" DstPort 3 } Branch { Points [90, 0] Branch { Points [0, -55] DstBlock "Register4" DstPort 3 } Branch { Points [100, 0] Branch { DstBlock "Register5" DstPort 3 } Branch { Points [0, 55] DstBlock "Delay3" DstPort 1 } } } } } } } Line { SrcBlock "Delay3" SrcPort 1 Points [90, 0] Branch { DstBlock "Enc Bits tvalid" DstPort 1 } Branch { Points [0, -370] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Sym Cfg" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock " Sym Cfg" DstPort 1 } Line { SrcBlock "Tx Bit tlast" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Enc Bits tlast" DstPort 1 } Line { Name "Bit In" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Conv Enc" DstPort 1 } Line { Name "Bit In Valid" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Conv Enc" DstPort 2 } Line { Name "Enc Bit B" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Conv Enc" DstPort 4 } Line { Name "Enc Bit A" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Conv Enc" DstPort 3 } Line { Name "Enc Bit Valid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Conv Enc" DstPort 5 } } } Block { BlockType SubSystem Name "Index Gen" SID "367" Ports [2, 5] Position [430, 370, 540, 470] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Index Gen" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Sym Cfg" SID "368" Position [300, 443, 330, 457] IconDisplay "Port number" } Block { BlockType Inport Name "Start Sym" SID "369" Position [390, 308, 420, 322] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "Bit Index Gen" SID "370" Ports [1, 4] Position [1035, 265, 1170, 400] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Bit Index Gen" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Bit Rd En" SID "371" Position [350, 248, 380, 262] IconDisplay "Port number" } Block { BlockType Reference Name "Bit counter" SID "372" Ports [2, 1] Position [470, 210, 530, 270] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "6" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))+3" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Bit in Byte" SID "373" Ports [1, 1] Position [620, 290, 665, 310] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2.02" sg_icon_stat "45,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('ou" "tput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Bytes" SID "374" Ports [1, 1] Position [620, 230, 665, 250] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "ceil(log2(MAX_NUM_BYTES))" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2.02" sg_icon_stat "45,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('ou" "tput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "375" Ports [0, 1] Position [805, 352, 830, 378] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From3" SID "376" Position [300, 217, 385, 233] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Logical5" SID "377" Ports [2, 1] Position [960, 338, 990, 402] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,64,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 64 64 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 64 64 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[36.44 36.44 40.4" "4 36.44 40.44 40.44 40.44 36.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[32.44 32.44 36.44 36.44 32.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[28.44 28.44 32.44 32.44 28.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[24.44 24.44 28.44 24.44 28.44 28.44 24.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "378" Ports [2, 1] Position [875, 336, 910, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Byte Ind" SID "379" Position [1055, 232, 1085, 248] IconDisplay "Port number" } Block { BlockType Outport Name "Byte Ind Valid" SID "380" Position [1055, 362, 1085, 378] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Bit Sel" SID "381" Position [1055, 293, 1085, 307] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Bit Sel Valid" SID "382" Position [1055, 478, 1085, 492] Port "4" IconDisplay "Port number" } Line { SrcBlock "Bit counter" SrcPort 1 Points [45, 0] Branch { DstBlock "Bytes" DstPort 1 } Branch { Points [0, 60] DstBlock "Bit in Byte" DstPort 1 } } Line { SrcBlock "Bit in Byte" SrcPort 1 Points [135, 0] Branch { DstBlock "Bit Sel" DstPort 1 } Branch { Points [0, 45] DstBlock "Relational1" DstPort 1 } } Line { SrcBlock "Bytes" SrcPort 1 DstBlock "Byte Ind" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Byte Ind Valid" DstPort 1 } Line { SrcBlock "Bit Rd En" SrcPort 1 Points [55, 0] Branch { Points [0, 230; 420, 0] Branch { Points [0, -100] DstBlock "Logical5" DstPort 2 } Branch { DstBlock "Bit Sel Valid" DstPort 1 } } Branch { DstBlock "Bit counter" DstPort 2 } } Line { SrcBlock "From3" SrcPort 1 DstBlock "Bit counter" DstPort 1 } } } Block { BlockType SubSystem Name "Bits Per Sym" SID "383" Ports [3, 1] Position [880, 301, 970, 369] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Bits Per Sym" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Start" SID "384" Position [335, 163, 365, 177] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Base Rate" SID "385" Position [280, 198, 310, 212] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Full Rate" SID "386" Position [280, 183, 310, 197] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Constant2" SID "387" Ports [0, 1] Position [825, 434, 855, 456] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "24" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bada18f5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'24');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "388" Ports [2, 1] Position [1000, 150, 1060, 210] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "47" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_DATA_BITS_PER_SYM_PERIOD))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "389" Position [570, 382, 655, 398] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType From Name "From2" SID "390" Position [605, 207, 690, 223] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType From Name "From5" SID "391" Position [570, 368, 765, 382] ShowName off CloseFcn "tagdialog Close" GotoTag "OFDM_TX_DATA_N_DBPS" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "392" Ports [1, 1] Position [820, 261, 845, 279] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "393" Ports [1, 1] Position [945, 156, 970, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "394" Ports [2, 1] Position [735, 207, 775, 238] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "395" Ports [2, 1] Position [390, 182, 430, 213] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "396" Ports [2, 1] Position [475, 155, 510, 215] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 60 60 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[35.55 35.55 40." "55 35.55 40.55 40.55 40.55 35.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[30.55 30.55 35.55 35.55 30." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[25.55 25.55 30.55 30.55 25.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 20.55 25.55 25.55 20.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "397" Ports [2, 1] Position [1010, 87, 1050, 118] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "398" Ports [3, 1] Position [945, 309, 970, 471] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,162,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 23.1429 138.857 162 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 23.1429 138.857 162 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[84.33 84.33 87.33 84.33 87.33 87.33 87.33 84.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[8" "1.33 81.33 84.33 84.33 81.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[78.33 78.33 81.33 81" ".33 78.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[75.33 75.33 78.33 75.33 78.33 78.33 75." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "399" Ports [3, 1] Position [820, 364, 860, 416] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "24" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,52,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 52 52 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 52 52 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[31.55 31.55 36." "55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 31.55 26." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register3" SID "400" Ports [3, 1] Position [820, 309, 860, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,52,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 52 52 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 52 52 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[31.55 31.55 36." "55 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 31.55 26." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bla" "ck');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Relational3" SID "401" Ports [2, 1] Position [1010, 249, 1055, 291] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "406" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "407" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "408" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "409" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Outport Name "Rd En" SID "410" Position [1125, 98, 1155, 112] IconDisplay "Port number" } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [120, 0] Branch { Points [0, -55] DstBlock "Register3" DstPort 2 } Branch { DstBlock "Register2" DstPort 2 } } Line { SrcBlock "Inverter" SrcPort 1 Points [-105, 0; 0, -40] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [10, 0; 0, -25] DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 Points [-90, 0] Branch { Points [0, -175] DstBlock "Logical4" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 Points [105, 0; 0, -110] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 Points [15, 0; 0, 80] DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [20, 0] Branch { Points [0, 220; 250, 0] Branch { Points [0, -55] DstBlock "Register3" DstPort 3 } Branch { DstBlock "Register2" DstPort 3 } } Branch { DstBlock "S-R Latch1" DstPort 1 } } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [70, 0] Branch { Points [0, -30] Branch { Points [0, -55] DstBlock "Logical4" DstPort 2 } Branch { DstBlock "Inverter1" DstPort 1 } } Branch { DstBlock "Counter" DstPort 2 } } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Rd En" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Base Rate" SrcPort 1 Points [30, 0] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, 115] DstBlock "Register3" DstPort 1 } } Line { SrcBlock "Full Rate" SrcPort 1 DstBlock "Logical2" DstPort 1 } Annotation { Name "SIGNAL and HT-SIG sybmols always\ncontain 24 data bits (48 subcarriers, BPSK, 1/2 rate)\nThis mux select" "s the N_DBPS value for the current\nMCS sometime after the SIGNAL (11a) or HT-SIG (11n)\nfields are decoded.\nInit" "ial vlaue of N_DBPS register at mux in 0 must be non-zero!" Position [825, 521] HorizontalAlignment "left" } Annotation { Name "This block asserts the \"Bit Rd En\" output for a number of cycles\nequal to the number of bits that wil" "l be read from the packet\nbuffer. Each OFDM symbol contains either 24 bits (for PHY\npreamble symbols) or DATA_N_" "DBPS bits (set by the packet's MCS)." Position [185, 474] HorizontalAlignment "left" } } } Block { BlockType Reference Name "MCode" SID "2585" Ports [1, 8] Position [460, 390, 710, 505] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input po" "rts of the block are input arguments of the function. The output ports of the block are output arguments of the" " function." mfname "sym_config_decode" explicit_period on period "1" inputsTable "{'boundInpExpr'=>[''],'inputs'=>['sym_cfg']}" outputsTable "{'outputs'=>['load_base_rate','rotate_bpsk','load_htstf','load_htltf','load_full_rate','pil" "ot_shift','cyclic_prefix','cyclic_shift'],'suppressOut'=>['off','off','off','off','off','off','off','off']}" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "250,115,1,8,white,blue,0,d3620376,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 250 250 0 0 ],[0 0 115 115 0 ],[0." "77 0.82 0.91 ]);\nplot([0 250 250 0 0 ],[0 0 115 115 0 ]);\npatch([89.4 112.52 128.52 144.52 160.52 128.52 105." "4 89.4 ],[74.76 74.76 90.76 74.76 90.76 90.76 90.76 74.76 ],[1 1 1 ]);\npatch([105.4 128.52 112.52 89.4 105.4 ]" ",[58.76 58.76 74.76 74.76 58.76 ],[0.931 0.946 0.973 ]);\npatch([89.4 112.52 128.52 105.4 89.4 ],[42.76 42.76 5" "8.76 58.76 42.76 ],[1 1 1 ]);\npatch([105.4 160.52 144.52 128.52 112.52 89.4 105.4 ],[26.76 26.76 42.76 26.76 4" "2.76 42.76 26.76 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\ncolor('black');port_label('input',1,'sym_cfg');\ncolor('black');port_label('output',1,'load_bas" "e_rate');\ncolor('black');port_label('output',2,'rotate_bpsk');\ncolor('black');port_label('output',3,'load_hts" "tf');\ncolor('black');port_label('output',4,'load_htltf');\ncolor('black');port_label('output',5,'load_full_rat" "e');\ncolor('black');port_label('output',6,'pilot_shift');\ncolor('black');port_label('output',7,'cyclic_prefix" "');\ncolor('black');port_label('output',8,'cyclic_shift');\ncolor('black');disp('\\bf{sym\\_config\\_decode}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Sym Cfg" SID "427" Position [1350, 523, 1380, 537] IconDisplay "Port number" } Block { BlockType Outport Name "Byte Ind" SID "428" Position [1350, 272, 1380, 288] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Byte Ind Valid" SID "429" Position [1350, 307, 1380, 323] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Bit Sel" SID "430" Position [1350, 343, 1380, 357] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Bit Sel Valid" SID "431" Position [1350, 378, 1380, 392] Port "5" IconDisplay "Port number" } Line { SrcBlock "MCode" SrcPort 5 Points [75, 0; 0, -100] DstBlock "Bits Per Sym" DstPort 3 } Line { SrcBlock "Sym Cfg" SrcPort 1 Points [40, 0] Branch { Points [0, 80] DstBlock " Sym Cfg" DstPort 1 } Branch { DstBlock "MCode" DstPort 1 } } Line { SrcBlock "Start Sym" SrcPort 1 DstBlock "Bits Per Sym" DstPort 1 } Line { Labels [0, 0] SrcBlock "Bits Per Sym" SrcPort 1 DstBlock "Bit Index Gen" DstPort 1 } Line { SrcBlock "MCode" SrcPort 1 Points [70, 0; 0, -60] DstBlock "Bits Per Sym" DstPort 2 } Line { SrcBlock "Bit Index Gen" SrcPort 1 DstBlock "Byte Ind" DstPort 1 } Line { SrcBlock "Bit Index Gen" SrcPort 3 DstBlock "Bit Sel" DstPort 1 } Line { SrcBlock "Bit Index Gen" SrcPort 4 DstBlock "Bit Sel Valid" DstPort 1 } Line { SrcBlock "Bit Index Gen" SrcPort 2 DstBlock "Byte Ind Valid" DstPort 1 } } } Block { BlockType SubSystem Name "Modulate" SID "432" Ports [4, 6] Position [1190, 352, 1315, 493] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off Port { PortNumber 3 Name "I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 5 Name "IQ tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 6 Name "IQ tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "Modulate" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "97" Block { BlockType Inport Name "Sym Cfg" SID "433" Position [165, 193, 195, 207] IconDisplay "Port number" } Block { BlockType Inport Name "Sc Bits" SID "434" Position [330, 633, 360, 647] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Sym Bits Rdy" SID "435" Position [330, 498, 360, 512] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ FIFO tready" SID "2149" Position [330, 533, 360, 547] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "16QAM Mod" SID "436" Ports [1, 2] Position [710, 750, 750, 785] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "16QAM Mod" Location [2, 74, 2464, 1576] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "b[3:0]" SID "437" Position [300, 538, 330, 552] IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "438" Ports [0, 1] Position [625, 592, 745, 618] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_16QAM(3)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,941d5e43,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'0.87841796875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "439" Ports [0, 1] Position [625, 562, 745, 588] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_16QAM(1)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,f18e0d9c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'-0.87841796875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "440" Ports [0, 1] Position [625, 622, 745, 648] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_16QAM(2)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,014b07ca,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'-0.29296875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "441" Ports [0, 1] Position [625, 652, 745, 678] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_16QAM(4)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,f9ee7cdd,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'0.29296875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "442" Ports [5, 1] Position [815, 525, 845, 685] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,160,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 22.8571 137.143 160 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 22.8571 137.143 160 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1" " 6.1 ],[84.44 84.44 88.44 84.44 88.44 88.44 88.44 84.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[80.44 80" ".44 84.44 84.44 80.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[76.44 76.44 80.44 80.44 76.44 ]" ",[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[72.44 72.44 76.44 72.44 76.44 76.44 72.44 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\ncolor('black');disp(" "'\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "443" Ports [5, 1] Position [815, 710, 845, 870] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,160,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 22.8571 137.143 160 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 22.8571 137.143 160 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1" " 6.1 ],[84.44 84.44 88.44 84.44 88.44 88.44 88.44 84.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[80.44 80" ".44 84.44 84.44 80.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[76.44 76.44 80.44 80.44 76.44 ]" ",[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[72.44 72.44 76.44 72.44 76.44 76.44 72.44 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\ncolor('black');disp(" "'\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[1:0]" SID "444" Ports [1, 1] Position [400, 536, 435, 554] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[3:2]" SID "445" Ports [1, 1] Position [400, 721, 435, 739] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "446" Position [930, 598, 960, 612] IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "447" Position [930, 783, 960, 797] Port "2" IconDisplay "Port number" } Line { SrcBlock "b[1:0]" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "b[3:0]" SrcPort 1 Points [20, 0] Branch { DstBlock "b[1:0]" DstPort 1 } Branch { Points [0, 185] DstBlock "b[3:2]" DstPort 1 } } Line { SrcBlock "Constant2" SrcPort 1 Points [40, 0] Branch { DstBlock "Mux" DstPort 2 } Branch { Points [0, 185] DstBlock "Mux1" DstPort 2 } } Line { SrcBlock "Constant1" SrcPort 1 Points [35, 0] Branch { DstBlock "Mux" DstPort 3 } Branch { Points [0, 185] DstBlock "Mux1" DstPort 3 } } Line { SrcBlock "Constant3" SrcPort 1 Points [30, 0] Branch { DstBlock "Mux" DstPort 4 } Branch { Points [0, 185] DstBlock "Mux1" DstPort 4 } } Line { SrcBlock "Constant4" SrcPort 1 Points [25, 0] Branch { DstBlock "Mux" DstPort 5 } Branch { Points [0, 185] DstBlock "Mux1" DstPort 5 } } Line { SrcBlock "b[3:2]" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Q" DstPort 1 } Annotation { Name "16-QAM Bit Mapping:\n[b0 b1] / [b2 b3]:\n00 = -3\n01 = -1\n11 = +1\n10 = +3\nNorm = 1/sqrt(10)" Position [560, 396] } Annotation { Name "00 -> 00" Position [538, 574] } Annotation { Name "10 -> 01" Position [535, 603] } Annotation { Name "01 -> 10" Position [535, 633] } Annotation { Name "11 -> 11" Position [535, 668] } } } Block { BlockType Reference Name "1LSB" SID "2153" Ports [1, 1] Position [615, 634, 650, 646] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bla" "ck');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "2LSB" SID "2154" Ports [1, 1] Position [615, 704, 650, 716] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bla" "ck');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB" SID "2155" Ports [1, 1] Position [615, 764, 650, 776] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bla" "ck');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "64QAM Mod" SID "448" Ports [1, 2] Position [710, 810, 750, 845] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "64QAM Mod" Location [21, 80, 2158, 1372] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "b[5:0]" SID "449" Position [300, 538, 330, 552] IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "450" Ports [0, 1] Position [495, 592, 615, 618] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_64QAM(5)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,4133ba54,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'0.99951171875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant10" SID "451" Ports [0, 1] Position [495, 682, 615, 708] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_64QAM(2)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,c52825ea,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'-0.71435546875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant11" SID "452" Ports [0, 1] Position [495, 742, 615, 768] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_64QAM(4)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,c6f2d39a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'-0.4287109375');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant12" SID "453" Ports [0, 1] Position [495, 772, 615, 798] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_64QAM(8)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,e7892d26,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'0.4287109375');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "454" Ports [0, 1] Position [495, 562, 615, 588] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_64QAM(1)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,43c97d40,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'-1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "455" Ports [0, 1] Position [495, 622, 615, 648] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_64QAM(3)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,c9e0c8c4,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'-0.14306640625');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "456" Ports [0, 1] Position [495, 652, 615, 678] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_64QAM(7)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,d07ae3d0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'0.14306640625');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant9" SID "457" Ports [0, 1] Position [495, 712, 615, 738] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_64QAM(6)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,18ddcefc,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'0.71435546875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "458" Ports [9, 1] Position [780, 528, 815, 802] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,274,9,1,white,blue,3,9717d9a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 39.1429 234.857 274 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 39.1429 234.857 274 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[142.55 142.55 147.55 142.55 147.55 147.55 147.55 142.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.87" "5 ],[137.55 137.55 142.55 142.55 137.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[132.55 13" "2.55 137.55 137.55 132.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[127.55 127.55 132.55 127" ".55 132.55 132.55 127.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT:" " begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolo" "r('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('inp" "ut',5,'d3');\ncolor('black');port_label('input',6,'d4');\ncolor('black');port_label('input',7,'d5');\ncolor('black" "');port_label('input',8,'d6');\ncolor('black');port_label('input',9,'d7');\n\ncolor('black');disp('\\bf{}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "459" Ports [9, 1] Position [780, 813, 815, 1087] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,274,9,1,white,blue,3,9717d9a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 39.1429 234.857 274 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 39.1429 234.857 274 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[142.55 142.55 147.55 142.55 147.55 147.55 147.55 142.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.87" "5 ],[137.55 137.55 142.55 142.55 137.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[132.55 13" "2.55 137.55 137.55 132.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[127.55 127.55 132.55 127" ".55 132.55 132.55 127.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT:" " begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolo" "r('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('inp" "ut',5,'d3');\ncolor('black');port_label('input',6,'d4');\ncolor('black');port_label('input',7,'d5');\ncolor('black" "');port_label('input',8,'d6');\ncolor('black');port_label('input',9,'d7');\n\ncolor('black');disp('\\bf{}','texmod" "e','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[2:0]" SID "460" Ports [1, 1] Position [400, 536, 435, 554] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[5:3]" SID "461" Ports [1, 1] Position [405, 821, 440, 839] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "462" Position [890, 658, 920, 672] IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "463" Position [890, 943, 920, 957] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant4" SrcPort 1 Points [115, 0] Branch { DstBlock "Mux" DstPort 5 } Branch { Points [0, 285] DstBlock "Mux1" DstPort 5 } } Line { SrcBlock "Constant3" SrcPort 1 Points [120, 0] Branch { DstBlock "Mux" DstPort 4 } Branch { Points [0, 285] DstBlock "Mux1" DstPort 4 } } Line { SrcBlock "Constant1" SrcPort 1 Points [125, 0] Branch { DstBlock "Mux" DstPort 3 } Branch { Points [0, 285] DstBlock "Mux1" DstPort 3 } } Line { SrcBlock "Constant2" SrcPort 1 Points [130, 0] Branch { DstBlock "Mux" DstPort 2 } Branch { Points [0, 285] DstBlock "Mux1" DstPort 2 } } Line { SrcBlock "b[5:0]" SrcPort 1 Points [20, 0] Branch { Points [0, 285] DstBlock "b[5:3]" DstPort 1 } Branch { DstBlock "b[2:0]" DstPort 1 } } Line { SrcBlock "b[2:0]" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant10" SrcPort 1 Points [110, 0] Branch { DstBlock "Mux" DstPort 6 } Branch { Points [0, 285] DstBlock "Mux1" DstPort 6 } } Line { SrcBlock "Constant9" SrcPort 1 Points [105, 0] Branch { DstBlock "Mux" DstPort 7 } Branch { Points [0, 285] DstBlock "Mux1" DstPort 7 } } Line { SrcBlock "Constant11" SrcPort 1 Points [100, 0] Branch { DstBlock "Mux" DstPort 8 } Branch { Points [0, 285] DstBlock "Mux1" DstPort 8 } } Line { SrcBlock "Constant12" SrcPort 1 Points [95, 0] Branch { DstBlock "Mux" DstPort 9 } Branch { Points [0, 285] DstBlock "Mux1" DstPort 9 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b[5:3]" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Q" DstPort 1 } Annotation { Name "64-QAM Bit Mapping:\n[b0 b1 b2] / [b3 b4 b5]:\n000 = -7\n001 = -5\n010 = -1\n011 = -3\n100 = +7\n101 = +" "5\n110 = +1\n111 = +3\n\nNorm = 1/sqrt(42)" Position [540, 381] } Annotation { Name "Endian swap here - mux sels are [b2 b1 b0] and [b5 b4 b3]" Position [537, 517] } Annotation { Name "000" Position [449, 573] } Annotation { Name "001" Position [448, 603] } Annotation { Name "010" Position [447, 637] } Annotation { Name "011" Position [447, 667] } Annotation { Name "100" Position [449, 698] } Annotation { Name "101" Position [448, 728] } Annotation { Name "110" Position [447, 762] } Annotation { Name "111" Position [447, 792] } } } Block { BlockType Reference Name "6LSB" SID "2156" Ports [1, 1] Position [615, 824, 650, 836] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bla" "ck');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "BPSK Mod" SID "464" Ports [2, 2] Position [710, 633, 750, 662] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "BPSK Mod" Location [21, 80, 2158, 1372] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "b[0]" SID "465" Position [135, 38, 165, 52] IconDisplay "Port number" } Block { BlockType Inport Name "rot" SID "2572" Position [135, 143, 165, 157] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant2" SID "466" Ports [0, 1] Position [205, 62, 300, 88] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_BPSK(1)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "95,26,0,1,white,blue,0,f79afc1c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 95 95 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 95 95 0 0 ],[0 0 26 26 0 ]);\npatch([40.325 44.66 47.66 50.66 53.66 47.66 43.325 40.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([43.325 47.66 44.66 40.325 43.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([40.325 44.66 47.66 43.325 40.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([43.325 53.66 50.66 47.66 44.66 40.325 43.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'-0.92578125');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "467" Ports [0, 1] Position [205, 93, 300, 117] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_BPSK(2)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "95,24,0,1,white,blue,0,6adc731b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 95 95 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 95 95 0 0 ],[0 0 24 24 0 ]);\npatch([40.325 44.66 47.66 50.66 53.66 47.66 43.325 40.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([43.325 47.66 44.66 40.325 43.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([40.325 44.66 47.66 43.325 40.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([43.325 53.66 50.66 47.66 44.66 40.325 43.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('output',1,'0.92578125');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "468" Ports [0, 1] Position [260, 198, 300, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "40,24,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 24 24 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "469" Ports [3, 1] Position [340, 27, 370, 123] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,96,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ],[0." "77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6" ".1 ],[52.44 52.44 56.44 52.44 56.44 56.44 56.44 52.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[48.44 48.4" "4 52.44 52.44 48.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[44.44 44.44 48.44 48.44 44.44 ],[" "1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[40.44 40.44 44.44 40.44 44.44 44.44 40.44 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');" "\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "2573" Ports [3, 1] Position [535, 132, 565, 228] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,96,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ],[0." "77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6" ".1 ],[52.44 52.44 56.44 52.44 56.44 56.44 56.44 52.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[48.44 48.4" "4 52.44 52.44 48.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[44.44 44.44 48.44 48.44 44.44 ],[" "1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[40.44 40.44 44.44 40.44 44.44 44.44 40.44 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');" "\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "2574" Ports [3, 1] Position [535, 237, 565, 333] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,96,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ],[0." "77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6" ".1 ],[52.44 52.44 56.44 52.44 56.44 56.44 56.44 52.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[48.44 48.4" "4 52.44 52.44 48.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[44.44 44.44 48.44 48.44 44.44 ],[" "1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[40.44 40.44 44.44 40.44 44.44 44.44 40.44 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');" "\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "470" Position [625, 173, 655, 187] IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "471" Position [625, 278, 655, 292] Port "2" IconDisplay "Port number" } Line { SrcBlock "Mux" SrcPort 1 Points [125, 0; 0, 105] Branch { Points [0, 0] DstBlock "Mux1" DstPort 2 } Branch { Points [0, 135] DstBlock "Mux2" DstPort 3 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "b[0]" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "rot" SrcPort 1 Points [340, 0] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, 105] DstBlock "Mux2" DstPort 1 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 Points [200, 0] Branch { DstBlock "Mux1" DstPort 3 } Branch { Points [0, 75] DstBlock "Mux2" DstPort 2 } } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType Reference Name "Concat" SID "2157" Ports [2, 1] Position [1080, 296, 1105, 334] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 38 38 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[22" ".33 22.33 25.33 22.33 25.33 25.33 25.33 22.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[19.33 19.33 " "22.33 22.33 19.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[16.33 16.33 19.33 19.33 16.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 13.33 16.33 16.33 13.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "3611" Ports [0, 1] Position [875, 927, 905, 943] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "472" Ports [0, 1] Position [1450, 482, 1480, 498] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "473" Ports [0, 1] Position [1455, 307, 1485, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Control & Pilots" SID "474" Ports [4, 5] Position [665, 418, 795, 552] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Control & Pilots" Location [2, 74, 2469, 1576] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Full Rate" SID "2160" Position [230, 413, 260, 427] IconDisplay "Port number" } Block { BlockType Inport Name "Pilot Shift" SID "2588" Position [230, 573, 260, 587] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Sym Bits Rdy" SID "475" Position [230, 343, 260, 357] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ FIFO tready" SID "2147" Position [230, 463, 260, 477] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "Concat1" SID "476" Ports [2, 1] Position [1010, 511, 1040, 549] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 23.44 27.4" "4 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 23.44 19.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi" "');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Data SC Map" SID "477" Ports [2, 2] Position [805, 426, 915, 479] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Data SC Map" Location [-1678, 70, -2, 1030] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Full Rate" SID "2159" Position [185, 473, 215, 487] IconDisplay "Port number" } Block { BlockType Inport Name "sc_ind" SID "478" Position [185, 518, 215, 532] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "11a Subcarrier Map" SID "479" Ports [1, 1] Position [360, 505, 415, 545] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_SC" initVector "sc_data_sym_map_11a" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC))+1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,372,359" block_type "sprom" sg_icon_stat "55,40,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 40 40 0 ]);\npatch([15.875 23.1 28.1 33.1 38.1 28.1 20.875 15.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([20.875 28.1 23.1 15.875 20.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([15.875 23.1 28.1 20.875 15.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([20.875 38.1 33.1 28.1 23.1 15.875 20.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "11n HT20 Subcarrier Map" SID "480" Ports [1, 1] Position [360, 555, 415, 595] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_SC" initVector "sc_data_sym_map_11n" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC))+1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,372,359" block_type "sprom" sg_icon_stat "55,40,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 40 40 0 ]);\npatch([15.875 23.1 28.1 33.1 38.1 28.1 20.875 15.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([20.875 28.1 23.1 15.875 20.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([15.875 23.1 28.1 20.875 15.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([20.875 38.1 33.1 28.1 23.1 15.875 20.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "481" Ports [0, 1] Position [710, 617, 740, 633] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "MAX_NUM_SC" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC))+1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,04961a6a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'64');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "482" Position [395, 432, 530, 448] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "2161" Ports [2, 1] Position [590, 456, 620, 489] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.4" "4 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 " "16.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('an" "d');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "483" Ports [3, 1] Position [695, 448, 720, 602] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,154,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 22 132 154 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 22 132 154 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[" "80.33 80.33 83.33 80.33 83.33 83.33 83.33 80.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[77.33 77.33" " 80.33 80.33 77.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[74.33 74.33 77.33 77.33 74.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 71.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('i" "nput',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "484" Ports [2, 1] Position [795, 600, 830, 635] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,35,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22." "55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 2" "2.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "\\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "485" Ports [1, 1] Position [790, 516, 830, 534] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "ceil(log2(MAX_NUM_SC))" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "data_sym_ind" SID "487" Position [890, 518, 920, 532] IconDisplay "Port number" } Block { BlockType Outport Name "data_sym_valid" SID "488" Position [890, 613, 920, 627] Port "2" IconDisplay "Port number" } Line { SrcBlock "sc_ind" SrcPort 1 Points [55, 0] Branch { DstBlock "11a Subcarrier Map" DstPort 1 } Branch { Points [0, 50] DstBlock "11n HT20 Subcarrier Map" DstPort 1 } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "11a Subcarrier Map" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "11n HT20 Subcarrier Map" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 Points [35, 0] Branch { Points [0, 85] DstBlock "Relational1" DstPort 1 } Branch { DstBlock "Slice" DstPort 1 } } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "data_sym_valid" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [20, 0; 0, 25] DstBlock "Logical" DstPort 1 } Line { SrcBlock "Full Rate" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "data_sym_ind" DstPort 1 } Annotation { Name "ROMs store mapping of subcarrier indexes as used by\nupstream logic to subcarrier indexes into the IF" "FT. These\nmaps also encode which subcarriers are occupied.\nUnoccupied subcarrier indexes are encoded as 64 in " "the\nROM (64 is an invalid subcarrier index).\n\nThe mapping in these ROMs implements the effective\n'fftshift' " "from the 802.11 standard, where subcarriers are\nloaded starting from the most negative subcarrier." Position [250, 692] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Delay" SID "489" Ports [1, 1] Position [1180, 378, 1210, 412] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "490" Ports [1, 1] Position [1180, 618, 1210, 652] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "2163" Ports [1, 1] Position [1260, 238, 1290, 272] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "491" Ports [1, 1] Position [1085, 513, 1115, 547] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "492" Ports [1, 1] Position [1085, 558, 1115, 592] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From6" SID "493" Position [120, 544, 215, 566] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "494" Ports [1, 1] Position [1430, 219, 1465, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "IQ tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "495" Ports [1, 1] Position [1430, 234, 1465, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "IQ tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "496" Ports [1, 1] Position [1430, 249, 1465, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Data Sym Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "2158" Ports [1, 1] Position [1430, 264, 1465, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sc Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "2162" Ports [1, 1] Position [1430, 279, 1465, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "IQ Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "2357" Ports [1, 1] Position [1430, 294, 1465, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Full Rate Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "2582" Ports [1, 1] Position [1430, 309, 1465, 321] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Pilot I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "497" Ports [1, 1] Position [1430, 204, 1465, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sym Bits Ready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical" SID "498" Ports [2, 1] Position [340, 361, 375, 394] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2148" Ports [2, 1] Position [595, 446, 630, 479] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.4" "4 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Scope Name "Mod Ctrl" SID "499" Ports [8] Position [1620, 200, 1655, 325] ZOrder -3 Floating off Location [218, 166, 2418, 1510] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "8000" YMin "0~0~0~0~0~0~0~-1" YMax "1~1~1~60~80~2~1~1" SaveName "ScopeData4" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Pilot Gen" SID "500" Ports [3, 2] Position [805, 518, 915, 592] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pilot Gen" Location [21, 80, 2158, 1372] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "sc_ind" SID "501" Position [215, 508, 245, 522] IconDisplay "Port number" } Block { BlockType Inport Name "reset" SID "502" Position [215, 668, 245, 682] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Pilot Shift" SID "2589" Position [215, 548, 245, 562] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "503" Ports [0, 1] Position [705, 672, 735, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_BPSK(1)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,f79afc1c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'-0.92578125');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "504" Ports [0, 1] Position [705, 642, 735, 658] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_BPSK(2)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,6adc731b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'0.92578125');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "505" Ports [1, 1] Position [305, 603, 335, 637] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "506" Ports [2, 1] Position [705, 601, 740, 634] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,33,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.4" "4 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 " "16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('xo" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "507" Ports [3, 1] Position [805, 605, 825, 695] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[16 0 0 32 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,90,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 12.8571 77.1429 90 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 12.8571 77.1429 90 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 " "7.55 5.55 ],[47.22 47.22 49.22 47.22 49.22 49.22 49.22 47.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[4" "5.22 45.22 47.22 47.22 45.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[43.22 43.22 45.22 45." "22 43.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[41.22 41.22 43.22 41.22 43.22 43.22 41.22" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_labe" "l('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Pilot Selection" SID "508" Ports [2, 2] Position [365, 507, 445, 543] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pilot Selection" Location [202, 70, 1918, 1152] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "158" Block { BlockType Inport Name "sc_ind" SID "509" Position [365, 213, 390, 227] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Shift" SID "2590" Position [265, 473, 290, 487] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "510" Ports [0, 1] Position [400, 297, 435, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "21" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,b02509bd,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'21');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "511" Ports [0, 1] Position [400, 262, 435, 288] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "512" Ports [0, 1] Position [400, 367, 435, 393] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "64-7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,624292f4,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'57');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "513" Ports [0, 1] Position [400, 332, 435, 358] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "64-21" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,86470e0e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'43');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "514" Ports [4, 1] Position [725, 270, 760, 405] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[2 0 0 2 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,135,4,1,white,blue,0,4f3eee2e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 135 135 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 135 135 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[72.55" " 72.55 77.55 72.55 77.55 77.55 77.55 72.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[67.55 67.55 72." "55 72.55 67.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[62.55 62.55 67.55 67.55 62.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[57.55 57.55 62.55 57.55 62.55 62.55 57.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" SID "2591" Ports [5, 1] Position [640, 464, 680, 636] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "40,172,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 24.5714 147.429 172 0 " "],[0.77 0.82 0.91 ]);\nplot([0 40 40 0 0 ],[0 24.5714 147.429 172 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 1" "3.875 8.875 ],[91.55 91.55 96.55 91.55 96.55 96.55 96.55 91.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.87" "5 ],[86.55 86.55 91.55 91.55 86.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[81.55 81.55 " "86.55 86.55 81.55 ],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[76.55 76.55 81.55 76.55 81.55 " "81.55 76.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon" " text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'" "d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "515" Ports [2, 1] Position [510, 269, 550, 296] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label(" "'output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "516" Ports [2, 1] Position [510, 304, 550, 331] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label(" "'output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "517" Ports [2, 1] Position [510, 339, 550, 366] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label(" "'output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational7" SID "518" Ports [2, 1] Position [510, 374, 550, 401] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[2 0 0 3 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,27,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label(" "'output',1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Pilot" SID "519" Position [915, 333, 945, 347] IconDisplay "Port number" } Block { BlockType Outport Name "Negate" SID "520" Position [915, 543, 945, 557] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational5" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational4" DstPort 1 } Line { SrcBlock "Relational4" SrcPort 1 Points [45, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 265] DstBlock "Mux" DstPort 3 } } Line { SrcBlock "Relational5" SrcPort 1 Points [55, 0] Branch { Points [0, 195] DstBlock "Mux" DstPort 2 } Branch { DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Relational6" SrcPort 1 Points [20, 0] Branch { DstBlock "Logical1" DstPort 3 } Branch { Points [0, 265] DstBlock "Mux" DstPort 5 } } Line { SrcBlock "Relational7" SrcPort 1 Points [30, 0] Branch { DstBlock "Logical1" DstPort 4 } Branch { Points [0, 195] DstBlock "Mux" DstPort 4 } } Line { SrcBlock "sc_ind" SrcPort 1 Points [90, 0; 0, 70] Branch { DstBlock "Relational4" DstPort 2 } Branch { Points [0, 35] Branch { DstBlock "Relational5" DstPort 2 } Branch { Points [0, 35] Branch { DstBlock "Relational6" DstPort 2 } Branch { Points [0, 35] DstBlock "Relational7" DstPort 2 } } } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Pilot" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational6" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational7" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Negate" DstPort 1 } Line { SrcBlock "Shift" SrcPort 1 DstBlock "Mux" DstPort 1 } Annotation { Name "All PHY modes:\n-Pilot tones in subcarriers [-21,-7,7,21]\n-Subcarriers [-7,-21] are x_ind [57,43]\n-" "One pilot per OFDM sybmol is opposite sign of other 3\n\n11a/g:\n-Opposite sign always in subcarrier 21\n\n11n/a" "c:\n-Syms 0:4: Same as a/g\n-Syms 5:6: No pilot tones in HT-STF, HT-LTF\n-Syms 7:N: Opposite sign pilot rotates " "across 4 subcarriers sequentially:\n 7: 21\n 8: 7\n 9: -21\n 10: -7\n ...\nLogic uses 2LSB of sym ind" "ex to select current negative pilot subcarrier" Position [598, 848] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Posedge" SID "521" Ports [1, 1] Position [450, 598, 505, 622] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "522" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "523" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "524" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "525" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "526" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Relational1" SID "527" Ports [2, 1] Position [375, 580, 410, 635] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a
Hardware notes: In hardware th" "is block costs nothing." assert_type on type_source "Explicitly" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,436" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,9657e937,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "532" Ports [1, 1] Position [665, 257, 710, 273] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware this" " block costs nothing." assert_type on type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,436" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,9657e937,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "533" Ports [1, 1] Position [305, 475, 330, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "534" Ports [1, 1] Position [305, 500, 330, 520] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "535" Ports [2, 1] Position [575, 233, 620, 277] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,dc21e094,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "536" Ports [3, 1] Position [400, 306, 445, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "537" Ports [3, 1] Position [485, 306, 530, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "538" Ports [3, 1] Position [575, 306, 620, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "539" Ports [3, 1] Position [665, 306, 710, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "540" Ports [3, 1] Position [825, 306, 870, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "541" Ports [3, 1] Position [915, 306, 960, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "542" Ports [3, 1] Position [1000, 306, 1045, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "543" Position [585, 188, 615, 202] NamePlacement "alternate" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 Points [20, 0; 0, -85] DstBlock "Assert" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [-225, 0] Branch { Points [0, 60] DstBlock "Register" DstPort 1 } Branch { Points [0, -60] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Register5" SrcPort 1 Points [0, -15] DstBlock "Register6" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 Points [45, 0; 0, -15] Branch { DstBlock "Register4" DstPort 1 } Branch { Points [0, -50] DstBlock "Assert1" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [0, -15] DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [5, 0; 0, -15] DstBlock "Register1" DstPort 1 } Line { SrcBlock "Assert" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Assert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "en" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [30, 0] Branch { Points [0, -155] DstBlock "Register" DstPort 2 } Branch { Points [95, 0] Branch { Points [0, -155] DstBlock "Register1" DstPort 2 } Branch { Points [80, 0] Branch { Points [0, -155] DstBlock "Register2" DstPort 2 } Branch { Points [100, 0] Branch { Points [0, -155] DstBlock "Register3" DstPort 2 } Branch { Points [150, 0] Branch { Points [0, -155] DstBlock "Register4" DstPort 2 } Branch { Points [100, 0] Branch { Points [0, -155] DstBlock "Register5" DstPort 2 } Branch { Points [80, 0; 0, -155] DstBlock "Register6" DstPort 2 } } } } } } } Line { SrcBlock "Convert1" SrcPort 1 Points [40, 0] Branch { Points [0, -165] DstBlock "Register" DstPort 3 } Branch { Points [95, 0] Branch { DstBlock "Register1" DstPort 3 } Branch { Points [80, 0] Branch { Points [0, -165] DstBlock "Register2" DstPort 3 } Branch { Points [100, 0] Branch { DstBlock "Register3" DstPort 3 } Branch { Points [150, 0] Branch { Points [0, -165] DstBlock "Register4" DstPort 3 } Branch { Points [100, 0] Branch { DstBlock "Register5" DstPort 3 } Branch { Points [75, 0; 0, -165] DstBlock "Register6" DstPort 3 } } } } } } } } } Block { BlockType Outport Name "pilot_valid" SID "544" Position [565, 508, 595, 522] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Pilot_I" SID "545" Position [940, 643, 970, 657] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Line { SrcBlock "Pilot Selection" SrcPort 1 DstBlock "pilot_valid" DstPort 1 } Line { SrcBlock "Pilot Selection" SrcPort 2 Points [220, 0; 0, 75] DstBlock "Logical" DstPort 1 } Line { SrcBlock "sc_ind" SrcPort 1 Points [25, 0] Branch { DstBlock "Pilot Selection" DstPort 1 } Branch { Points [0, 80] Branch { Points [0, 25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Relational1" DstPort 1 } } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "Scrambling LFSR" DstPort 1 } Line { SrcBlock "Scrambling LFSR" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Mux1" DstPort 1 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Pilot_I" DstPort 1 } Line { SrcBlock "reset" SrcPort 1 Points [260, 0; 0, -35] DstBlock "Scrambling LFSR" DstPort 2 } Line { SrcBlock "Pilot Shift" SrcPort 1 Points [100, 0] DstBlock "Pilot Selection" DstPort 2 } } } Block { BlockType SubSystem Name "Posedge" SID "546" Ports [1, 1] Position [405, 343, 450, 357] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "547" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "548" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "549" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "550" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "551" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "Posedge1" SID "552" Ports [1, 1] Position [405, 373, 450, 387] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "553" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "554" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "555" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "556" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "557" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "S-R Latch1" SID "558" Ports [2, 1] Position [485, 333, 520, 397] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "559" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "560" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "561" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "562" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "563" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "564" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "565" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "Subcarrier\nIndex Count" SID "566" Ports [2, 2] Position [660, 455, 730, 495] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subcarrier\nIndex Count" Location [263, 1164, 796, 1358] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "en" SID "567" Position [95, 463, 125, 477] IconDisplay "Port number" } Block { BlockType Inport Name "reset" SID "568" Position [170, 383, 200, 397] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "569" Ports [2, 1] Position [410, 227, 450, 258] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "40,31,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_lab" "el('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "570" Ports [0, 1] Position [330, 242, 360, 258] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From5" SID "571" Position [210, 228, 340, 242] ShowName off CloseFcn "tagdialog Close" GotoTag "regTx_NUM_SC" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "572" Ports [2, 1] Position [205, 422, 245, 453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');di" "sp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "573" Ports [2, 1] Position [290, 382, 330, 413] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 31 31 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');di" "sp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "574" Ports [2, 1] Position [535, 334, 580, 376] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 2" "7.66 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 " "27.66 21.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa" " = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Subcarrier\nIndex" SID "575" Ports [2, 1] Position [400, 380, 460, 440] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "47" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "4" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38" ".88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38." "88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf" "++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "sc_ind" SID "576" Position [625, 403, 655, 417] IconDisplay "Port number" } Block { BlockType Outport Name "last" SID "577" Position [625, 633, 655, 647] Port "2" IconDisplay "Port number" } Line { SrcBlock "Subcarrier\nIndex" SrcPort 1 Points [40, 0] Branch { Points [0, -45] DstBlock "Relational3" DstPort 2 } Branch { DstBlock "sc_ind" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 Points [50, 0; 0, 100] DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 Points [45, 0; 0, -40; -465, 0; 0, 115] DstBlock "Logical1" DstPort 1 } Line { SrcBlock "en" SrcPort 1 Points [35, 0] Branch { Points [190, 0; 0, -45] DstBlock "Subcarrier\nIndex" DstPort 2 } Branch { Points [0, -25] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Subcarrier\nIndex" DstPort 1 } Line { SrcBlock "reset" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 Points [25, 0] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, 200] DstBlock "last" DstPort 1 } } Line { SrcBlock "From5" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "AddSub" DstPort 2 } } } Block { BlockType Outport Name "Pilot I" SID "578" Position [1310, 568, 1340, 582] IconDisplay "Port number" } Block { BlockType Outport Name "IQ Sel" SID "579" Position [1310, 523, 1340, 537] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "IQ tvalid" SID "580" Position [1310, 388, 1340, 402] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "IQ tlast" SID "581" Position [1310, 628, 1340, 642] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Data Sym Ind" SID "582" Position [1310, 433, 1340, 447] Port "5" IconDisplay "Port number" } Line { SrcBlock "Subcarrier\nIndex Count" SrcPort 1 Points [35, 0] Branch { DstBlock "Data SC Map" DstPort 2 } Branch { Points [0, 65] DstBlock "Pilot Gen" DstPort 1 } Branch { Points [0, -195] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Pilot Gen" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Data SC Map" SrcPort 2 Points [40, 0; 0, 55] DstBlock "Concat1" DstPort 1 } Line { SrcBlock "Data SC Map" SrcPort 1 Points [325, 0] Branch { DstBlock "Data Sym Ind" DstPort 1 } Branch { DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Delay5" DstPort 1 } Line { SrcBlock "Pilot Gen" SrcPort 2 DstBlock "Delay6" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 Points [85, 0] Branch { Points [325, 0; 0, 0] Branch { Points [0, -70] DstBlock "Subcarrier\nIndex Count" DstPort 2 } Branch { DstBlock "Pilot Gen" DstPort 2 } } Branch { Points [0, -185] DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Sym Bits Rdy" SrcPort 1 Points [120, 0] Branch { DstBlock "Posedge" DstPort 1 } Branch { Points [0, -140] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Subcarrier\nIndex Count" SrcPort 2 Points [15, 0; 0, 150] Branch { Points [-440, 0; 0, -250] DstBlock "Logical" DstPort 2 } Branch { DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [20, 0; 0, 30] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, 60] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [20, 0] Branch { DstBlock "IQ tvalid" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [25, 0] Branch { DstBlock "IQ tlast" DstPort 1 } Branch { Points [0, -395] DstBlock "Gateway Out2" DstPort 1 } } Line { Name "Sym Bits Ready" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Mod Ctrl" DstPort 1 } Line { Name "IQ tvalid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Mod Ctrl" DstPort 2 } Line { Name "IQ tlast" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Mod Ctrl" DstPort 3 } Line { Name "Data Sym Ind" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Mod Ctrl" DstPort 4 } Line { SrcBlock "Delay5" SrcPort 1 Points [140, 0] Branch { DstBlock "IQ Sel" DstPort 1 } Branch { Points [0, -245] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Delay6" SrcPort 1 Points [150, 0] Branch { DstBlock "Pilot I" DstPort 1 } Branch { Points [0, -260] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Subcarrier\nIndex Count" DstPort 1 } Line { SrcBlock "IQ FIFO tready" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { Name "Sc Ind" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Mod Ctrl" DstPort 5 } Line { SrcBlock "Full Rate" SrcPort 1 Points [375, 0] Branch { Points [0, 20] DstBlock "Data SC Map" DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out6" DstPort 1 } } Line { Name "IQ Sel" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Mod Ctrl" DstPort 6 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Gateway Out3" DstPort 1 } Line { Name "Full Rate Sym" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Mod Ctrl" DstPort 7 } Line { Name "Pilot I" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Mod Ctrl" DstPort 8 } Line { SrcBlock "Pilot Shift" SrcPort 1 DstBlock "Pilot Gen" DstPort 3 } Annotation { Name "1 cycle for RAM access" Position [1195, 363] } } } Block { BlockType Reference Name "Delay" SID "583" Ports [1, 1] Position [725, 83, 755, 117] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 " "21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 2" "1.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "584" Position [920, 343, 1105, 367] ZOrder -9 ShowName off GotoTag "OFDM_TX_DATA_Mod_Sel" TagVisibility "global" } Block { BlockType From Name "From1" SID "585" Position [1240, 357, 1310, 373] ZOrder -9 ShowName off GotoTag "BPSK_I" } Block { BlockType From Name "From10" SID "586" Position [1240, 447, 1310, 463] ZOrder -9 ShowName off GotoTag "QAM64_I" } Block { BlockType From Name "From11" SID "587" Position [1240, 622, 1310, 638] ZOrder -9 ShowName off GotoTag "QAM64_Q" } Block { BlockType From Name "From2" SID "588" Position [1240, 532, 1310, 548] ZOrder -9 ShowName off GotoTag "BPSK_Q" } Block { BlockType From Name "From3" SID "589" Position [1240, 387, 1310, 403] ZOrder -9 ShowName off GotoTag "QPSK_I" } Block { BlockType From Name "From4" SID "590" Position [1240, 562, 1310, 578] ZOrder -9 ShowName off GotoTag "QPSK_Q" } Block { BlockType From Name "From5" SID "591" Position [1415, 347, 1485, 363] ZOrder -9 ShowName off GotoTag "PILOT_I" } Block { BlockType From Name "From6" SID "592" Position [1240, 417, 1310, 433] ZOrder -9 ShowName off GotoTag "QAM16_I" } Block { BlockType From Name "From7" SID "593" Position [1415, 267, 1485, 283] ZOrder -9 ShowName off GotoTag "IQ_SEL" } Block { BlockType From Name "From8" SID "3610" Position [855, 947, 925, 963] ZOrder -9 ShowName off GotoTag "IQ_SEL" } Block { BlockType From Name "From9" SID "594" Position [1240, 592, 1310, 608] ZOrder -9 ShowName off GotoTag "QAM16_Q" } Block { BlockType Reference Name "Gateway Out1" SID "2308" Ports [1, 1] Position [1645, 124, 1680, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Full Rate Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "595" Ports [1, 1] Position [1645, 79, 1680, 91] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Mod Rate Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "2309" Ports [1, 1] Position [1645, 139, 1680, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Base Rate Sym" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3606" Ports [1, 1] Position [1170, 889, 1205, 901] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "3607" Ports [1, 1] Position [1170, 929, 1205, 941] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "596" Ports [1, 1] Position [1645, 94, 1680, 106] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Data Mod Rate" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "597" Ports [1, 1] Position [1645, 109, 1680, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "598" Ports [1, 1] Position [1645, 154, 1680, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "599" Ports [1, 1] Position [1645, 169, 1680, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "600" Position [815, 632, 885, 648] ZOrder -10 ShowName off GotoTag "BPSK_I" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "601" Position [815, 647, 885, 663] ZOrder -10 ShowName off GotoTag "BPSK_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "602" Position [815, 827, 885, 843] ZOrder -10 ShowName off GotoTag "QAM64_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "603" Position [815, 692, 885, 708] ZOrder -10 ShowName off GotoTag "QPSK_I" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "604" Position [815, 707, 885, 723] ZOrder -10 ShowName off GotoTag "QPSK_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "605" Position [895, 427, 965, 443] ZOrder -10 ShowName off GotoTag "PILOT_I" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "606" Position [895, 452, 965, 468] ZOrder -10 ShowName off GotoTag "IQ_SEL" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "607" Position [815, 752, 885, 768] ZOrder -10 ShowName off GotoTag "QAM16_I" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "608" Position [815, 767, 885, 783] ZOrder -10 ShowName off GotoTag "QAM16_Q" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "609" Position [815, 812, 885, 828] ZOrder -10 ShowName off GotoTag "QAM64_I" TagVisibility "local" } Block { BlockType Reference Name "Logical1" SID "3609" Ports [2, 1] Position [1070, 914, 1095, 956] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 42 42 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[24" ".33 24.33 27.33 24.33 27.33 27.33 27.33 24.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[21.33 21.33 " "24.33 24.33 21.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[18.33 18.33 21.33 21.33 18.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[15.33 15.33 18.33 15.33 18.33 18.33 15.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "610" Ports [2, 1] Position [1175, 293, 1200, 377] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,84,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 84 84 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 84 84 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[45" ".33 45.33 48.33 45.33 48.33 48.33 48.33 45.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[42.33 42.33 " "45.33 45.33 42.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[39.33 39.33 42.33 42.33 39.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[36.33 36.33 39.33 36.33 39.33 39.33 36.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "MCode" SID "2587" Ports [1, 8] Position [265, 140, 515, 255] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input po" "rts of the block are input arguments of the function. The output ports of the block are output arguments of the" " function." mfname "sym_config_decode" explicit_period on period "1" inputsTable "{'boundInpExpr'=>[''],'inputs'=>['sym_cfg']}" outputsTable "{'outputs'=>['load_base_rate','rotate_bpsk','load_htstf','load_htltf','load_full_rate','pil" "ot_shift','cyclic_prefix','cyclic_shift'],'suppressOut'=>['off','off','off','off','off','off','off','off']}" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "250,115,1,8,white,blue,0,d3620376,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 250 250 0 0 ],[0 0 115 115 0 ],[0." "77 0.82 0.91 ]);\nplot([0 250 250 0 0 ],[0 0 115 115 0 ]);\npatch([89.4 112.52 128.52 144.52 160.52 128.52 105." "4 89.4 ],[74.76 74.76 90.76 74.76 90.76 90.76 90.76 74.76 ],[1 1 1 ]);\npatch([105.4 128.52 112.52 89.4 105.4 ]" ",[58.76 58.76 74.76 74.76 58.76 ],[0.931 0.946 0.973 ]);\npatch([89.4 112.52 128.52 105.4 89.4 ],[42.76 42.76 5" "8.76 58.76 42.76 ],[1 1 1 ]);\npatch([105.4 160.52 144.52 128.52 112.52 89.4 105.4 ],[26.76 26.76 42.76 26.76 4" "2.76 42.76 26.76 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\ncolor('black');port_label('input',1,'sym_cfg');\ncolor('black');port_label('output',1,'load_bas" "e_rate');\ncolor('black');port_label('output',2,'rotate_bpsk');\ncolor('black');port_label('output',3,'load_hts" "tf');\ncolor('black');port_label('output',4,'load_htltf');\ncolor('black');port_label('output',5,'load_full_rat" "e');\ncolor('black');port_label('output',6,'pilot_shift');\ncolor('black');port_label('output',7,'cyclic_prefix" "');\ncolor('black');port_label('output',8,'cyclic_shift');\ncolor('black');disp('\\bf{sym\\_config\\_decode}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Mod " SID "611" Ports [7] Position [1830, 83, 1865, 177] ZOrder -3 Floating off Location [1, 45, 1843, 1199] Open on NumInputPorts "7" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~0~-2~0~-0.1~-0.1" YMax "300~300~1~2~4000~1.1~1.1" SaveName "ScopeData28" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Mux1" SID "612" Ports [5, 1] Position [1360, 318, 1385, 472] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,154,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 22 132 154 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 22 132 154 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325" " ],[80.33 80.33 83.33 80.33 83.33 83.33 83.33 80.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[77.33 " "77.33 80.33 80.33 77.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[74.33 74.33 77.33 77.3" "3 74.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 71" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port" "_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');" "\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "613" Ports [5, 1] Position [1360, 493, 1385, 647] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,154,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 22 132 154 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 22 132 154 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325" " ],[80.33 80.33 83.33 80.33 83.33 83.33 83.33 80.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[77.33 " "77.33 80.33 80.33 77.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[74.33 74.33 77.33 77.3" "3 74.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 71" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port" "_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');" "\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "614" Ports [4, 1] Position [1550, 258, 1575, 412] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,154,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 22 132 154 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 22 132 154 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325" " ],[80.33 80.33 83.33 80.33 83.33 83.33 83.33 80.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[77.33 " "77.33 80.33 80.33 77.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[74.33 74.33 77.33 77.3" "3 74.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 71" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port" "_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "615" Ports [4, 1] Position [1550, 433, 1575, 587] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,154,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 22 132 154 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 22 132 154 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325" " ],[80.33 80.33 83.33 80.33 83.33 83.33 83.33 80.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[77.33 " "77.33 80.33 80.33 77.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[74.33 74.33 77.33 77.3" "3 74.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 71" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port" "_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "QPSK Mod" SID "616" Ports [1, 2] Position [710, 690, 750, 725] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "QPSK Mod" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "b[1:0]" SID "617" Position [280, 178, 310, 192] IconDisplay "Port number" } Block { BlockType Reference Name "Constant2" SID "618" Ports [0, 1] Position [515, 202, 635, 228] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_QPSK(1)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,47e7e2f8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'-0.65478515625');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "619" Ports [0, 1] Position [515, 232, 635, 258] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "Mod_Constellation_QPSK(2)" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "120,26,0,1,white,blue,0,d9c0b92d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 120 120 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 120 120 0 0 ],[0 0 26 26 0 ]);\npatch([53.325 57.66 60.66 63.66 66.66 60.66 56.325 53.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([56.325 60.66 57.66 53.325 56.325 ],[13.33 13.33 1" "6.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([53.325 57.66 60.66 56.325 53.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([56.325 66.66 63.66 60.66 57.66 53.325 56.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'0.65478515625');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB" SID "620" Ports [1, 1] Position [355, 176, 390, 194] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB+1" SID "621" Ports [1, 1] Position [355, 281, 390, 299] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "622" Ports [3, 1] Position [705, 167, 735, 263] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,96,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ],[0." "77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6" ".1 ],[52.44 52.44 56.44 52.44 56.44 56.44 56.44 52.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[48.44 48.4" "4 52.44 52.44 48.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[44.44 44.44 48.44 48.44 44.44 ],[" "1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[40.44 40.44 44.44 40.44 44.44 44.44 40.44 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');" "\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "623" Ports [3, 1] Position [705, 272, 735, 368] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,96,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ],[0." "77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 13.7143 82.2857 96 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6" ".1 ],[52.44 52.44 56.44 52.44 56.44 56.44 56.44 52.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[48.44 48.4" "4 52.44 52.44 48.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[44.44 44.44 48.44 48.44 44.44 ],[" "1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[40.44 40.44 44.44 40.44 44.44 44.44 40.44 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');" "\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "624" Position [760, 208, 790, 222] IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "625" Position [760, 313, 790, 327] Port "2" IconDisplay "Port number" } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 Points [30, 0] Branch { Points [0, 105] DstBlock "Mux1" DstPort 3 } Branch { DstBlock "Mux" DstPort 3 } } Line { SrcBlock "Constant2" SrcPort 1 Points [40, 0] Branch { Points [0, 105] DstBlock "Mux1" DstPort 2 } Branch { DstBlock "Mux" DstPort 2 } } Line { SrcBlock "b[1:0]" SrcPort 1 Points [15, 0] Branch { DstBlock "LSB" DstPort 1 } Branch { Points [0, 105] DstBlock "LSB+1" DstPort 1 } } Line { SrcBlock "LSB" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "LSB+1" SrcPort 1 DstBlock "Mux1" DstPort 1 } } } Block { BlockType Reference Name "Relational" SID "3608" Ports [2, 1] Position [995, 931, 1040, 964] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,33,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 33 33 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 33 33 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType ToWorkspace Name "To Workspace" SID "3604" Ports [1] Position [1235, 881, 1385, 909] ZOrder -7 ShowName off VariableName "tx_bits_enc_intlv_scr" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "3605" Ports [1] Position [1235, 921, 1385, 949] ZOrder -7 ShowName off VariableName "tx_bits_enc_intlv_scr_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Outport Name "Data Sym Ind" SID "642" Position [1005, 528, 1035, 542] IconDisplay "Port number" } Block { BlockType Outport Name " Sym Cfg" SID "643" Position [1000, 93, 1030, 107] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "I" SID "644" Position [1640, 328, 1670, 342] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "645" Position [1640, 503, 1670, 517] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "IQ tvalid" SID "646" Position [1005, 478, 1035, 492] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "IQ tlast" SID "647" Position [960, 503, 990, 517] Port "6" IconDisplay "Port number" } Line { SrcBlock "From10" SrcPort 1 DstBlock "Mux1" DstPort 5 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Mux2" DstPort 5 } Line { SrcBlock "BPSK Mod" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "BPSK Mod" SrcPort 2 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "QPSK Mod" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "QPSK Mod" SrcPort 2 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Logical2" SrcPort 1 Points [25, 0] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, 175] DstBlock "Mux2" DstPort 1 } Branch { Points [0, -250] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "From3" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Constant5" SrcPort 1 Points [25, 0] Branch { DstBlock "Mux4" DstPort 2 } Branch { Points [0, 40] DstBlock "Mux4" DstPort 3 } } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Mux3" DstPort 4 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Mux4" DstPort 4 } Line { SrcBlock "Mux3" SrcPort 1 Points [5, 0] Branch { DstBlock "I" DstPort 1 } Branch { Points [0, -175] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Mux4" SrcPort 1 Points [10, 0] Branch { DstBlock "Q" DstPort 1 } Branch { Points [0, -335] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "From7" SrcPort 1 Points [35, 0] Branch { DstBlock "Mux3" DstPort 1 } Branch { Points [0, 175] DstBlock "Mux4" DstPort 1 } Branch { Points [0, -160] DstBlock "Gateway Out6" DstPort 1 } } Line { Name "Mod Rate Sel" Labels [-1, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Mod " DstPort 1 } Line { Name "Data Mod Rate" Labels [-1, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Mod " DstPort 2 } Line { Name "IQ Sel" Labels [1, 1] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Mod " DstPort 3 } Line { Name "I" Labels [1, 1] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Mod " DstPort 6 } Line { Name "Q" Labels [1, 1] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Mod " DstPort 7 } Line { SrcBlock "16QAM Mod" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "16QAM Mod" SrcPort 2 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Mux1" DstPort 4 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Mux2" DstPort 4 } Line { SrcBlock "64QAM Mod" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "64QAM Mod" SrcPort 2 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Sc Bits" SrcPort 1 Points [200, 0] Branch { Points [0, 70] Branch { Points [0, 60] Branch { DstBlock "4LSB" DstPort 1 } Branch { Points [0, 60] DstBlock "6LSB" DstPort 1 } } Branch { DstBlock "2LSB" DstPort 1 } } Branch { DstBlock "1LSB" DstPort 1 } Branch { Points [0, 255] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Control & Pilots" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Control & Pilots" SrcPort 2 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Sym Bits Rdy" SrcPort 1 DstBlock "Control & Pilots" DstPort 3 } Line { SrcBlock "Sym Cfg" SrcPort 1 Points [30, 0] Branch { Points [0, -100] DstBlock "Delay" DstPort 1 } Branch { DstBlock "MCode" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [35, 0] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, -255] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Control & Pilots" SrcPort 3 Points [130, 0] Branch { DstBlock "IQ tvalid" DstPort 1 } Branch { Points [0, 440] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Control & Pilots" SrcPort 4 DstBlock "IQ tlast" DstPort 1 } Line { SrcBlock "Control & Pilots" SrcPort 5 DstBlock "Data Sym Ind" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Sym Cfg" DstPort 1 } Line { SrcBlock "IQ FIFO tready" SrcPort 1 DstBlock "Control & Pilots" DstPort 4 } Line { SrcBlock "1LSB" SrcPort 1 DstBlock "BPSK Mod" DstPort 1 } Line { SrcBlock "2LSB" SrcPort 1 DstBlock "QPSK Mod" DstPort 1 } Line { SrcBlock "4LSB" SrcPort 1 DstBlock "16QAM Mod" DstPort 1 } Line { SrcBlock "6LSB" SrcPort 1 DstBlock "64QAM Mod" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "MCode" SrcPort 5 Points [60, 0] Branch { Points [0, 230] DstBlock "Control & Pilots" DstPort 1 } Branch { Points [475, 0] Branch { Points [0, 100] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, 20] DstBlock "Concat" DstPort 2 } } Branch { Points [0, -75] DstBlock "Gateway Out1" DstPort 1 } } } Line { Name "Full Rate Sym" Labels [-1, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Mod " DstPort 4 } Line { Name "Base Rate Sym" Labels [-1, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Mod " DstPort 5 } Line { SrcBlock "MCode" SrcPort 1 DstBlock "Gateway Out2" DstPort 1 } Line { SrcBlock "MCode" SrcPort 2 Points [50, 0; 0, 495] DstBlock "BPSK Mod" DstPort 2 } Line { SrcBlock "MCode" SrcPort 6 Points [55, 0; 0, 250] DstBlock "Control & Pilots" DstPort 2 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Gateway Out4" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 Points [35, 0; 0, 5] DstBlock "Relational" DstPort 1 } Annotation { Name "Foce base rate syms to BPSK" Position [1038, 379] } Annotation { Name "Use local GOTOs to avoid\nrouting mess at mux inputs" Position [834, 868] } } } Block { BlockType SubSystem Name "Pkt Data" SID "648" Ports [5, 5] Position [620, 371, 745, 469] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pkt Data" Location [-158, 363, 1502, 1307] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "111" Block { BlockType Inport Name "Sym Cfg" SID "649" Position [210, 753, 240, 767] IconDisplay "Port number" } Block { BlockType Inport Name "Byte Ind" SID "650" Position [210, 458, 240, 472] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Byte Ind Valid " SID "651" Position [210, 568, 240, 582] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Bit Sel" SID "652" Position [210, 333, 240, 347] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Bit Sel Valid" SID "653" Position [210, 278, 240, 292] Port "5" IconDisplay "Port number" } Block { BlockType SubSystem Name "BRAM IF 64b" SID "654" Ports [1, 1] Position [590, 442, 705, 488] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "BRAM IF 64b" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Byte Addr" SID "655" Position [205, 623, 235, 637] IconDisplay "Port number" } Block { BlockType Reference Name "12 LSB" SID "656" Ports [1, 1] Position [310, 620, 355, 640] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "ceil(log2(MAX_NUM_BYTES))" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2.02" sg_icon_stat "45,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('ou" "tput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "3 LSB" SID "657" Ports [1, 1] Position [595, 660, 640, 680] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2.02" sg_icon_stat "45,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('ou" "tput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "658" Ports [2, 1] Position [695, 586, 755, 644] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))-3" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "60,58,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[37.88 37.88 45" ".88 37.88 45.88 45.88 45.88 37.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[29.88 29.88 37.88 37.88 29.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[21.88 21.88 29.88 29.88 21.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "BRAM Addr Map" SID "659" Ports [1, 1] Position [410, 617, 515, 643] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "BRAM Addr Map" Location [130, 120, 1790, 1080] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Tx Ind" SID "660" Position [385, 258, 415, 272] IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "661" Ports [2, 1] Position [690, 410, 735, 450] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,40,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 40 40 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[25.55 2" "5.55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[20.55 20.55 25.5" "5 25.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[15.55 15.55 20.55 20.55 15.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('b" "lack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'" ",1,'\\bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "662" Ports [0, 1] Position [390, 376, 415, 404] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,28,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "663" Ports [0, 1] Position [390, 511, 415, 539] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "11" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,28,0,1,white,blue,0,997df0ab,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('output',1,'11');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "664" Ports [0, 1] Position [390, 421, 415, 449] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "10" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,28,0,1,white,blue,0,46ffeebb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('output',1,'10');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "665" Ports [0, 1] Position [390, 556, 415, 584] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,28,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "666" Position [230, 333, 395, 357] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n_ac" TagVisibility "global" } Block { BlockType Reference Name "Mux1" SID "667" Ports [3, 1] Position [465, 323, 490, 457] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,134,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.1429 114.857 134 0 " "],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12." "66 8.325 5.325 ],[70.33 70.33 73.33 70.33 73.33 73.33 73.33 70.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8." "325 ],[67.33 67.33 70.33 70.33 67.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[64.33 64.3" "3 67.33 67.33 64.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[61.33 61.33 64.33 61.33 64." "33 64.33 61.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('bla" "ck');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon" " text');" } Block { BlockType Reference Name "Mux2" SID "668" Ports [3, 1] Position [465, 458, 490, 592] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,134,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.1429 114.857 134 0 " "],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12." "66 8.325 5.325 ],[70.33 70.33 73.33 70.33 73.33 73.33 73.33 70.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8." "325 ],[67.33 67.33 70.33 70.33 67.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[64.33 64.3" "3 67.33 67.33 64.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[61.33 61.33 64.33 61.33 64." "33 64.33 61.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('bla" "ck');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon" " text');" } Block { BlockType Reference Name "Mux5" SID "669" Ports [3, 1] Position [805, 363, 830, 497] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,134,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.1429 114.857 134 0 " "],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.1429 114.857 134 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12." "66 8.325 5.325 ],[70.33 70.33 73.33 70.33 73.33 73.33 73.33 70.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8." "325 ],[67.33 67.33 70.33 70.33 67.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[64.33 64.3" "3 67.33 67.33 64.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[61.33 61.33 64.33 61.33 64." "33 64.33 61.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('bla" "ck');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon" " text');" } Block { BlockType Reference Name "Relational" SID "670" Ports [2, 1] Position [695, 367, 730, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,31,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','t" "exmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Mem Addr" SID "671" Position [935, 423, 965, 437] IconDisplay "Port number" } Line { SrcBlock "Mux2" SrcPort 1 Points [140, 0; 0, -85] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Tx Ind" SrcPort 1 Points [245, 0; 0, 110] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 45] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 55] DstBlock "Mux5" DstPort 3 } } } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Mux5" DstPort 1 } Line { SrcBlock "Mux5" SrcPort 1 DstBlock "Mem Addr" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Mux5" DstPort 2 } Line { SrcBlock "From2" SrcPort 1 Points [35, 0] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, 135] DstBlock "Mux2" DstPort 1 } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux2" DstPort 3 } Annotation { Name "OFDM Byte Index Tx -> Memory mapping\n11a/g Tx\n\nT=Tx byte index\nM=Memory byte index\n\nT M\n0 0 " " SIGNAL[0]\n1 1 SIGNAL[1]\n2 2 SIGNAL[2]\n3 3 SERVICE[0]\n4 4 SERVICE[1]\n 5 no read\n ...\n " " 15 no read\n5 16 MPDU[0]\n6 17 MPDU[1]\n..." Position [309, 969] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } Annotation { Name "OFDM Byte Index Tx -> Memory mapping\n11n/ac Tx\n\nT=Rx byte index\nM=Memory byte index\n\nT M\n0 0" " SIGNAL[0]\n1 1 SIGNAL[1]\n2 2 SIGNAL[2]\n3 3 HT-SIG[0]\n4 4 HT-SIG[1]\n5 5 HT-SIG[2]\n6 6 H" "T-SIG[3]\n7 7 HT-SIG[4]\n8 8 HT-SIG[5]\n9 9 SERVICE[0]\n10 10 SERVICE[1]\n 11 no read\n...\n 15 " "no read\n11 16 MAC Payload[0]\n12 17 MAC Payload[1]\n..." Position [589, 1009] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } Annotation { Name "Packet buffer contents depend on the PHY mode. 11n payloads\nmust include the HTSIG field, for exampl" "e. For easier addressing\nin software the Tx PHY logic uses the address mapping below. Note\nthat the MAC payloa" "d always starts at a 64-bit aligned address. This\nallows efficient use of the DMA in CPU high to move MAC paylo" "ads into\nthe packet buffer. CPU Low adds the PHY-mode-specific fields before\ntransmission.\n\nThe MAC code mus" "t write valid bytes for SIGNAL, HT-SIG and SERVICE\nfields. The PHY will abort if the SIGNAL or HT-SIG fields ar" "e invlid.\nThe MAC software must set the SERVICE field bytes to 0 to ensure\nthe resulting payload can be de-scr" "ambled by the receiver." Position [319, 724] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } } } Block { BlockType SubSystem Name "BRAM Interface" SID "672" Ports [2, 1] Position [860, 572, 1000, 628] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "BRAM Interface" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Pkt Buf Index" SID "673" Position [325, 513, 355, 527] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "64b Word Addr" SID "674" Position [325, 533, 355, 547] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "BRAM_Addr" SID "675" Ports [1, 1] Position [635, 520, 690, 540] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,356,332" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_Din" SID "676" Ports [1, 1] Position [635, 434, 690, 456] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to X" "ilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level" " input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "64" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,22,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 22 22 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 22 22 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.985 0.979 0.895 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.985 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1" ",' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_Dout" SID "677" Ports [1, 1] Position [635, 725, 690, 745] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,356,332" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_En" SID "678" Ports [1, 1] Position [635, 605, 695, 625] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2.02" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_Reset" SID "679" Ports [1, 1] Position [635, 660, 695, 680] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2.02" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BRAM_WEn" SID "680" Ports [1, 1] Position [635, 775, 690, 795] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, doub" "le, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarde" "d, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,356,332" block_type "gatewayout" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "681" Ports [4, 1] Position [515, 494, 560, 566] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "4" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,72,4,1,white,blue,0,47d3d416,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 72 72 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 72 72 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[42.66 4" "2.66 48.66 42.66 48.66 48.66 48.66 42.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[36.66 36.66 42.66 " "42.66 36.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[30.66 30.66 36.66 36.66 30.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 24.66 30.66 30.66 24.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'hi');\n\n\ncolor('black');port_label('input',4,'lo');\n\ncolor('black');disp('\\fontsize" "{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant" SID "682" Position [565, 432, 590, 458] ZOrder -5 ShowName off Value "0" } Block { BlockType Reference Name "Constant1" SID "683" Ports [0, 1] Position [555, 604, 575, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "684" Ports [0, 1] Position [555, 659, 575, 681] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "685" Ports [0, 1] Position [425, 549, 450, 571] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "686" Ports [0, 1] Position [425, 489, 450, 511] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "16" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "687" Ports [0, 1] Position [555, 724, 575, 746] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "64" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant8" SID "688" Ports [0, 1] Position [555, 774, 575, 796] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2.02" sg_icon_stat "20,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13." "22 15.22 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22" " 11.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npa" "tch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output" "',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Sim RAM" SID "689" Ports [1, 1] Position [625, 356, 700, 394] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sim RAM" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr" SID "690" Position [150, 578, 180, 592] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "691" Ports [2, 1] Position [510, 540, 570, 600] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38" ".88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38." "88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "692" Ports [1, 1] Position [295, 570, 340, 600] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))-3" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_l" "abel('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Disregard Subsystem" SID "693" Tag "discardX" Ports [] Position [408, 672, 466, 730] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code gener" "ation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative sim" "ulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0.1 0" ".1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 37.88" " 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.88 37." "88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.88 ],[0" ".33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ]," "[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "ROM1" SID "694" Ports [1, 1] Position [405, 487, 465, 543] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_BYTES/8" initVector "PPDU_words(2:2:end)" distributed_mem "Block RAM" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "60,56,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text')" ";" } Block { BlockType Reference Name "ROM2" SID "695" Ports [1, 1] Position [405, 557, 465, 613] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_BYTES/8" initVector "PPDU_words(1:2:end)" distributed_mem "Block RAM" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "60,56,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text')" ";" } Block { BlockType Outport Name "64b" SID "696" Position [670, 563, 700, 577] IconDisplay "Port number" } Line { SrcBlock "Concat" SrcPort 1 DstBlock "64b" DstPort 1 } Line { SrcBlock "ROM1" SrcPort 1 Points [10, 0; 0, 40] DstBlock "Concat" DstPort 1 } Line { SrcBlock "ROM2" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 Points [30, 0] Branch { Points [0, -70] DstBlock "ROM1" DstPort 1 } Branch { DstBlock "ROM2" DstPort 1 } } Line { SrcBlock "Addr" SrcPort 1 DstBlock "Convert2" DstPort 1 } Annotation { Name "This subsystem is only used in simulation.\n\nThe ROMs below emulate the Tx packet buffer in the full" " 802.11 Reference Design.\nThese ROMs are initalized with a packet defined in the .m init script. The PHY uses\n" "this packet in its simulation. In hardware the PHY pulls its packets directly from\nthe Tx packet buffer, whose " "contents are controlled by the MAC software.\n\nThese ROMs accurately mimic the 1 cycle latency for accessing th" "e packet buffer BRAMs\nin the real design. It is essential the packet buffer implementation honor this 1-cycle \n" "assumption." Position [275, 394] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Simulation Multiplexer" SID "697" Ports [2, 1] Position [835, 407, 885, 458] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified" " For Simulation will be used during Simulink simulation. The input specified For Generation will be used during" " code generation. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim" " subsystem.

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "simmux" sg_icon_stat "50,51,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n" "\n\nfprintf('','COMMENT: end icon text');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX" ",hwSwLineY);\n" } Block { BlockType Terminator Name "Terminator" SID "698" Position [740, 525, 750, 535] ShowName off } Block { BlockType Terminator Name "Terminator2" SID "699" Position [740, 730, 750, 740] ShowName off } Block { BlockType Terminator Name "Terminator3" SID "700" Position [740, 610, 750, 620] ShowName off } Block { BlockType Terminator Name "Terminator4" SID "701" Position [740, 665, 750, 675] ShowName off } Block { BlockType Terminator Name "Terminator5" SID "702" Position [740, 780, 750, 790] ShowName off } Block { BlockType Outport Name "64b Data" SID "703" Position [965, 428, 995, 442] IconDisplay "Port number" } Line { SrcBlock "Sim RAM" SrcPort 1 Points [70, 0; 0, 45] DstBlock "Simulation Multiplexer" DstPort 1 } Line { SrcBlock "BRAM_Din" SrcPort 1 DstBlock "Simulation Multiplexer" DstPort 2 } Line { SrcBlock "BRAM_WEn" SrcPort 1 DstBlock "Terminator5" DstPort 1 } Line { SrcBlock "BRAM_Reset" SrcPort 1 DstBlock "Terminator4" DstPort 1 } Line { SrcBlock "BRAM_En" SrcPort 1 DstBlock "Terminator3" DstPort 1 } Line { SrcBlock "BRAM_Dout" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "BRAM_Addr" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "BRAM_Reset" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "BRAM_En" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "BRAM_Din" DstPort 1 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "BRAM_Dout" DstPort 1 } Line { SrcBlock "Constant8" SrcPort 1 DstBlock "BRAM_WEn" DstPort 1 } Line { SrcBlock "64b Word Addr" SrcPort 1 Points [50, 0] Branch { Points [0, -165] DstBlock "Sim RAM" DstPort 1 } Branch { DstBlock "Concat" DstPort 3 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "BRAM_Addr" DstPort 1 } Line { SrcBlock "Simulation Multiplexer" SrcPort 1 DstBlock "64b Data" DstPort 1 } Line { SrcBlock "Pkt Buf Index" SrcPort 1 DstBlock "Concat" DstPort 2 } } } Block { BlockType SubSystem Name "Byte Sel" SID "704" Ports [2, 1] Position [1085, 566, 1135, 704] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Byte Sel" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "64b" SID "705" Position [485, 313, 515, 327] IconDisplay "Port number" } Block { BlockType Inport Name "B Sel" SID "706" Position [485, 273, 515, 287] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "B0" SID "707" Ports [1, 1] Position [595, 311, 635, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B1" SID "708" Ports [1, 1] Position [595, 351, 635, 369] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B2" SID "709" Ports [1, 1] Position [595, 391, 635, 409] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B3" SID "710" Ports [1, 1] Position [595, 431, 635, 449] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B4" SID "711" Ports [1, 1] Position [595, 471, 635, 489] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "32" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B5" SID "712" Ports [1, 1] Position [595, 511, 635, 529] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "40" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B6" SID "713" Ports [1, 1] Position [595, 551, 635, 569] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "48" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B7" SID "714" Ports [1, 1] Position [595, 591, 635, 609] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "56" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "715" Ports [9, 1] Position [695, 257, 730, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,366,9,1,white,blue,3,9717d9a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 52.2857 313.714 366 0 " "],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 52.2857 313.714 366 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 1" "0.875 5.875 ],[188.55 188.55 193.55 188.55 193.55 193.55 193.55 188.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.8" "75 10.875 ],[183.55 183.55 188.55 188.55 183.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ]," "[178.55 178.55 183.55 183.55 178.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[173.55 173.5" "5 178.55 173.55 178.55 178.55 173.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprint" "f('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input" "',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black" "');port_label('input',5,'d3');\ncolor('black');port_label('input',6,'d4');\ncolor('black');port_label('input',7," "'d5');\ncolor('black');port_label('input',8,'d6');\ncolor('black');port_label('input',9,'d7');\n\ncolor('black')" ";disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "B" SID "716" Position [795, 433, 825, 447] IconDisplay "Port number" } Line { SrcBlock "Mux" SrcPort 1 DstBlock "B" DstPort 1 } Line { SrcBlock "B Sel" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "64b" SrcPort 1 Points [15, 0] Branch { Points [0, 40] Branch { Points [0, 40] Branch { DstBlock "B2" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "B3" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "B4" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "B5" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "B6" DstPort 1 } Branch { Points [0, 40] DstBlock "B7" DstPort 1 } } } } } } Branch { DstBlock "B1" DstPort 1 } } Branch { DstBlock "B0" DstPort 1 } } Line { SrcBlock "B3" SrcPort 1 DstBlock "Mux" DstPort 5 } Line { SrcBlock "B2" SrcPort 1 DstBlock "Mux" DstPort 4 } Line { SrcBlock "B1" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "B0" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "B4" SrcPort 1 DstBlock "Mux" DstPort 6 } Line { SrcBlock "B5" SrcPort 1 DstBlock "Mux" DstPort 7 } Line { SrcBlock "B6" SrcPort 1 DstBlock "Mux" DstPort 8 } Line { SrcBlock "B7" SrcPort 1 DstBlock "Mux" DstPort 9 } } } Block { BlockType Reference Name "Delay4" SID "717" Ports [1, 1] Position [915, 656, 945, 684] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "2330" Ports [1] Position [630, 468, 720, 492] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From" SID "718" Position [560, 543, 730, 567] ZOrder -9 ShowName off GotoTag "Tx_PKT_BUF_SEL" TagVisibility "global" } Block { BlockType From Name "From1" SID "719" Position [270, 588, 440, 612] ZOrder -9 ShowName off GotoTag "regTx_Pkt_Buf_Addr_Offset" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out3" SID "2331" Ports [1, 1] Position [545, 474, 575, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "N MSB" SID "720" Ports [1, 1] Position [595, 620, 640, 640] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "ceil(log2(MAX_NUM_BYTES))-3" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2.02" sg_icon_stat "45,20,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('ou" "tput',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "3586" Ports [1, 1] Position [1185, 617, 1220, 653] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType Outport Name "RAM Byte" SID "721" Position [1285, 628, 1315, 642] ZOrder -9 IconDisplay "Port number" } Line { SrcBlock "BRAM Addr Map" SrcPort 1 Points [35, 0] Branch { DstBlock "N MSB" DstPort 1 } Branch { Points [0, 40] DstBlock "3 LSB" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 Points [50, 0; 0, 30] DstBlock "BRAM Interface" DstPort 1 } Line { SrcBlock "N MSB" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 Points [70, 0] Branch { DstBlock "AddSub" DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Byte Addr" SrcPort 1 DstBlock "12 LSB" DstPort 1 } Line { Labels [0, 0] SrcBlock "AddSub" SrcPort 1 DstBlock "BRAM Interface" DstPort 2 } Line { SrcBlock "BRAM Interface" SrcPort 1 DstBlock "Byte Sel" DstPort 1 } Line { SrcBlock "3 LSB" SrcPort 1 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "Byte Sel" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "12 LSB" SrcPort 1 DstBlock "BRAM Addr Map" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Byte Sel" DstPort 2 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "RAM Byte" DstPort 1 } Annotation { Name "BRAM_Addr is a UFix32_0 value interpretted as a byte address by\nthe BRAM block. The BRAM is a 64-bit me" "mory and requires BRAM_Addr\nto be aligned for 64-bit accesses. Thus the 3LSB of the BRAM_Addr\nsignal must always" " be 0.\n\nIn the current ref design the Tx Pkt Buf BRAM is 32KB (2^15 bytes),\ndivided into 8 4KB packet buffers.\n" "\nThe Tx PHY Byte Address is 12 bits (4KB addressable). The 3 LSB are\ntrimmed to construct the 64-bit-word addres" "s.\n\nThe Tx_PKT_BUF_SEL signal is 4 bits, but only takes values 0:7.\n\nPkt_Buf_Addr_Offset is a software-program" "med value which defines\nthe \"0\" address in the BRAM from the PHY's perspective. This offset\nallows software to" " store meta data in the pkt buffer before the actual pkt\npayload. The PHY's zero-address starts at that offset." Position [860, 401] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Bit Select" SID "722" Ports [2, 1] Position [1205, 428, 1270, 472] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Bit Select" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "b Sel" SID "723" Position [25, 53, 55, 67] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "724" Position [25, 88, 55, 102] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Mux" SID "725" Ports [9, 1] Position [260, 40, 290, 360] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,320,9,1,white,blue,3,9717d9a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 45.7143 274.286 320 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 45.7143 274.286 320 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1" " 6.1 ],[164.44 164.44 168.44 164.44 168.44 168.44 168.44 164.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[" "160.44 160.44 164.44 164.44 160.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[156.44 156.44 160." "44 160.44 156.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[152.44 152.44 156.44 152.44 156.44 " "156.44 152.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon" " text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3')" ";\ncolor('black');port_label('input',6,'d4');\ncolor('black');port_label('input',7,'d5');\ncolor('black');port_lab" "el('input',8,'d6');\ncolor('black');port_label('input',9,'d7');\n\ncolor('black');disp('\\bf{}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "726" Ports [1, 1] Position [160, 86, 200, 104] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "727" Ports [1, 1] Position [160, 121, 200, 139] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "728" Ports [1, 1] Position [160, 156, 200, 174] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "729" Ports [1, 1] Position [160, 191, 200, 209] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "730" Ports [1, 1] Position [160, 226, 200, 244] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "731" Ports [1, 1] Position [160, 261, 200, 279] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "732" Ports [1, 1] Position [160, 296, 200, 314] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "733" Ports [1, 1] Position [160, 331, 200, 349] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "b" SID "734" Position [360, 193, 390, 207] IconDisplay "Port number" } Line { SrcBlock "Mux" SrcPort 1 DstBlock "b" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [70, 0] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] DstBlock "b7" DstPort 1 } Branch { DstBlock "b6" DstPort 1 } } Branch { DstBlock "b5" DstPort 1 } } Branch { DstBlock "b4" DstPort 1 } } Branch { DstBlock "b3" DstPort 1 } } Branch { DstBlock "b2" DstPort 1 } } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Mux" DstPort 4 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Mux" DstPort 5 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Mux" DstPort 6 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Mux" DstPort 7 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Mux" DstPort 8 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Mux" DstPort 9 } Line { SrcBlock "b Sel" SrcPort 1 DstBlock "Mux" DstPort 1 } } } Block { BlockType SubSystem Name "Byte Src Sel" SID "735" Ports [6, 1] Position [1015, 409, 1130, 506] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Byte Src Sel" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Sel Zero" SID "736" Position [385, 288, 415, 302] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Sel FCS" SID "737" Position [385, 358, 415, 372] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Sel HTSIG " SID "2709" Position [385, 338, 415, 352] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Data B" SID "738" Position [500, 383, 530, 397] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "FCS B" SID "739" Position [500, 418, 530, 432] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "HTSIG" SID "2710" Position [500, 453, 530, 467] Port "6" IconDisplay "Port number" } Block { BlockType Scope Name "Byte Select" SID "2512" Ports [7] Position [1305, 602, 1355, 758] ZOrder -3 Floating off Location [6, 40, 2477, 1594] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } YMin "-5~-5~-5~-5~-5~-5~-5" YMax "5~5~5~5~5~5~5" SaveName "ScopeData7" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Concat" SID "740" Ports [2, 1] Position [605, 336, 640, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "741" Ports [0, 1] Position [835, 469, 860, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "2747" Ports [0, 1] Position [625, 484, 650, 506] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "2514" Ports [1, 1] Position [1135, 634, 1165, 646] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sel FCS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "2515" Ports [1, 1] Position [1135, 674, 1165, 686] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Data Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "2516" Ports [1, 1] Position [1135, 694, 1165, 706] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FCS Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "2748" Ports [1, 1] Position [1135, 654, 1165, 666] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sel HTSIG" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "2749" Ports [1, 1] Position [1135, 714, 1165, 726] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "HTSIG Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "2831" Ports [1, 1] Position [1135, 734, 1165, 746] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Tx Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "2513" Ports [1, 1] Position [1135, 614, 1165, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sel Zero" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Mux" SID "742" Ports [5, 1] Position [710, 342, 745, 508] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,166,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 23.7143 142.286 166 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 23.7143 142.286 166 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[88.55 88.55 93.55 88.55 93.55 93.55 93.55 88.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[83." "55 83.55 88.55 88.55 83.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[78.55 78.55 83.55 83.5" "5 78.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[73.55 73.55 78.55 73.55 78.55 78.55 73.55 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('in" "put',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\ncolor('bl" "ack');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "2746" Ports [3, 1] Position [920, 342, 955, 508] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,166,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 23.7143 142.286 166 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 23.7143 142.286 166 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 " "5.875 ],[88.55 88.55 93.55 88.55 93.55 93.55 93.55 88.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[83." "55 83.55 88.55 88.55 83.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[78.55 78.55 83.55 83.5" "5 78.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[73.55 73.55 78.55 73.55 78.55 78.55 73.55 " "],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('in" "put',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "3596" Ports [1, 1] Position [1035, 407, 1070, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType Outport Name "Tx Byte" SID "743" Position [1135, 418, 1165, 432] IconDisplay "Port number" } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Sel FCS" SrcPort 1 Points [35, 0] Branch { DstBlock "Concat" DstPort 2 } Branch { Points [0, 275] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Data B" SrcPort 1 Points [40, 0] Branch { DstBlock "Mux" DstPort 2 } Branch { Points [0, 290] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Sel HTSIG " SrcPort 1 Points [30, 0] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, 315] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "FCS B" SrcPort 1 Points [35, 0] Branch { DstBlock "Mux" DstPort 3 } Branch { Points [0, 275] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { Name "Sel Zero" Labels [1, 1] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Byte Select" DstPort 1 } Line { Name "Sel FCS" Labels [1, 1] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Byte Select" DstPort 2 } Line { Name "Data Byte" Labels [-1, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Byte Select" DstPort 4 } Line { Name "FCS Byte" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Byte Select" DstPort 5 } Line { SrcBlock "Sel Zero" SrcPort 1 Points [40, 0] Branch { Points [350, 0; 0, 75] DstBlock "Mux1" DstPort 1 } Branch { Points [0, 325] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 Points [40, 0] Branch { Points [0, 315] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "HTSIG" SrcPort 1 Points [30, 0] Branch { DstBlock "Mux" DstPort 4 } Branch { Points [0, 260] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux" DstPort 5 } Line { Name "Sel HTSIG" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Byte Select" DstPort 3 } Line { Name "HTSIG Byte" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Byte Select" DstPort 6 } Line { Name "Tx Byte" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Byte Select" DstPort 7 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Tx Byte" DstPort 1 } } } Block { BlockType Reference Name "Delay1" SID "744" Ports [1, 1] Position [630, 516, 660, 544] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay10" SID "2836" Ports [1, 1] Position [850, 436, 880, 464] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay11" SID "3587" Ports [1, 1] Position [630, 216, 660, 244] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay12" SID "3588" Ports [1, 1] Position [1055, 216, 1085, 244] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay13" SID "3589" Ports [1, 1] Position [1055, 271, 1085, 299] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay14" SID "3590" Ports [1, 1] Position [1055, 326, 1085, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay15" SID "3591" Ports [1, 1] Position [1055, 351, 1085, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay16" SID "3592" Ports [1, 1] Position [1065, 656, 1095, 684] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay17" SID "3593" Ports [1, 1] Position [1065, 686, 1095, 714] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay18" SID "3595" Ports [1, 1] Position [1065, 746, 1095, 774] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay19" SID "3597" Ports [1, 1] Position [590, 401, 620, 429] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "745" Ports [1, 1] Position [630, 271, 660, 299] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay20" SID "3598" Ports [1, 1] Position [630, 416, 660, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "746" Ports [1, 1] Position [630, 561, 660, 589] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "747" Ports [1, 1] Position [630, 351, 660, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "748" Ports [1, 1] Position [630, 326, 660, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "749" Ports [1, 1] Position [630, 386, 660, 414] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay7" SID "750" Ports [1, 1] Position [850, 421, 880, 449] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay8" SID "751" Ports [1, 1] Position [630, 746, 660, 774] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay9" SID "752" Ports [1, 1] Position [630, 686, 660, 714] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "FCS Calc" SID "753" Ports [4, 1] Position [810, 490, 925, 555] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FCS Calc" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "FCS Sel" SID "754" Position [565, 758, 595, 772] IconDisplay "Port number" } Block { BlockType Inport Name "Byte" SID "755" Position [730, 503, 760, 517] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Byte Ind" SID "756" Position [260, 543, 290, 557] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Byte Valid" SID "757" Position [260, 513, 290, 527] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "2LSB" SID "2838" Ports [1, 1] Position [855, 719, 890, 731] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.931 0.946 0.973 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub" SID "2840" Ports [2, 1] Position [1075, 735, 1120, 775] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "2" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,40,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 40 40 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[25.55 25.55 3" "0.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[20.55 20.55 25.55 25.55 " "20.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_la" "bel('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}'" ",'texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Byte Sel" SID "760" Ports [2, 1] Position [1360, 630, 1410, 705] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Byte Sel" Location [380, 118, 2362, 1458] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" SID "761" Position [435, 313, 465, 327] IconDisplay "Port number" } Block { BlockType Inport Name "B Sel" SID "762" Position [520, 273, 550, 287] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "B0" SID "763" Ports [1, 1] Position [600, 431, 640, 449] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B1" SID "764" Ports [1, 1] Position [600, 391, 640, 409] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B2" SID "765" Ports [1, 1] Position [600, 351, 640, 369] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B3" SID "766" Ports [1, 1] Position [600, 311, 640, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "2837" Ports [0, 1] Position [425, 387, 480, 413] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "hex2dec('87654321') %hex2dec('FF00FF00') %" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,5b6545ec,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.33 13." "33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.33 13.3" "3 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('output',1,'2271560481');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "767" Ports [5, 1] Position [690, 261, 725, 459] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,198,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 28.2857 169.714 198 0 " "],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 28.2857 169.714 198 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 1" "0.875 5.875 ],[104.55 104.55 109.55 104.55 109.55 109.55 109.55 104.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.8" "75 10.875 ],[99.55 99.55 104.55 104.55 99.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[94" ".55 94.55 99.55 99.55 94.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[89.55 89.55 94.55 89" ".55 94.55 94.55 89.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: " "begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('" "input',5,'d3');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "B" SID "768" Position [800, 353, 830, 367] IconDisplay "Port number" } Line { SrcBlock "Mux" SrcPort 1 DstBlock "B" DstPort 1 } Line { SrcBlock "B Sel" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "32b" SrcPort 1 Points [100, 0] Branch { Points [0, 40] Branch { Points [0, 40] Branch { Points [0, 40] DstBlock "B0" DstPort 1 } Branch { DstBlock "B1" DstPort 1 } } Branch { DstBlock "B2" DstPort 1 } } Branch { DstBlock "B3" DstPort 1 } } Line { SrcBlock "B0" SrcPort 1 DstBlock "Mux" DstPort 5 } Line { SrcBlock "B1" SrcPort 1 DstBlock "Mux" DstPort 4 } Line { SrcBlock "B2" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "B3" SrcPort 1 DstBlock "Mux" DstPort 2 } } } Block { BlockType SubSystem Name "CRC32 Calc" SID "769" Ports [2, 1] Position [855, 485, 995, 580] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CRC32 Calc" Location [490, 314, 1955, 1081] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "byte" SID "770" Position [25, 283, 55, 297] IconDisplay "Port number" } Block { BlockType Inport Name "en" SID "771" Position [520, 358, 550, 372] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "24LSB" SID "772" Ports [1, 1] Position [420, 81, 465, 109] BlockMirror on LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

H" "ardware notes: In hardware this block costs nothing." nbits "24" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,28,1,1,white,blue,0,1fd851a7,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 28 28 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[18.44 18" ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[14.44 14.44 18.44 18." "44 14.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]" ");\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_l" "abel('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "8MSB" SID "773" Ports [1, 1] Position [420, 26, 465, 54] BlockMirror on LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

H" "ardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,28,1,1,white,blue,0,1fd851a7,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 28 28 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[18.44 18" ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[14.44 14.44 18.44 18." "44 14.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]" ");\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_l" "abel('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert" SID "774" Ports [1, 1] Position [1310, 329, 1355, 351] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware th" "is block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "45,22,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "775" Ports [1, 1] Position [770, 273, 805, 287] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware th" "is block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,423" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,14,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('Ass" "ert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B0" SID "776" Ports [1, 1] Position [1010, 271, 1050, 289] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B1" SID "777" Ports [1, 1] Position [1010, 311, 1050, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B2" SID "778" Ports [1, 1] Position [1010, 351, 1050, 369] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "B3" SID "779" Ports [1, 1] Position [1010, 391, 1050, 409] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "CRC Remainders1" SID "780" Ports [1, 1] Position [400, 244, 450, 296] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "256" initVector "CRC_Table32" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,52,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 52 52 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 52 52 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "781" Ports [4, 1] Position [1225, 255, 1250, 425] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "4" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,170,4,1,white,blue,0,47d3d416,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 170 170 0 ],[0.77 0." "82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 170 170 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[88" ".33 88.33 91.33 88.33 91.33 91.33 91.33 88.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[85.33 85.33 8" "8.33 88.33 85.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[82.33 82.33 85.33 85.33 82.33 " "],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[79.33 79.33 82.33 79.33 82.33 82.33 79.33 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'hi');\n\n\ncolor('black');port_label('input',4,'lo');\n\ncolor('black');disp('\\fo" "ntsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat1" SID "782" Ports [2, 1] Position [415, 125, 465, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,55,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 55 55 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 55 55 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[34.7" "7 34.77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[27.77 27.77 " "34.77 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[20.77 20.77 27.77 27.77 20." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\" "fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "783" Ports [0, 1] Position [350, 152, 375, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 " "16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Endian Swap" SID "784" Ports [1, 1] Position [115, 273, 175, 307] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "785" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "786" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "787" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "788" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "789" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "790" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "791" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "792" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "793" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "794" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "795" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] DstBlock "b7" DstPort 1 } Branch { DstBlock "b6" DstPort 1 } } Branch { DstBlock "b5" DstPort 1 } } Branch { DstBlock "b4" DstPort 1 } } Branch { DstBlock "b3" DstPort 1 } } Branch { DstBlock "b2" DstPort 1 } } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType SubSystem Name "Endian Swap1" SID "796" Ports [1, 1] Position [1120, 263, 1180, 297] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap1" Location [-1678, 70, -2, 1030] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "797" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "798" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "799" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "800" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "801" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "802" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "803" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "804" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "805" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "806" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "807" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b3" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b4" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b5" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b6" DstPort 1 } Branch { Points [0, 35] DstBlock "b7" DstPort 1 } } } } } } } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } } } Block { BlockType SubSystem Name "Endian Swap2" SID "808" Ports [1, 1] Position [1120, 303, 1180, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap2" Location [-1678, 70, -2, 1030] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "809" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "810" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "811" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "812" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "813" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "814" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "815" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "816" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "817" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "818" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "819" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] DstBlock "b7" DstPort 1 } Branch { DstBlock "b6" DstPort 1 } } Branch { DstBlock "b5" DstPort 1 } } Branch { DstBlock "b4" DstPort 1 } } Branch { DstBlock "b3" DstPort 1 } } Branch { DstBlock "b2" DstPort 1 } } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType SubSystem Name "Endian Swap3" SID "820" Ports [1, 1] Position [1120, 343, 1180, 377] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap3" Location [-1678, 70, -2, 1030] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "821" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "822" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "823" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "824" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "825" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "826" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "827" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "828" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "829" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "830" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "831" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b3" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b4" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b5" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b6" DstPort 1 } Branch { Points [0, 35] DstBlock "b7" DstPort 1 } } } } } } } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } } } Block { BlockType SubSystem Name "Endian Swap4" SID "832" Ports [1, 1] Position [1120, 383, 1180, 417] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap4" Location [-1678, 70, -2, 1030] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "833" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "834" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "835" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "836" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "837" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "838" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "839" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "840" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "841" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "842" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "843" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] DstBlock "b7" DstPort 1 } Branch { DstBlock "b6" DstPort 1 } } Branch { DstBlock "b5" DstPort 1 } } Branch { DstBlock "b4" DstPort 1 } } Branch { DstBlock "b3" DstPort 1 } } Branch { DstBlock "b2" DstPort 1 } } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType From Name "From" SID "844" Position [485, 329, 580, 351] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "845" Ports [1, 1] Position [875, 271, 905, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "846" Ports [2, 1] Position [270, 230, 315, 310] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,80,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 80 80 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 80 80 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[46.66 4" "6.66 52.66 46.66 52.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 " "46.66 40.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[34.66 34.66 40.66 40.66 34.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[28.66 28.66 34.66 28.66 34.66 34.66 28.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "847" Ports [2, 1] Position [530, 232, 575, 283] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,51,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 51 51 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31.66 3" "1.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 31.66 " "31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "crc_accum" SID "848" Ports [3, 1] Position [665, 253, 710, 307] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('FFFFFFFF')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,54,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 54 54 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 54 54 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[33.66 3" "3.66 39.66 33.66 39.66 39.66 39.66 33.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[27.66 27.66 33.66 " "33.66 27.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[21.66 21.66 27.66 27.66 21.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[15.66 15.66 21.66 15.66 21.66 21.66 15.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "CRC32" SID "849" Position [1410, 333, 1440, 347] IconDisplay "Port number" } Line { SrcBlock "Inverter" SrcPort 1 Points [15, 0] Branch { DstBlock "B0" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "B1" DstPort 1 } Branch { Points [0, 40] Branch { Points [0, 40] DstBlock "B3" DstPort 1 } Branch { DstBlock "B2" DstPort 1 } } } } Line { SrcBlock "Endian Swap4" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "Endian Swap3" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "Endian Swap2" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Endian Swap1" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Endian Swap" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Assert" DstPort 1 } Line { SrcBlock "B3" SrcPort 1 DstBlock "Endian Swap4" DstPort 1 } Line { SrcBlock "B2" SrcPort 1 DstBlock "Endian Swap3" DstPort 1 } Line { SrcBlock "B1" SrcPort 1 DstBlock "Endian Swap2" DstPort 1 } Line { SrcBlock "B0" SrcPort 1 DstBlock "Endian Swap1" DstPort 1 } Line { SrcBlock "byte" SrcPort 1 DstBlock "Endian Swap" DstPort 1 } Line { SrcBlock "8MSB" SrcPort 1 Points [-260, 0; 0, 210] DstBlock "Logical3" DstPort 1 } Line { SrcBlock "24LSB" SrcPort 1 Points [-45, 0; 0, 45] DstBlock "Concat1" DstPort 1 } Line { SrcBlock "From" SrcPort 1 Points [25, 0; 0, -60] DstBlock "crc_accum" DstPort 2 } Line { SrcBlock "Assert1" SrcPort 1 Points [25, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -185; -330, 0] Branch { Points [0, -55] DstBlock "8MSB" DstPort 1 } Branch { DstBlock "24LSB" DstPort 1 } } } Line { SrcBlock "crc_accum" SrcPort 1 DstBlock "Assert1" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "crc_accum" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Concat1" SrcPort 1 Points [35, 0; 0, 90] DstBlock "Logical4" DstPort 1 } Line { SrcBlock "CRC Remainders1" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "CRC Remainders1" DstPort 1 } Line { SrcBlock "Assert" SrcPort 1 DstBlock "CRC32" DstPort 1 } Line { SrcBlock "en" SrcPort 1 Points [85, 0; 0, -65] DstBlock "crc_accum" DstPort 3 } } } Block { BlockType Reference Name "Constant2" SID "850" Ports [0, 1] Position [335, 559, 360, 581] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "851" Ports [0, 1] Position [335, 694, 360, 716] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "11" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,997df0ab,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'11');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "FCS Calc" SID "2342" Ports [7] Position [1615, 351, 1650, 479] ZOrder -3 Floating off Location [6, 40, 2477, 1594] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "12000" YMin "0~0~0~0~0~0~-1" YMax "70~1~1~1~3~300~1" SaveName "ScopeData5" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType From Name "From1" SID "2848" Position [735, 734, 830, 756] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType From Name "From2" SID "852" Position [225, 471, 405, 489] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11ag" TagVisibility "global" } Block { BlockType From Name "From3" SID "853" Position [225, 606, 405, 624] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "2340" Ports [1, 1] Position [1450, 369, 1480, 381] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Byte Ind Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "2343" Ports [1, 1] Position [1450, 389, 1480, 401] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FCS Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "2341" Ports [1, 1] Position [1450, 349, 1480, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Byte Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "2344" Ports [1, 1] Position [1450, 409, 1480, 421] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "CRC32 En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "2345" Ports [1, 1] Position [1450, 429, 1480, 441] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FCS B Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "2518" Ports [1, 1] Position [1450, 449, 1480, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FCS Byte" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "2353" Ports [1, 1] Position [660, 610, 695, 630] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "854" Ports [2, 1] Position [665, 497, 690, 593] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,96,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 96 96 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 96 96 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[51.33 51.33 " "54.33 51.33 54.33 54.33 54.33 51.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[48.33 48.33 51.33 51.33 4" "8.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[45.33 45.33 48.33 48.33 45.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[42.33 42.33 45.33 42.33 45.33 45.33 42.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "855" Ports [3, 1] Position [550, 463, 575, 577] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,114,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 114 114 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 25 25 0 0 ],[0 0 114 114 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[60.33 60" ".33 63.33 60.33 63.33 63.33 63.33 60.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[57.33 57.33 60.33 60." "33 57.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[54.33 54.33 57.33 57.33 54.33 ],[1 1 1 ]" ");\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[51.33 51.33 54.33 51.33 54.33 54.33 51.33 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black'" ");disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "2352" Ports [2, 1] Position [760, 538, 800, 567] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 29 29 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[18.44 18.44 22" ".44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[14.44 14.44 18.44 18.44 14.44" " ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch(" "[15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "856" Ports [3, 1] Position [550, 598, 575, 712] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,114,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 114 114 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 25 25 0 0 ],[0 0 114 114 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[60.33 60" ".33 63.33 60.33 63.33 63.33 63.33 60.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[57.33 57.33 60.33 60." "33 57.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[54.33 54.33 57.33 57.33 54.33 ],[1 1 1 ]" ");\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[51.33 51.33 54.33 51.33 54.33 54.33 51.33 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black'" ");disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "2841" Ports [3, 1] Position [945, 713, 995, 777] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "50,64,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 64 64 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 64 64 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[39.77 39.7" "7 46.77 39.77 46.77 46.77 46.77 39.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[32.77 32.77 39.77 39" ".77 32.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[25.77 25.77 32.77 32.77 25.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[18.77 18.77 25.77 18.77 25.77 25.77 18.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en')" ";\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT:" " end icon text');" } Block { BlockType Reference Name "Relational1" SID "865" Ports [2, 1] Position [445, 675, 480, 715] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','te" "xmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "866" Ports [2, 1] Position [445, 540, 480, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25.55 30." "55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 25.55 20." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','te" "xmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "posedge" SID "2842" Ports [1, 1] Position [800, 758, 845, 772] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "posedge" Location [380, 118, 2362, 1458] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "2843" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "2844" Ports [1, 1] Position [425, 178, 460, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "2845" Ports [1, 1] Position [490, 181, 515, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2846" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2847" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -25] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "CRC Byte" SID "867" Position [1530, 663, 1560, 677] IconDisplay "Port number" } Line { SrcBlock "Byte Sel" SrcPort 1 Points [20, 0] Branch { DstBlock "CRC Byte" DstPort 1 } Branch { DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Byte" SrcPort 1 DstBlock "CRC32 Calc" DstPort 1 } Line { SrcBlock "CRC32 Calc" SrcPort 1 Points [305, 0; 0, 115] DstBlock "Byte Sel" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical2" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Byte Ind" SrcPort 1 Points [125, 0] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, -195] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [0, 135] Branch { Points [0, 0] DstBlock "Relational1" DstPort 1 } Branch { Points [0, 40] DstBlock "2LSB" DstPort 1 } } } Line { Labels [0, 0] SrcBlock "Byte Valid" SrcPort 1 Points [130, 0] Branch { Points [75, 0] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, 135] DstBlock "Logical5" DstPort 2 } } Branch { Points [0, -145] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical5" DstPort 3 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical5" SrcPort 1 Points [15, 0; 0, -85] DstBlock "Logical1" DstPort 2 } Line { Name "Byte Ind Valid" Labels [-1, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FCS Calc" DstPort 2 } Line { Name "Byte Ind" Labels [-1, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FCS Calc" DstPort 1 } Line { Name "FCS Sel" Labels [1, 1] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FCS Calc" DstPort 3 } Line { Name "CRC32 En" Labels [1, 1] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FCS Calc" DstPort 4 } Line { Name "FCS B Sel" Labels [1, 1] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "FCS Calc" DstPort 5 } Line { SrcBlock "Logical3" SrcPort 1 Points [15, 0] Branch { DstBlock "CRC32 Calc" DstPort 2 } Branch { Points [0, -140] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 Points [120, 0; 0, -70] Branch { Points [0, -250] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Byte Sel" DstPort 2 } } Line { Name "FCS Byte" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FCS Calc" DstPort 6 } Line { SrcBlock "FCS Sel" SrcPort 1 Points [20, 0] Branch { Points [0, -145] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -225] DstBlock "Gateway Out2" DstPort 1 } } Branch { DstBlock "posedge" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [20, 0; 0, -60] DstBlock "Logical3" DstPort 2 } Line { SrcBlock "2LSB" SrcPort 1 Points [20, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 85; 130, 0; 0, -45] DstBlock "AddSub" DstPort 2 } } Line { SrcBlock "posedge" SrcPort 1 DstBlock "Register" DstPort 3 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "AddSub" DstPort 1 } Annotation { Name "FCS covers bytes starting with first MAC payload byte.\nFor 11ag FCS starts after SIGNAL (3B) and SERVIC" "E (2B).\nFor 11n FCS starts after L-SIG (3B), HT-SIG (6B) and SERVICE (2B)." Position [186, 763] HorizontalAlignment "left" } Annotation { Name "Checksum bytes must be output [0,1,2,3], even when they're\nnot aligned to a 32-bit boundary in the actu" "al payload. The \nCRC bytes are selected [0,1,2,3] here, adjusting the 2 LSB\nof the actual byte index to count fr" "om 0 during the FCS output." Position [917, 848] HorizontalAlignment "left" } Annotation { Name "Don't udpate CRC state while checksum\nis being read by Tx pipeline" Position [706, 795] } } } Block { BlockType Reference Name "Gateway Out1" SID "2832" Ports [1, 1] Position [1355, 454, 1385, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out10" SID "2580" Ports [1, 1] Position [1650, 189, 1680, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Tx Bit tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "2581" Ports [1, 1] Position [1650, 204, 1680, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sym Cfg out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "2833" Ports [1, 1] Position [1355, 489, 1385, 501] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out4" SID "2576" Ports [1, 1] Position [1650, 129, 1680, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Byte Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "2326" Ports [1, 1] Position [1220, 629, 1250, 641] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "2328" Ports [1, 1] Position [1220, 664, 1250, 676] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "2577" Ports [1, 1] Position [1650, 144, 1680, 156] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Bit Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "2578" Ports [1, 1] Position [1650, 159, 1680, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Bit Sel valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "2579" Ports [1, 1] Position [1650, 174, 1680, 186] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Tx Bit tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "873" Position [980, 631, 1140, 649] ZOrder -10 ShowName off GotoTag "TX_SIG_DECODE_ERROR" TagVisibility "global" } Block { BlockType SubSystem Name "Packet Sections" SID "875" Ports [2, 5] Position [400, 375, 510, 455] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Packet Sections" Location [-1678, 227, -18, 1171] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "Bit sel" SID "876" Position [500, 208, 530, 222] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Byte Ind" SID "877" Position [500, 257, 530, 273] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "878" Ports [2, 1] Position [530, 489, 575, 531] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,42,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texmode" "','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "879" Ports [2, 1] Position [670, 744, 715, 786] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,42,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode" "','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub3" SID "880" Ports [2, 1] Position [455, 449, 500, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_BYTES))" bin_pt "0" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,42,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texmode" "','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "881" Ports [0, 1] Position [275, 379, 305, 401] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "882" Ports [0, 1] Position [275, 419, 305, 441] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "9" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,350ae870,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'9');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "883" Ports [0, 1] Position [520, 764, 550, 786] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "884" Ports [0, 1] Position [685, 459, 715, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "885" Ports [0, 1] Position [370, 469, 400, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "2726" Ports [0, 1] Position [740, 839, 770, 861] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "9" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,350ae870,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'9');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "2728" Ports [0, 1] Position [740, 874, 770, 896] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "DATA Sections" SID "886" Ports [7] Position [1430, 103, 1475, 217] ZOrder -3 Floating off Location [147, 298, 2411, 1521] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } YMin "-5~-5~-5~-5~-5~-5~-5" YMax "5~5~5~5~5~5~5" SaveName "ScopeData1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Display Name "Display" SID "887" Ports [1] Position [425, 565, 515, 595] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "888" Position [155, 510, 320, 530] ZOrder -9 ShowName off GotoTag "OFDM_TX_DATA_LENGTH" TagVisibility "global" } Block { BlockType From Name "From2" SID "2724" Position [685, 807, 860, 823] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType From Name "From7" SID "889" Position [150, 342, 325, 358] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "2334" Ports [1, 1] Position [1300, 124, 1330, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Bit Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "2335" Ports [1, 1] Position [1300, 139, 1330, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Unscrambled" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "893" Ports [1, 1] Position [1300, 109, 1330, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Byte Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "894" Ports [1, 1] Position [355, 574, 385, 586] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out5" SID "2336" Ports [1, 1] Position [1300, 154, 1330, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sel Zero" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "2337" Ports [1, 1] Position [1300, 169, 1330, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Sel FCS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "2338" Ports [1, 1] Position [1300, 184, 1330, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "DATA Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "897" Ports [1, 1] Position [865, 682, 895, 698] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "898" Ports [1, 1] Position [865, 552, 895, 568] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "899" Ports [2, 1] Position [950, 363, 980, 427] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,64,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 64 64 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 64 64 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[36.44 36.44 40.4" "4 36.44 40.44 40.44 40.44 36.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[32.44 32.44 36.44 36.44 32.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[28.44 28.44 32.44 32.44 28.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[24.44 24.44 28.44 24.44 28.44 28.44 24.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "900" Ports [2, 1] Position [950, 671, 975, 749] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,78,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 78 78 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 78 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[42.33 42.33 " "45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[39.33 39.33 42.33 42.33 3" "9.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 36.33 39.33 39.33 36.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.33 36.33 36.33 33.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "901" Ports [2, 1] Position [950, 541, 975, 619] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,78,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 78 78 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 78 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[42.33 42.33 " "45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[39.33 39.33 42.33 42.33 3" "9.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 36.33 39.33 39.33 36.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.33 36.33 36.33 33.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "902" Ports [2, 1] Position [850, 441, 875, 519] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,78,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 78 78 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 78 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[42.33 42.33 " "45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[39.33 39.33 42.33 42.33 3" "9.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 36.33 39.33 39.33 36.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.33 36.33 36.33 33.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('and');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TAIL" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Logical5" SID "2723" Ports [3, 1] Position [960, 801, 985, 879] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,78,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 78 78 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 78 78 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[42.33 42.33 " "45.33 42.33 45.33 45.33 45.33 42.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[39.33 39.33 42.33 42.33 3" "9.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[36.33 36.33 39.33 39.33 36.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[33.33 33.33 36.33 33.33 36.33 36.33 33.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');di" "sp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux8" SID "903" Ports [3, 1] Position [370, 329, 395, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,122,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 17.4286 104.571 122 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 17.4286 104.571 122 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[64.33 64.33 67.33 64.33 67.33 67.33 67.33 64.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "1.33 61.33 64.33 64.33 61.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[58.33 58.33 61.33 61" ".33 58.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[55.33 55.33 58.33 55.33 58.33 58.33 55." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "904" Ports [2, 1] Position [770, 711, 805, 749] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmod" "e','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "905" Ports [2, 1] Position [700, 361, 735, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmod" "e','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "PAD" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Relational5" SID "907" Ports [2, 1] Position [770, 481, 805, 519] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode','" "on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "908" Ports [2, 1] Position [770, 441, 805, 479] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmod" "e','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Unscrambled" SID "909" Position [1065, 388, 1095, 402] IconDisplay "Port number" } Block { BlockType Outport Name "Sel Zero" SID "910" Position [1065, 638, 1095, 652] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Sel FCS" SID "911" Position [1065, 703, 1095, 717] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Sel HTSIG" SID "2722" Position [1065, 833, 1095, 847] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "DATA Done" SID "912" Position [1065, 573, 1095, 587] Port "5" IconDisplay "Port number" } Line { SrcBlock "Mux8" SrcPort 1 Points [20, 0] Branch { DstBlock "Relational2" DstPort 2 } Branch { Points [0, 70] DstBlock "AddSub3" DstPort 1 } } Line { Name "SIG/HTSIG" Labels [1, 1] SrcBlock "Relational2" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 Points [25, 0] Branch { DstBlock "Unscrambled" DstPort 1 } Branch { Points [0, -250] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [15, 0] Branch { DstBlock "AddSub1" DstPort 2 } Branch { DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "From7" SrcPort 1 DstBlock "Mux8" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux8" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux8" DstPort 3 } Line { SrcBlock "AddSub1" SrcPort 1 Points [5, 0] Branch { DstBlock "Relational5" DstPort 2 } Branch { Points [0, 145] Branch { DstBlock "Relational4" DstPort 2 } Branch { Points [0, 100] DstBlock "AddSub2" DstPort 1 } } } Line { Name "PAD" Labels [0, 0] SrcBlock "Relational4" SrcPort 1 Points [35, 0] Branch { Points [0, 45] DstBlock "Inverter" DstPort 1 } Branch { Points [175, 0] Branch { DstBlock "Sel Zero" DstPort 1 } Branch { Points [0, -485] DstBlock "Gateway Out5" DstPort 1 } } } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational6" DstPort 2 } Line { Name "TAIL" Labels [0, 0] SrcBlock "Logical4" SrcPort 1 Points [35, 0; 0, -70] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Relational6" SrcPort 1 Points [15, 0] Branch { DstBlock "Logical4" DstPort 1 } Branch { Points [0, 100] DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Relational5" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical4" DstPort 2 } Branch { Points [0, 100] DstBlock "Logical3" DstPort 2 } } Line { SrcBlock "Byte Ind" SrcPort 1 Points [55, 0] Branch { Points [0, 105] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 120] Branch { DstBlock "Relational5" DstPort 1 } Branch { Points [0, 145] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, 85] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 110] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 35] DstBlock "Relational7" DstPort 1 } } } } } } Branch { Points [0, -150] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Bit sel" SrcPort 1 Points [130, 0] Branch { Points [0, 235] DstBlock "Relational6" DstPort 1 } Branch { Points [0, -85] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "AddSub2" SrcPort 1 Points [15, 0; 0, -25] DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "AddSub3" DstPort 2 } Line { SrcBlock "AddSub3" SrcPort 1 Points [5, 0; 0, 30] DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 Points [45, 0] Branch { DstBlock "Sel FCS" DstPort 1 } Branch { Points [0, -535] DstBlock "Gateway Out6" DstPort 1 } } Line { Name "Bit Sel" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "DATA Sections" DstPort 2 } Line { Name "Byte Ind" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "DATA Sections" DstPort 1 } Line { Name "Unscrambled" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "DATA Sections" DstPort 3 } Line { Name "Sel Zero" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "DATA Sections" DstPort 4 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Display" DstPort 1 } Line { Name "Sel FCS" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "DATA Sections" DstPort 5 } Line { Name "DATA Done" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "DATA Sections" DstPort 6 } Line { SrcBlock "Logical3" SrcPort 1 Points [55, 0] Branch { DstBlock "DATA Done" DstPort 1 } Branch { Points [0, -390] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Relational7" SrcPort 1 Points [20, 0; 0, -10] DstBlock "Logical5" DstPort 3 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Relational7" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Sel HTSIG" DstPort 1 } Annotation { Name "11ag Bytes (L = SIGNAL.LENGTH):\n0:2 : SIGNAL No FCS, Unscrambled\n3:4 : SERVICE " " No FCS, Scrambled\n4:(L-5) : MAC payload FCS, Scrambled\n(L-4):(L-1): FCS Scrambled\n : P" "AD (zeros) Unscrambled\n : TAIL (zeros) Scrambled" Position [298, 1021] HorizontalAlignment "left" FontName "Consolas" FontSize 14 } Annotation { Name "11n Bytes (L = HT-SIG.LENGTH):\n0:2 : SIGNAL No FCS, Unscrambled\n3:8 : HT-SIG " " No FCS, Unscrambled\n9:10 : SERVICE No FCS, Scrambled\n10:(L-5) : MAC payload FCS, Scrambled\n(L-4)" ":(L-1): FCS Scrambled\n : PAD (zeros) Unscrambled\n : TAIL (zeros) Scrambled" Position [693, 1026] HorizontalAlignment "left" FontName "Consolas" FontSize 14 } Annotation { Name "6 bits past L are unscrambled zero (TAIL). \nAll further bits to fill symbol are scrambled\nzeros (PAD)." Position [483, 1146] HorizontalAlignment "left" FontName "Consolas" FontSize 14 } Annotation { Name "len(SIGNAL)" Position [235, 389] } Annotation { Name "len(L-SIG + HT-SIG)" Position [214, 428] } Annotation { Name "len(SERVICE)" Position [329, 482] } Annotation { Name "len(FCS)" Position [534, 792] } Annotation { Name "len(TAIL)" Position [662, 469] } } } Block { BlockType Scope Name "Pkt Data" SID "2575" Ports [7] Position [1750, 123, 1795, 237] ZOrder -3 Floating off Location [147, 85, 2126, 1521] Open off NumInputPorts "7" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } YMin "-5~-5~-5~-5~-5~-5~-5" YMax "5~5~5~5~5~5~5" SaveName "ScopeData8" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "SIGNAL & HT-SIG\nDecode" SID "913" Ports [3, 2] Position [810, 587, 930, 653] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "SIGNAL & HT-SIG\nDecode" Location [-1678, 227, -18, 1171] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "110" Block { BlockType Inport Name "Byte" SID "914" Position [140, 203, 170, 217] IconDisplay "Port number" } Block { BlockType Inport Name "Byte Ind" SID "915" Position [140, 123, 170, 137] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Valid" SID "916" Position [140, 163, 170, 177] Port "3" IconDisplay "Port number" } Block { BlockType From Name "From" SID "918" Position [15, 239, 110, 261] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType From Name "From1" SID "919" Position [550, 632, 685, 648] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType From Name "From10" SID "920" Position [915, 172, 1050, 188] ZOrder -9 ShowName off GotoTag "Code_Rate_11n" } Block { BlockType From Name "From11" SID "921" Position [915, 247, 1050, 263] ZOrder -9 ShowName off GotoTag "Mod_Sel_11n" } Block { BlockType From Name "From12" SID "922" Position [915, 302, 1050, 318] ZOrder -9 ShowName off GotoTag "N_DBPS_11ag" } Block { BlockType From Name "From13" SID "923" Position [915, 227, 1050, 243] ZOrder -9 ShowName off GotoTag "Mod_Sel_11ag" } Block { BlockType From Name "From14" SID "924" Position [915, 387, 1050, 403] ZOrder -9 ShowName off GotoTag "N_CBPS_11ag" } Block { BlockType From Name "From15" SID "925" Position [915, 407, 1050, 423] ZOrder -9 ShowName off GotoTag "N_CBPS_11n" } Block { BlockType From Name "From16" SID "926" Position [915, 152, 1050, 168] ZOrder -9 ShowName off GotoTag "Code_Rate_11ag" } Block { BlockType From Name "From17" SID "927" Position [915, 97, 1050, 113] ZOrder -9 ShowName off GotoTag "MCS_11n" } Block { BlockType From Name "From18" SID "928" Position [915, 77, 1050, 93] ZOrder -9 ShowName off GotoTag "MCS_11ag" } Block { BlockType From Name "From23" SID "930" Position [735, 867, 870, 883] ZOrder -9 ShowName off GotoTag "HT_SIG_Unsupported" } Block { BlockType From Name "From24" SID "931" Position [735, 852, 870, 868] ZOrder -9 ShowName off GotoTag "HT_SIG_Valid" } Block { BlockType From Name "From25" SID "932" Position [735, 807, 870, 823] ZOrder -9 ShowName off GotoTag "SIGNAL_Invalid" } Block { BlockType From Name "From26" SID "933" Position [735, 902, 870, 918] ZOrder -9 ShowName off GotoTag "HT_SIG_Invalid" } Block { BlockType From Name "From27" SID "934" Position [915, 457, 1050, 473] ZOrder -9 ShowName off GotoTag "N_SS_11ag" } Block { BlockType From Name "From28" SID "935" Position [915, 477, 1050, 493] ZOrder -9 ShowName off GotoTag "N_SS_11n" } Block { BlockType From Name "From29" SID "936" Position [735, 887, 870, 903] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType From Name "From30" SID "937" Position [735, 837, 870, 853] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType From Name "From6" SID "938" Position [550, 617, 685, 633] ZOrder -9 ShowName off GotoTag "HT_SIG_Valid" } Block { BlockType From Name "From7" SID "939" Position [915, 572, 1050, 588] ZOrder -9 ShowName off GotoTag "LENGTH_11ag" } Block { BlockType From Name "From8" SID "940" Position [915, 592, 1050, 608] ZOrder -9 ShowName off GotoTag "LENGTH_11n" } Block { BlockType From Name "From9" SID "941" Position [915, 322, 1050, 338] ZOrder -9 ShowName off GotoTag "N_DBPS_11n" } Block { BlockType Reference Name "Gateway Out1" SID "2167" Ports [1, 1] Position [1620, 679, 1650, 691] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out2" SID "2168" Ports [1, 1] Position [1620, 694, 1650, 706] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out3" SID "2169" Ports [1, 1] Position [1620, 664, 1650, 676] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out4" SID "2170" Ports [1, 1] Position [1620, 709, 1650, 721] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Goto Name "Goto1" SID "942" Position [440, 122, 575, 138] ShowName off GotoTag "SIGNAL_Invalid" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "943" Position [440, 167, 575, 183] ShowName off GotoTag "Mod_Sel_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto11" SID "944" Position [440, 407, 575, 423] ShowName off GotoTag "Mod_Sel_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto12" SID "945" Position [440, 182, 575, 198] ShowName off GotoTag "Code_Rate_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto13" SID "946" Position [440, 422, 575, 438] ShowName off GotoTag "Code_Rate_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto14" SID "947" Position [440, 212, 575, 228] ShowName off GotoTag "N_DBPS_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto15" SID "948" Position [440, 452, 575, 468] ShowName off GotoTag "N_DBPS_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto16" SID "949" Position [440, 227, 575, 243] ShowName off GotoTag "N_CBPS_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto17" SID "950" Position [440, 467, 575, 483] ShowName off GotoTag "N_CBPS_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto18" SID "951" Position [440, 482, 575, 498] ShowName off GotoTag "N_SS_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto19" SID "952" Position [440, 242, 575, 258] ShowName off GotoTag "N_SS_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "953" Position [440, 107, 575, 123] ShowName off GotoTag "SIGNAL_Valid" TagVisibility "local" } Block { BlockType Goto Name "Goto20" SID "954" Position [440, 197, 575, 213] ShowName off GotoTag "Chan_BW_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto21" SID "955" Position [440, 437, 575, 453] ShowName off GotoTag "Chan_BW_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto22" SID "956" Position [1325, 225, 1525, 245] ShowName off GotoTag "OFDM_TX_DATA_Mod_Sel" TagVisibility "global" } Block { BlockType Goto Name "Goto24" SID "957" Position [440, 332, 575, 348] ShowName off GotoTag "HT_SIG_Valid" TagVisibility "local" } Block { BlockType Goto Name "Goto25" SID "958" Position [440, 347, 575, 363] ShowName off GotoTag "HT_SIG_Invalid" TagVisibility "local" } Block { BlockType Goto Name "Goto26" SID "959" Position [1325, 150, 1525, 170] ShowName off GotoTag "OFDM_TX_DATA_Code_Rate" TagVisibility "global" } Block { BlockType Goto Name "Goto27" SID "960" Position [1325, 300, 1525, 320] ShowName off GotoTag "OFDM_TX_DATA_N_DBPS" TagVisibility "global" } Block { BlockType Goto Name "Goto28" SID "961" Position [1325, 385, 1525, 405] ShowName off GotoTag "OFDM_TX_DATA_N_CBPS" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "962" Position [1325, 75, 1525, 95] ShowName off GotoTag "OFDM_TX_DATA_MCS" TagVisibility "global" } Block { BlockType Goto Name "Goto30" SID "963" Position [440, 497, 575, 513] ShowName off GotoTag "HT_SIG_Done" TagVisibility "local" } Block { BlockType Goto Name "Goto34" SID "965" Position [1325, 455, 1525, 475] ShowName off GotoTag "OFDM_TX_DATA_N_SS" TagVisibility "global" } Block { BlockType Goto Name "Goto36" SID "966" Position [440, 257, 575, 273] ShowName off GotoTag "SIGNAL_Done" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "967" Position [440, 377, 575, 393] ShowName off GotoTag "LENGTH_11n" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "968" Position [1325, 570, 1525, 590] ShowName off GotoTag "OFDM_TX_DATA_LENGTH" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "969" Position [440, 362, 575, 378] ShowName off GotoTag "HT_SIG_Unsupported" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "970" Position [440, 137, 575, 153] ShowName off GotoTag "LENGTH_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "971" Position [440, 152, 575, 168] ShowName off GotoTag "MCS_11ag" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "972" Position [440, 392, 575, 408] ShowName off GotoTag "MCS_11n" TagVisibility "local" } Block { BlockType SubSystem Name "HT-SIG Decode" SID "973" Ports [4, 13] Position [255, 315, 370, 515] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "HT-SIG Decode" Location [-1678, 227, -18, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "97" Block { BlockType Inport Name "byte_ind" SID "974" Position [90, 463, 120, 477] IconDisplay "Port number" } Block { BlockType Inport Name "byte_valid" SID "975" Position [90, 423, 120, 437] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "byte" SID "976" Position [90, 353, 120, 367] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "977" Position [90, 388, 120, 402] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "CRC8 Calc" SID "2750" Ports [4, 1] Position [735, 867, 860, 968] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CRC8 Calc" Location [480, 85, 2361, 1332] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "byte_ind" SID "2751" Position [85, 308, 115, 322] IconDisplay "Port number" } Block { BlockType Inport Name "data_valid" SID "2752" Position [85, 193, 115, 207] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "data_byte" SID "2753" Position [85, 153, 115, 167] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "reset" SID "2754" Position [85, 353, 115, 367] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "4LSB Calc" SID "2755" Ports [1, 1] Position [835, 266, 945, 304] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "4LSB Calc" Location [2, 74, 2469, 1576] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "crc_accum" SID "2756" Position [295, 317, 325, 333] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "2757" Ports [4, 1] Position [870, 310, 915, 480] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "4" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,170,4,1,white,blue,0,47d3d416,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 170 170 0 ],[0.77 0." "82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 170 170 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[91." "66 91.66 97.66 91.66 97.66 97.66 97.66 91.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[85.66 85.66 91" ".66 91.66 85.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[79.66 79.66 85.66 85.66 79.66 ]," "[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[73.66 73.66 79.66 73.66 79.66 79.66 73.66 ],[0.93" "1 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'hi');\n\n\ncolor('black');port_label('input',4,'lo');\n\ncolor('black');disp('\\font" "size{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2758" Ports [2, 1] Position [665, 396, 710, 434] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 2" "4.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.5" "5 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor(" "'black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "2759" Ports [2, 1] Position [665, 316, 710, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 2" "4.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.5" "5 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor(" "'black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "2760" Ports [2, 1] Position [775, 356, 820, 394] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 2" "4.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.5" "5 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor(" "'black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[0]" SID "2761" Ports [1, 1] Position [395, 357, 435, 373] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[1]" SID "2762" Ports [1, 1] Position [395, 317, 435, 333] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]" SID "2763" Ports [1, 1] Position [395, 447, 435, 463] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7]" SID "2764" Ports [1, 1] Position [395, 487, 435, 503] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Final 4LSB" SID "2765" Position [1000, 388, 1030, 402] IconDisplay "Port number" } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Final 4LSB" DstPort 1 } Line { SrcBlock "b[6]" SrcPort 1 Points [195, 0] Branch { DstBlock "Concat" DstPort 4 } Branch { Points [0, -50] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 Points [35, 0] Branch { DstBlock "Concat" DstPort 3 } Branch { Points [0, -30] DstBlock "Logical4" DstPort 2 } } Line { SrcBlock "b[7]" SrcPort 1 Points [200, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -80] DstBlock "Logical3" DstPort 2 } } Line { SrcBlock "b[1]" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b[0]" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "crc_accum" SrcPort 1 Points [35, 0] Branch { DstBlock "b[1]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[0]" DstPort 1 } Branch { Points [0, 90] Branch { DstBlock "b[6]" DstPort 1 } Branch { Points [0, 40] DstBlock "b[7]" DstPort 1 } } } } } } Block { BlockType Reference Name "Assert1" SID "2766" Ports [1, 1] Position [805, 153, 840, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware th" "is block costs nothing." assert_type off type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,423" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,14,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('Ass" "ert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "CRC8 Lookup" SID "2767" Ports [1, 1] Position [540, 114, 590, 166] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "256" initVector "CRC_Table8" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,308" block_type "sprom" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,52,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 52 52 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 52 52 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.7" "7 33.77 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 " "33.77 33.77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat3" SID "2768" Ports [2, 1] Position [1050, 97, 1100, 348] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "50,251,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 251 251 0 ],[0.77 0." "82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 251 251 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[" "132.77 132.77 139.77 132.77 139.77 139.77 139.77 132.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[" "125.77 125.77 132.77 132.77 125.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[118.77 118" ".77 125.77 125.77 118.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[111.77 111.77 118.7" "7 111.77 118.77 118.77 111.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','C" "OMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo'" ");\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "2769" Ports [0, 1] Position [155, 234, 180, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "2770" Ports [0, 1] Position [155, 269, 180, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Endian Swap" SID "2771" Ports [1, 1] Position [295, 147, 350, 173] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "2772" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "2773" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "2774" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "2775" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "2776" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "2777" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "2778" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "2779" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "2780" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "2781" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "2782" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b3" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b4" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b5" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b6" DstPort 1 } Branch { Points [0, 35] DstBlock "b7" DstPort 1 } } } } } } } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } } } Block { BlockType Reference Name "Inverter" SID "2789" Ports [1, 1] Position [1170, 216, 1215, 234] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2790" Ports [3, 1] Position [305, 181, 340, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,108,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 108 108 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 108 108 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[59.55" " 59.55 64.55 59.55 64.55 64.55 64.55 59.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[54.55 54.55 59." "55 59.55 54.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[49.55 49.55 54.55 54.55 49.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[44.55 44.55 49.55 44.55 49.55 49.55 44.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\nco" "lor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "2791" Ports [2, 1] Position [410, 100, 455, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,80,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 80 80 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 80 80 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[46.66 4" "6.66 52.66 46.66 52.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 " "46.66 40.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[34.66 34.66 40.66 40.66 34.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[28.66 28.66 34.66 28.66 34.66 34.66 28.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "2792" Ports [2, 1] Position [230, 215, 265, 255] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "2793" Ports [2, 1] Position [230, 250, 265, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[5:2]" SID "2794" Ports [1, 1] Position [935, 152, 975, 168] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "crc_accum" SID "2795" Ports [3, 1] Position [690, 133, 735, 187] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('FF')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,54,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 54 54 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 54 54 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[33.66 3" "3.66 39.66 33.66 39.66 39.66 39.66 33.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[27.66 27.66 33.66 " "33.66 27.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[21.66 21.66 27.66 27.66 21.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[15.66 15.66 21.66 15.66 21.66 21.66 15.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "CRC8" SID "2796" Position [1330, 218, 1360, 232] IconDisplay "Port number" } Line { SrcBlock "Endian Swap" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "CRC8 Lookup" SrcPort 1 DstBlock "crc_accum" DstPort 1 } Line { SrcBlock "Assert1" SrcPort 1 Points [35, 0] Branch { Points [0, -80; -525, 0; 0, 40] DstBlock "Logical3" DstPort 1 } Branch { DstBlock "b[5:2]" DstPort 1 } } Line { SrcBlock "crc_accum" SrcPort 1 Points [25, 0] Branch { DstBlock "Assert1" DstPort 1 } Branch { Labels [0, 0] Points [0, 125] DstBlock "4LSB Calc" DstPort 1 } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "CRC8 Lookup" DstPort 1 } Line { SrcBlock "data_byte" SrcPort 1 DstBlock "Endian Swap" DstPort 1 } Line { SrcBlock "byte_ind" SrcPort 1 Points [80, 0; 0, -55] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, -35] DstBlock "Relational3" DstPort 1 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "data_valid" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical1" DstPort 3 } Line { SrcBlock "Logical1" SrcPort 1 Points [295, 0; 0, -55] DstBlock "crc_accum" DstPort 3 } Line { SrcBlock "reset" SrcPort 1 Points [500, 0; 0, -200] DstBlock "crc_accum" DstPort 2 } Line { SrcBlock "b[5:2]" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "4LSB Calc" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "Concat3" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "CRC8" DstPort 1 } Annotation { Name "This logic implements parallel version of the 8-bit shift register shown in IEEE 802.11-2012 20.3.9.4" ".4. The crc_accum \nblock contains the shift register state after the first 4 bytes of the HT-SIG are read. The " "CRC value must then be updated by \nloading 2 additional 0 bits (the N_ESS bits) to comptue the final CRC value " "used as the 8-bit checksum in the HT-SIG field.\n\nGiven the state of the shift register after loading 32 messag" "e bits, it is possible to directly compute the final shift register state.\n\nLet C[7:0] be value of CRC shift r" "egister (crc_accum here) after first 32 bits (4 bytes) have been processed.\n\nAssume 2LSB of byte 4, NUM_ESS in" " the HT-SIG defintion, are 00. This is definitely true for this version of the Tx PHY.\n\nFinal 8-bit checksum v" "alue can be computed by initializing the CRC shift register with C[7:0], then shifting in two zero message bits." " \n\nThe shift register state after loading 1 zero message bit (Cb1[7:0]) as a function of C:\n\nCb1[7:3] = C[6:" "2]\nCb1[ 2] = C[1] ^ C[7]\nCb1[ 1] = C[0] ^ C[7]\nCb1[ 0] = C[7]\n\nThe final state of the shift register CF[" "7:0] can be expressed as a function of Cb1:\n\nCF[7:3] = Cb1[6:2]\nCF[ 2] = Cb1[1] ^ Cb1[7]\nCF[ 1] = Cb1[0] ^" " Cb1[7]\nCF[ 0] = Cb1[7]\n\nExpanding Cb1 gives CF as a function of C:\n\nCF[7:4] = C[5:2] (== Cb" "1[6:3])\nCF[ 3] = C[1] ^ C[7] (== Cb1[2])\nCF[ 2] = C[0] ^ C[7] ^ C[6] (== Cb1[1] ^ Cb1[7])\nCF[ 1" "] = C[7] ^ C[6] (== Cb1[0] ^ Cb1[7])\nCF[ 0] = C[6] (== Cb1[7])" Position [141, 656] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } } } Block { BlockType Reference Name "Concat2" SID "2719" Ports [2, 1] Position [980, 1030, 1040, 1090] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38" ".88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38." "88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "1029" Ports [0, 1] Position [180, 574, 205, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "1030" Ports [0, 1] Position [180, 624, 205, 646] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "1031" Ports [0, 1] Position [180, 479, 205, 501] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "1032" Ports [0, 1] Position [180, 809, 205, 831] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "1033" Ports [0, 1] Position [180, 859, 205, 881] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "8" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,7a8c02d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'8');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "1034" Ports [0, 1] Position [180, 759, 205, 781] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT" SID "1035" Ports [3, 1] Position [610, 438, 645, 482] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT1" SID "1036" Ports [3, 1] Position [610, 533, 645, 577] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "100" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT2" SID "1037" Ports [3, 1] Position [610, 583, 645, 627] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT3" SID "1038" Ports [3, 1] Position [610, 718, 645, 762] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('03')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT4" SID "1039" Ports [3, 1] Position [610, 768, 645, 812] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('E0')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "1040" Ports [1, 1] Position [610, 985, 650, 1015] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "1041" Ports [1, 1] Position [760, 985, 800, 1015] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19" ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19." "44 15.44 ],[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]" ");\npatch([15.1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Format" SID "2849" Ports [1, 2] Position [920, 888, 1010, 952] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Format" Location [480, 85, 2254, 854] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "CRC" SID "2850" Position [285, 172, 315, 188] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "Concat1" SID "2851" Ports [2, 1] Position [535, 150, 570, 265] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,115,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 115 115 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 115 115 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[62.55" " 62.55 67.55 62.55 67.55 67.55 67.55 62.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[57.55 57.55 62." "55 62.55 57.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[52.55 52.55 57.55 57.55 52.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[47.55 47.55 52.55 47.55 52.55 52.55 47.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{" "20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "2852" Ports [2, 1] Position [535, 290, 570, 405] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,115,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 115 115 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 115 115 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[62.55" " 62.55 67.55 62.55 67.55 67.55 67.55 62.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[57.55 57.55 62." "55 62.55 57.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[52.55 52.55 57.55 57.55 52.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[47.55 47.55 52.55 47.55 52.55 52.55 47.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{" "20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "2853" Ports [0, 1] Position [420, 305, 455, 335] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,30,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('ou" "tput',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "2854" Ports [0, 1] Position [420, 220, 455, 250] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,30,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('ou" "tput',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Endian Swap1" SID "2855" Ports [1, 1] Position [620, 337, 665, 363] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap1" Location [480, 85, 1649, 904] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "2856" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "2857" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "2858" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "2859" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "2860" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "2861" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "2862" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "2863" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "2864" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "2865" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "2866" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] DstBlock "b7" DstPort 1 } Branch { DstBlock "b6" DstPort 1 } } Branch { DstBlock "b5" DstPort 1 } } Branch { DstBlock "b4" DstPort 1 } } Branch { DstBlock "b3" DstPort 1 } } Branch { DstBlock "b2" DstPort 1 } } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType SubSystem Name "Endian Swap2" SID "2867" Ports [1, 1] Position [620, 197, 665, 223] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Endian Swap2" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B" SID "2868" Position [270, 313, 300, 327] IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "2869" Ports [8, 1] Position [530, 296, 565, 589] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,293,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 293 293 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 293 293 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[151.5" "5 151.55 156.55 151.55 156.55 156.55 156.55 151.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[146.55 " "146.55 151.55 151.55 146.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[141.55 141.55 146.5" "5 146.55 141.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[136.55 136.55 141.55 136.55 141." "55 141.55 136.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin" " icon text');\ncolor('black');port_label('input',1,'hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo')" ";\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "2870" Ports [1, 1] Position [435, 311, 475, 329] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "2871" Ports [1, 1] Position [435, 346, 475, 364] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "2872" Ports [1, 1] Position [435, 381, 475, 399] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "2873" Ports [1, 1] Position [435, 416, 475, 434] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "2874" Ports [1, 1] Position [435, 451, 475, 469] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "2875" Ports [1, 1] Position [435, 486, 475, 504] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "2876" Ports [1, 1] Position [435, 521, 475, 539] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "2877" Ports [1, 1] Position [435, 556, 475, 574] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "2878" Position [650, 438, 680, 452] IconDisplay "Port number" } Line { SrcBlock "B" SrcPort 1 Points [100, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b3" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b4" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b5" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b6" DstPort 1 } Branch { Points [0, 35] DstBlock "b7" DstPort 1 } } } } } } } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Concat" DstPort 4 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Concat" DstPort 5 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Concat" DstPort 6 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Concat" DstPort 7 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Concat" DstPort 8 } } } Block { BlockType Reference Name "b[1:0]" SID "2879" Ports [1, 1] Position [415, 172, 455, 188] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7:2]" SID "2880" Ports [1, 1] Position [415, 367, 455, 383] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "HTSIG[4]" SID "2881" Position [735, 343, 765, 357] IconDisplay "Port number" } Block { BlockType Outport Name "HTSIG[5]" SID "2882" Position [735, 203, 765, 217] Port "2" IconDisplay "Port number" } Line { SrcBlock "CRC" SrcPort 1 Points [40, 0] Branch { DstBlock "b[1:0]" DstPort 1 } Branch { Points [0, 195] DstBlock "b[7:2]" DstPort 1 } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Endian Swap2" SrcPort 1 DstBlock "HTSIG[5]" DstPort 1 } Line { SrcBlock "Endian Swap1" SrcPort 1 DstBlock "HTSIG[4]" DstPort 1 } Line { SrcBlock "b[1:0]" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Endian Swap2" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "b[7:2]" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "Endian Swap1" DstPort 1 } Annotation { Name "Let checksum byte be C[7:0]\nB5[7:0] = [0 0 0 0 0 0 C[0] C[1]]\nB4[7:0] = [C[2] C[3] C[4] C[5] C[6] C" "[7] 0 0]" Position [472, 66] HorizontalAlignment "left" FontName "Consolas" } } } Block { BlockType Reference Name "Gateway Out1" SID "1044" Ports [1, 1] Position [1390, 84, 1425, 96] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Length" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "1045" Ports [1, 1] Position [1390, 259, 1425, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "HT-SIG Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "1046" Ports [1, 1] Position [1390, 109, 1425, 121] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "MCS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "1047" Ports [1, 1] Position [1390, 134, 1425, 146] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Mod Order" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "1048" Ports [1, 1] Position [1390, 159, 1425, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Code Rate" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "1049" Ports [1, 1] Position [1390, 184, 1425, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Chan BW" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "1050" Ports [1, 1] Position [1390, 209, 1425, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Unsupported" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "1051" Ports [1, 1] Position [1390, 234, 1425, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "HT-SIG Invalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "HT Length" SID "1053" Ports [2, 1] Position [735, 540, 850, 600] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "HT Length" Location [380, 118, 2362, 1458] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B4" SID "1054" Position [300, 443, 330, 457] IconDisplay "Port number" } Block { BlockType Inport Name "B5" SID "1055" Position [300, 408, 330, 422] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat1" SID "1056" Ports [2, 1] Position [415, 396, 475, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,73,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 73 73 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 73 73 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[44.88 44" ".88 52.88 44.88 52.88 52.88 52.88 44.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[36.88 36.88 44.88 44." "88 36.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[28.88 28.88 36.88 36.88 28.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[20.88 20.88 28.88 20.88 28.88 28.88 20.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "length" SID "1057" Position [575, 428, 605, 442] IconDisplay "Port number" } Line { SrcBlock "B5" SrcPort 1 DstBlock "Concat1" DstPort 1 } Line { SrcBlock "B4" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "length" DstPort 1 } } } Block { BlockType Scope Name "HT-SIG Decode" SID "1058" Ports [8] Position [1550, 73, 1585, 282] ZOrder -3 Floating off Location [729, 154, 2135, 1498] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "7000" YMin "0~0~0~0~100~-1~-1~-1" YMax "1~1~150~1~300~1~1~1" SaveName "ScopeData45" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "HT-SIG Flags" SID "1059" Ports [3, 1] Position [735, 710, 850, 770] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "HT-SIG Flags" Location [380, 118, 2362, 1458] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "B3" SID "1060" Position [300, 293, 330, 307] IconDisplay "Port number" } Block { BlockType Inport Name "B6" SID "1061" Position [300, 328, 330, 342] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B7" SID "1062" Position [300, 573, 330, 587] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "1063" Ports [0, 1] Position [440, 739, 475, 761] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "1064" Ports [0, 1] Position [440, 699, 475, 721] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14" ".33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11." "33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 " "8.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "1065" Position [635, 291, 755, 309] ZOrder -10 ShowName off GotoTag "CHAN_BW" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "1066" Position [635, 326, 755, 344] ZOrder -10 ShowName off GotoTag "SMOOTHING" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "1067" Position [635, 361, 755, 379] ZOrder -10 ShowName off GotoTag "NOT_SOUNDING" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "1068" Position [635, 396, 755, 414] ZOrder -10 ShowName off GotoTag "AGGREGATION" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "1069" Position [635, 436, 755, 454] ZOrder -10 ShowName off GotoTag "STBC" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "1070" Position [635, 476, 755, 494] ZOrder -10 ShowName off GotoTag "FEC" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "1071" Position [635, 511, 755, 529] ZOrder -10 ShowName off GotoTag "SHORT_GI" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "1072" Position [635, 571, 755, 589] ZOrder -10 ShowName off GotoTag "N_ESS" TagVisibility "local" } Block { BlockType Reference Name "Logical" SID "1073" Ports [5, 1] Position [645, 611, 700, 749] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "5" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "55,138,5,1,white,blue,0,d9ddc810,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 138 138 0 ],[0.77 0." "82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 138 138 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[76.77 76.77 83.77 76.77 83.77 83.77 83.77 76.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[69.77" " 69.77 76.77 76.77 69.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[62.77 62.77 69.77 " "69.77 62.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[55.77 55.77 62.77 55.77 62.77 6" "2.77 55.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\n\n\n\n\n\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "1074" Ports [2, 1] Position [540, 725, 585, 760] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,35,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 35 35 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[22.55 2" "2.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[17.55 17.55 22.5" "5 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[12.55 12.55 17.55 17.55 12.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "1075" Ports [2, 1] Position [540, 685, 585, 720] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,35,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 35 35 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[22.55 2" "2.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[17.55 17.55 22.5" "5 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[12.55 12.55 17.55 17.55 12.55 ]" ",[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[0]" SID "1076" Ports [1, 1] Position [425, 327, 465, 343] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[1:0]" SID "1077" Ports [1, 1] Position [425, 572, 465, 588] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[1]" SID "1078" Ports [1, 1] Position [425, 362, 465, 378] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[3]" SID "1079" Ports [1, 1] Position [425, 397, 465, 413] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[5:4]" SID "1080" Ports [1, 1] Position [425, 437, 465, 453] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]" SID "1081" Ports [1, 1] Position [425, 477, 465, 493] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7]" SID "1082" Ports [1, 1] Position [425, 292, 465, 308] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7] " SID "1083" Ports [1, 1] Position [425, 512, 465, 528] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Unsupported" SID "1084" Position [800, 673, 830, 687] IconDisplay "Port number" } Line { SrcBlock "B3" SrcPort 1 DstBlock "b[7]" DstPort 1 } Line { SrcBlock "B6" SrcPort 1 Points [65, 0] Branch { DstBlock "b[0]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[1]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[3]" DstPort 1 } Branch { Points [0, 40] Branch { Points [0, 40] Branch { DstBlock "b[6]" DstPort 1 } Branch { Points [0, 35] DstBlock "b[7] " DstPort 1 } } Branch { DstBlock "b[5:4]" DstPort 1 } } } } } Line { SrcBlock "b[7]" SrcPort 1 Points [140, 0] Branch { DstBlock "Goto" DstPort 1 } Branch { Points [0, 330] DstBlock "Logical" DstPort 1 } } Line { SrcBlock "b[3]" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "b[1]" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "b[0]" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "b[5:4]" SrcPort 1 Points [35, 0] Branch { DstBlock "Goto4" DstPort 1 } Branch { Points [0, 250] DstBlock "Relational1" DstPort 1 } } Line { SrcBlock "b[6]" SrcPort 1 Points [130, 0] Branch { DstBlock "Goto5" DstPort 1 } Branch { Points [0, 170] DstBlock "Logical" DstPort 2 } } Line { SrcBlock "b[7] " SrcPort 1 Points [120, 0] Branch { DstBlock "Goto6" DstPort 1 } Branch { Points [0, 160] DstBlock "Logical" DstPort 3 } } Line { SrcBlock "B7" SrcPort 1 DstBlock "b[1:0]" DstPort 1 } Line { SrcBlock "b[1:0]" SrcPort 1 Points [30, 0] Branch { DstBlock "Goto7" DstPort 1 } Branch { Points [0, 155] DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [20, 0; 0, -15] DstBlock "Logical" DstPort 5 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 4 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Unsupported" DstPort 1 } Annotation { Name "HT-SIG Flags\n(IEEE 802.11-2012 Figured 20-6)\n\nB3[7]: Channel bandwidth (0=20, 1=40)\n\nB6[0]: Smoo" "thing\nB6[1]: Not sounding\nB6[2]: Reserved (always 1)\nB6[3]: Aggregation\nB6[5:4]: STBC\nB6[6]: FEC (0=BCC, 1=" "LDPC)\nB6[7]: Short GI\n\nB7[1:0]: Num extension spatial streams" Position [1008, 354] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } } } Block { BlockType Reference Name "Inverter4" SID "1085" Ports [1, 1] Position [1145, 596, 1175, 614] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "1086" Ports [2, 1] Position [375, 603, 400, 632] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1087" Ports [2, 1] Position [375, 553, 400, 582] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1088" Ports [2, 1] Position [375, 458, 400, 487] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1089" Ports [2, 1] Position [375, 838, 400, 867] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "1090" Ports [2, 1] Position [375, 788, 400, 817] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "1091" Ports [2, 1] Position [375, 738, 400, 767] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "1092" Ports [2, 1] Position [1210, 595, 1250, 635] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "1094" Ports [2, 1] Position [1210, 750, 1250, 790] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical9" SID "1095" Ports [2, 1] Position [1045, 475, 1085, 515] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "MCS Decode" SID "1096" Ports [2, 9] Position [735, 267, 850, 523] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "MCS Decode" Location [380, 118, 2362, 1458] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "B3" SID "1097" Position [110, 253, 140, 267] IconDisplay "Port number" } Block { BlockType Inport Name "B6" SID "1098" Position [110, 203, 140, 217] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "5LSB" SID "1099" Ports [1, 1] Position [220, 252, 260, 268] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "5" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "7LSB" SID "1100" Ports [1, 1] Position [220, 457, 260, 473] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "7" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "1101" Ports [2, 1] Position [325, 199, 370, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,47,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 2" "9.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 " "29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}" "\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "1102" Ports [0, 1] Position [375, 692, 400, 708] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "76" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "7" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,d2990f9d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'76');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant17" SID "1103" Ports [0, 1] Position [375, 552, 400, 568] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant18" SID "1104" Ports [0, 1] Position [375, 657, 400, 673] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "31" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "7" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,8a5cc997,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'31');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "1105" Ports [1, 1] Position [635, 511, 660, 529] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1106" Ports [2, 1] Position [700, 508, 725, 557] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,49,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 49 49 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[27.33 " "27.33 30.33 27.33 30.33 30.33 30.33 27.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[24.33 24.33 27.33" " 27.33 24.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[21.33 21.33 24.33 24.33 21.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[18.33 18.33 21.33 18.33 21.33 21.33 18.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor" "('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "ROM" SID "1107" Ports [1, 1] Position [420, 197, 480, 253] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "numel(mcs_rom_11n)" initVector "mcs_rom_11n" distributed_mem "Block RAM" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "60,56,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text')" ";" } Block { BlockType Reference Name "Relational" SID "1108" Ports [2, 1] Position [445, 517, 500, 573] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "1109" Ports [2, 1] Position [445, 622, 500, 678] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35" ".77 35.77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28." "77 35.77 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.7" "7 21.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77" " 14.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_l" "abel('output',1,'\\bfa \\leq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text'" ");" } Block { BlockType Reference Name "b[0]" SID "1110" Ports [1, 1] Position [550, 217, 590, 233] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[16:7]" SID "1111" Ports [1, 1] Position [550, 372, 590, 388] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[26:17]" SID "1112" Ports [1, 1] Position [550, 412, 590, 428] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "17" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[2:1]" SID "1113" Ports [1, 1] Position [550, 252, 590, 268] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[4:3]" SID "1114" Ports [1, 1] Position [550, 292, 590, 308] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6:5]" SID "1115" Ports [1, 1] Position [550, 332, 590, 348] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7]" SID "1116" Ports [1, 1] Position [220, 202, 260, 218] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "MCS" SID "1117" Position [775, 458, 805, 472] IconDisplay "Port number" } Block { BlockType Outport Name "mod_sel" SID "1118" Position [775, 293, 805, 307] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "code_rate" SID "1119" Position [775, 333, 805, 347] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "N_CBPS" SID "1120" Position [775, 373, 805, 387] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "N_DBPS" SID "1121" Position [775, 413, 805, 427] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "N_SS" SID "1122" Position [775, 253, 805, 267] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "Chan_BW" SID "1123" Position [775, 218, 805, 232] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "Unsupported" SID "1124" Position [775, 528, 805, 542] Port "8" IconDisplay "Port number" } Block { BlockType Outport Name "MCS Valid" SID "1125" Position [775, 643, 805, 657] Port "9" IconDisplay "Port number" } Line { SrcBlock "Constant18" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "MCS Valid" DstPort 1 } Line { SrcBlock "Constant17" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "B3" SrcPort 1 Points [25, 0] Branch { DstBlock "5LSB" DstPort 1 } Branch { Points [0, 205] DstBlock "7LSB" DstPort 1 } } Line { SrcBlock "B6" SrcPort 1 DstBlock "b[7]" DstPort 1 } Line { SrcBlock "ROM" SrcPort 1 Points [35, 0] Branch { DstBlock "b[0]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[2:1]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[4:3]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[6:5]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[16:7]" DstPort 1 } Branch { Points [0, 40] DstBlock "b[26:17]" DstPort 1 } } } } } } Line { SrcBlock "b[7]" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "5LSB" SrcPort 1 Points [20, 0; 0, -25] DstBlock "Concat" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "ROM" DstPort 1 } Line { SrcBlock "7LSB" SrcPort 1 Points [95, 0] Branch { DstBlock "MCS" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 105] DstBlock "Relational1" DstPort 1 } } } Line { SrcBlock "b[6:5]" SrcPort 1 DstBlock "code_rate" DstPort 1 } Line { SrcBlock "b[4:3]" SrcPort 1 DstBlock "mod_sel" DstPort 1 } Line { SrcBlock "b[0]" SrcPort 1 Points [15, 0] Branch { DstBlock "Chan_BW" DstPort 1 } Branch { Points [0, 295] DstBlock "Convert" DstPort 1 } } Line { SrcBlock "b[26:17]" SrcPort 1 DstBlock "N_DBPS" DstPort 1 } Line { SrcBlock "b[16:7]" SrcPort 1 DstBlock "N_CBPS" DstPort 1 } Line { SrcBlock "b[2:1]" SrcPort 1 DstBlock "N_SS" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Unsupported" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Logical1" DstPort 1 } Annotation { Name "IEEE 802.11-2012 Table 20-30\nSingle spatial stream 20MHz MCS indexes:\n\n0: BPSK 1/2\n1: QPSK 1/2\n2" ": QPSK 3/4\n3: 16-QAM 1/2\n4: 16-QAM 3/4\n5: 64-QAM 2/3\n6: 64-QAM 3/4\n7: 64-QAM 5/6\n\nMod Order values:\n0: B" "PSK\n1: QPSK\n2: 16-QAM\n3: 64-QAM\n\nCode Rate values:\n0: 1/2\n1: 2/3\n2: 3/4\n3: 5/6 (HT/VHT only)\n\nN_DBPS " "values:\nBPSK 1/2: 26\nQPSK 1/2: 52\nQPSK 3/4: 78\n16-QAM 1/2: 104\n16-QAM 3/4: 156\n64-QAM 2/3: 208\n64-QAM 3/4" ": 234\n64-QAM 5/6: 260" Position [965, 322] HorizontalAlignment "left" } Annotation { Name "Byte_6[7] = Channel bandwidth (0=20, 1=40)\nByte_3[6:0]: MCS (5LSB used here)" Position [131, 165] HorizontalAlignment "left" } Annotation { Name "% Ouptut word contents:\n% b[ 0]: Chan bandwidth\n% b[ 2: 1]: Num spatial streams\n% b[ 4: 3]: " "Mod order index\n% b[ 6: 5]: Code rate index\n% b[16: 7]: Coded bits per symbol per stream\n% b[26:17]: Data " "bits per symbol per stream" Position [445, 128] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } Annotation { Name "MCS index values up to 76 are valid. But this block only decodes MCS indexes\nup to 31. This shortcut" " is based on observing no use of unequal-modulation\nMCS indexes in any actual system, and that all UQM schemes " "were dropped \nin 802.11ac.\n\nI'm technically cheating by calling the UQM MCS indexes invalid. The only real \n" "effect of this would be falling back on energy detection for deferring to UQM \nreceptions, since the rate*lengt" "h block won't attempt a deferral for \nMCS values declared invalid here." Position [342, 775] HorizontalAlignment "left" } Annotation { Name "PHY currently supports MCS 0-7 for BW=20" Position [789, 567] } } } Block { BlockType Reference Name "Mux" SID "2712" Ports [4, 1] Position [1155, 1039, 1180, 1216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,177,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 25.2857 151.714 177 0 " "],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 25.2857 151.714 177 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12." "66 8.325 5.325 ],[91.33 91.33 94.33 91.33 94.33 94.33 94.33 91.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8." "325 ],[88.33 88.33 91.33 91.33 88.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[85.33 85.3" "3 88.33 88.33 85.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[82.33 82.33 85.33 82.33 85." "33 85.33 82.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('bla" "ck');port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','te" "xmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "1126" Ports [2, 1] Position [290, 555, 325, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "1127" Ports [2, 1] Position [290, 605, 325, 645] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "1128" Ports [2, 1] Position [290, 460, 325, 500] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "1129" Ports [2, 1] Position [290, 790, 325, 830] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "1130" Ports [2, 1] Position [290, 840, 325, 880] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "1131" Ports [2, 1] Position [290, 740, 325, 780] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "HT-SIG Bytes" SID "2711" Position [1390, 1123, 1420, 1137] IconDisplay "Port number" } Block { BlockType Outport Name "HT-SIG Valid" SID "1132" Position [1385, 763, 1415, 777] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "HT-SIG Invalid" SID "1133" Position [1385, 608, 1415, 622] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Unsupported" SID "1134" Position [1260, 488, 1290, 502] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "Length" SID "1135" Position [1260, 563, 1290, 577] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "MCS" SID "1136" Position [1260, 268, 1290, 282] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "mod_sel" SID "1137" Position [1260, 298, 1290, 312] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "code_rate" SID "1138" Position [1260, 328, 1290, 342] Port "8" IconDisplay "Port number" } Block { BlockType Outport Name "Chan_BW" SID "1139" Position [1260, 448, 1290, 462] Port "9" IconDisplay "Port number" } Block { BlockType Outport Name "N_DBPS" SID "1140" Position [1260, 388, 1290, 402] Port "10" IconDisplay "Port number" } Block { BlockType Outport Name "N_CBPS" SID "1141" Position [1260, 358, 1290, 372] Port "11" IconDisplay "Port number" } Block { BlockType Outport Name "N_SS" SID "1142" Position [1260, 418, 1290, 432] Port "12" IconDisplay "Port number" } Block { BlockType Outport Name "HT-SIG Done" SID "1143" Position [1385, 993, 1415, 1007] Port "13" IconDisplay "Port number" } Line { SrcBlock "rst" SrcPort 1 Points [450, 0; 0, 65] Branch { Points [0, 95] Branch { DstBlock "DOUT1" DstPort 2 } Branch { Points [0, 50] Branch { DstBlock "DOUT2" DstPort 2 } Branch { Points [0, 135] Branch { DstBlock "DOUT3" DstPort 2 } Branch { Points [0, 50] Branch { DstBlock "DOUT4" DstPort 2 } Branch { Points [0, 165] DstBlock "CRC8 Calc" DstPort 4 } } } } } Branch { DstBlock "DOUT" DstPort 2 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "DOUT1" DstPort 3 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "DOUT" DstPort 3 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "DOUT2" DstPort 3 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "byte" SrcPort 1 Points [460, 0; 0, 85] Branch { Points [0, 95] Branch { DstBlock "DOUT1" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "DOUT2" DstPort 1 } Branch { Points [0, 135] Branch { Points [0, 50] Branch { DstBlock "DOUT4" DstPort 1 } Branch { Points [0, 155] Branch { DstBlock "CRC8 Calc" DstPort 3 } Branch { Points [0, 175] DstBlock "Mux" DstPort 2 } } } Branch { DstBlock "DOUT3" DstPort 1 } } } } Branch { DstBlock "DOUT" DstPort 1 } } Line { SrcBlock "byte_ind" SrcPort 1 Points [135, 0] Branch { Points [0, 95] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 135] Branch { Points [0, 50] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, 30] DstBlock "CRC8 Calc" DstPort 1 } } } Branch { DstBlock "Relational5" DstPort 1 } } } } Branch { DstBlock "Relational2" DstPort 1 } } Line { Labels [0, 0] SrcBlock "byte_valid" SrcPort 1 Points [225, 0; 0, 35] Branch { Points [0, 95] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 135] Branch { Points [0, 50] Branch { DstBlock "Logical4" DstPort 1 } Branch { Points [0, 50] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, 60] DstBlock "CRC8 Calc" DstPort 2 } } } Branch { DstBlock "Logical5" DstPort 1 } } } } Branch { DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "DOUT4" DstPort 3 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "DOUT3" DstPort 3 } Line { SrcBlock "Logical3" SrcPort 1 Points [160, 0; 0, 145] DstBlock "Delay" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical4" DstPort 2 } Branch { Points [0, 235] DstBlock "Concat2" DstPort 1 } } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Relational4" SrcPort 1 Points [5, 0] Branch { DstBlock "Logical3" DstPort 2 } Branch { Points [0, 215] DstBlock "Concat2" DstPort 2 } } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational5" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "DOUT" SrcPort 1 Points [50, 0] Branch { Points [0, 260] DstBlock "HT-SIG Flags" DstPort 1 } Branch { Points [0, -130] DstBlock "MCS Decode" DstPort 1 } } Line { SrcBlock "DOUT1" SrcPort 1 DstBlock "HT Length" DstPort 1 } Line { SrcBlock "DOUT2" SrcPort 1 Points [20, 0; 0, -20] DstBlock "HT Length" DstPort 2 } Line { SrcBlock "DOUT3" SrcPort 1 Points [60, 0] Branch { DstBlock "HT-SIG Flags" DstPort 2 } Branch { Points [0, -280] DstBlock "MCS Decode" DstPort 2 } } Line { Name "Length" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 1 } Line { Name "HT-SIG Valid" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 8 } Line { Name "MCS" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 2 } Line { Name "Mod Order" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 3 } Line { Name "Code Rate" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 4 } Line { SrcBlock "MCS Decode" SrcPort 1 Points [90, 0] Branch { DstBlock "MCS" DstPort 1 } Branch { Points [0, -160] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "MCS Decode" SrcPort 2 Points [95, 0] Branch { DstBlock "mod_sel" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "MCS Decode" SrcPort 3 Points [100, 0] Branch { DstBlock "code_rate" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "MCS Decode" SrcPort 4 DstBlock "N_CBPS" DstPort 1 } Line { SrcBlock "MCS Decode" SrcPort 5 DstBlock "N_DBPS" DstPort 1 } Line { SrcBlock "MCS Decode" SrcPort 6 DstBlock "N_SS" DstPort 1 } Line { SrcBlock "MCS Decode" SrcPort 7 Points [110, 0] Branch { DstBlock "Chan_BW" DstPort 1 } Branch { Points [0, -265] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "HT Length" SrcPort 1 Points [85, 0] Branch { DstBlock "Length" DstPort 1 } Branch { Points [0, -480] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Logical6" SrcPort 1 Points [95, 0] Branch { DstBlock "HT-SIG Invalid" DstPort 1 } Branch { Points [0, -375] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Logical8" SrcPort 1 Points [105, 0] Branch { DstBlock "HT-SIG Valid" DstPort 1 } Branch { Points [0, -505] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "HT-SIG Flags" SrcPort 1 Points [95, 0; 0, -235] DstBlock "Logical9" DstPort 2 } Line { SrcBlock "MCS Decode" SrcPort 8 Points [115, 0] Branch { Points [0, -270] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Logical9" DstPort 1 } } Line { Name "Chan BW" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 5 } Line { Name "Unsupported" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 6 } Line { SrcBlock "Delay1" SrcPort 1 Points [330, 0] Branch { DstBlock "HT-SIG Done" DstPort 1 } Branch { Points [0, -220] Branch { DstBlock "Logical8" DstPort 2 } Branch { Points [0, -155] DstBlock "Logical6" DstPort 2 } } } Line { SrcBlock "DOUT4" SrcPort 1 Points [70, 0] DstBlock "HT-SIG Flags" DstPort 3 } Line { SrcBlock "Logical9" SrcPort 1 DstBlock "Unsupported" DstPort 1 } Line { Name "HT-SIG Invalid" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "HT-SIG Decode" DstPort 7 } Line { SrcBlock "Inverter4" SrcPort 1 DstBlock "Logical6" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "HT-SIG Bytes" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "MCS Decode" SrcPort 9 Points [65, 0; 0, 90; 195, 0] Branch { DstBlock "Inverter4" DstPort 1 } Branch { Points [0, 155] DstBlock "Logical8" DstPort 1 } } Line { Labels [0, 0] SrcBlock "CRC8 Calc" SrcPort 1 DstBlock "Format" DstPort 1 } Line { SrcBlock "Format" SrcPort 2 Points [85, 0; 0, 215] DstBlock "Mux" DstPort 3 } Line { SrcBlock "Format" SrcPort 1 Points [90, 0; 0, 290] DstBlock "Mux" DstPort 4 } Annotation { Name "HTSIG has 8-bit checksum that spans bytes 4 and 5. The logic above\ncalculates the checksum value and" " generates the 8-bit values for HTSIG\nbytes 4 and 5, containing the checkusm bits and tail bits. The Tx PHY \np" "ipeline consumes these HTSIG bytes. Calculating the CRC here saves\nthe MAC software from having to calculate th" "e CRC for every packet.\n\nSoftwrae should always set HTSIG[5:4] = 0x0000." Position [735, 1170] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Logical1" SID "1144" Ports [3, 1] Position [930, 837, 965, 883] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,46,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 46 46 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 46 46 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[28.55 28.55 33." "55 28.55 33.55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[23.55 23.55 28.55 28.55 23." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[18.55 18.55 23.55 23.55 18.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[13.55 13.55 18.55 13.55 18.55 18.55 13.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1145" Ports [2, 1] Position [745, 615, 780, 650] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "1146" Ports [3, 1] Position [1090, 793, 1125, 927] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,134,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 134 134 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 35 35 0 0 ],[0 0 134 134 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[72.55 72.55" " 77.55 72.55 77.55 77.55 77.55 72.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[67.55 67.55 72.55 72.55" " 67.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[62.55 62.55 67.55 67.55 62.55 ],[1 1 1 ]);" "\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[57.55 57.55 62.55 57.55 62.55 62.55 57.55 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');d" "isp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "1147" Ports [2, 1] Position [930, 885, 965, 920] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 35 35 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "1148" Ports [3, 1] Position [1155, 278, 1175, 342] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "1149" Ports [3, 1] Position [1155, 548, 1175, 612] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "1150" Ports [3, 1] Position [1155, 53, 1175, 117] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux5" SID "1151" Ports [3, 1] Position [1155, 433, 1175, 497] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux7" SID "1153" Ports [3, 1] Position [1155, 128, 1175, 192] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux8" SID "1154" Ports [3, 1] Position [1155, 203, 1175, 267] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux9" SID "1155" Ports [3, 1] Position [1155, 363, 1175, 427] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,64,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 9.14286 54.8571 64 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[34.22 34.22 36.22 34.22 36.22 36.22 36.22 34.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[32.22 32." "22 34.22 34.22 32.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[30.22 30.22 32.22 32.22 30.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[28.22 28.22 30.22 28.22 30.22 30.22 28.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "1156" Ports [1, 1] Position [1220, 296, 1250, 324] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register10" SID "1157" Ports [1, 1] Position [1220, 451, 1250, 479] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register11" SID "1158" Ports [1, 1] Position [1220, 566, 1250, 594] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register2" SID "1159" Ports [1, 1] Position [1220, 221, 1250, 249] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register3" SID "1160" Ports [1, 1] Position [1220, 146, 1250, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register4" SID "1161" Ports [1, 1] Position [1220, 71, 1250, 99] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType Reference Name "Register9" SID "1163" Ports [1, 1] Position [1220, 381, 1250, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: en" "d icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "1164" Ports [2, 1] Position [850, 624, 885, 671] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1165" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1166" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1167" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1168" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1169" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1170" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1171" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "SIGNAL Decode" SID "1172" Ports [4, 11] Position [255, 105, 370, 275] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "SIGNAL Decode" Location [-1678, 227, -18, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "byte_ind" SID "1173" Position [85, 468, 115, 482] IconDisplay "Port number" } Block { BlockType Inport Name "byte_valid" SID "1174" Position [85, 438, 115, 452] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "byte" SID "1175" Position [85, 378, 115, 392] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rst" SID "1176" Position [85, 408, 115, 422] Port "4" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "1177" Ports [0, 1] Position [155, 759, 180, 781] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "1178" Ports [0, 1] Position [155, 809, 180, 831] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "1179" Ports [0, 1] Position [155, 484, 180, 506] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DOUT" SID "1180" Ports [3, 1] Position [425, 443, 460, 487] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('6B')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT1" SID "1181" Ports [3, 1] Position [425, 718, 460, 762] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('07')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "DOUT2" SID "1182" Ports [3, 1] Position [425, 768, 460, 812] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "hex2dec('00')" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,44,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 44 44 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[27.55 27." "55 32.55 27.55 32.55 32.55 32.55 27.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[22.55 22.55 27.55 2" "7.55 22.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[17.55 17.55 22.55 22.55 17.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[12.55 12.55 17.55 12.55 17.55 17.55 12.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'e" "n');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "1183" Ports [1, 1] Position [425, 981, 455, 1009] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "1184" Position [985, 549, 1135, 571] ZOrder -9 ShowName off GotoTag "LAST_SIG_BYTE_DONE" } Block { BlockType From Name "From1" SID "1185" Position [990, 724, 1140, 746] ZOrder -9 ShowName off GotoTag "LAST_SIG_BYTE_DONE" } Block { BlockType From Name "From2" SID "1186" Position [1020, 119, 1170, 141] ZOrder -9 ShowName off GotoTag "LAST_SIG_BYTE_DONE" } Block { BlockType Goto Name "Goto2" SID "1187" Position [505, 985, 645, 1005] ShowName off GotoTag "LAST_SIG_BYTE_DONE" TagVisibility "local" } Block { BlockType Reference Name "Inverter3" SID "1188" Ports [1, 1] Position [945, 601, 975, 619] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter4" SID "1189" Ports [1, 1] Position [1120, 706, 1150, 724] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "LENGTH" SID "1190" Ports [3, 1] Position [540, 703, 650, 807] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off Port { PortNumber 1 Name "Length" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "LENGTH" Location [380, 118, 2362, 1458] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "B0" SID "1191" Position [305, 588, 335, 602] IconDisplay "Port number" } Block { BlockType Inport Name "B1" SID "1192" Position [305, 553, 335, 567] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B2" SID "1193" Position [305, 518, 335, 532] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "1LSB" SID "1194" Ports [1, 1] Position [380, 517, 420, 533] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "3MSB" SID "1195" Ports [1, 1] Position [380, 587, 420, 603] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "1196" Ports [3, 1] Position [470, 506, 500, 614] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "30,108,3,1,white,blue,0,61ef8218,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 108 108 0 ],[0.77 0." "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 108 108 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[58.44 " "58.44 62.44 58.44 62.44 62.44 62.44 58.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[54.44 54.44 58.44 58" ".44 54.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[50.44 50.44 54.44 54.44 50.44 ],[1 1 1 ])" ";\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[46.44 46.44 50.44 46.44 50.44 50.44 46.44 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'hi');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Length" SID "1197" Position [1110, 553, 1140, 567] IconDisplay "Port number" } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Length" DstPort 1 } Line { SrcBlock "1LSB" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "3MSB" SrcPort 1 DstBlock "Concat" DstPort 3 } Line { SrcBlock "B1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "B2" SrcPort 1 DstBlock "1LSB" DstPort 1 } Line { SrcBlock "B0" SrcPort 1 DstBlock "3MSB" DstPort 1 } } } Block { BlockType Reference Name "Logical" SID "1198" Ports [2, 1] Position [350, 788, 375, 817] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1199" Ports [2, 1] Position [350, 738, 375, 767] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1200" Ports [2, 1] Position [350, 463, 375, 492] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "25,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 29 29 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 " "17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33" " 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1201" Ports [2, 1] Position [1185, 550, 1225, 590] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "1202" Ports [2, 1] Position [1025, 600, 1065, 640] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "1203" Ports [2, 1] Position [1185, 705, 1225, 745] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "RATE Decode" SID "1204" Ports [1, 8] Position [535, 349, 655, 581] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RATE Decode" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "B0" SID "1205" Position [85, 128, 115, 142] IconDisplay "Port number" } Block { BlockType Reference Name "3LSB" SID "1206" Ports [1, 1] Position [245, 182, 285, 198] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB" SID "1207" Ports [1, 1] Position [170, 127, 210, 143] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant17" SID "1208" Ports [0, 1] Position [250, 267, 275, 283] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant18" SID "1209" Ports [0, 1] Position [250, 327, 275, 343] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant19" SID "1210" Ports [0, 1] Position [250, 252, 275, 268] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant20" SID "1211" Ports [0, 1] Position [250, 312, 275, 328] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant21" SID "1212" Ports [0, 1] Position [250, 237, 275, 253] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant22" SID "1213" Ports [0, 1] Position [250, 297, 275, 313] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant23" SID "1214" Ports [0, 1] Position [250, 222, 275, 238] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant24" SID "1215" Ports [0, 1] Position [250, 282, 275, 298] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,16,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10" ".22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22" " 8.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'7');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "MSB" SID "1216" Ports [1, 1] Position [590, 127, 630, 143] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "1217" Ports [9, 1] Position [330, 195, 365, 355] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,160,9,1,white,blue,3,9717d9a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 22.8571 137.143 160 0 " "],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 22.8571 137.143 160 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 1" "0.875 5.875 ],[85.55 85.55 90.55 85.55 90.55 90.55 90.55 85.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.87" "5 ],[80.55 80.55 85.55 85.55 80.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[75.55 75.55 " "80.55 80.55 75.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[70.55 70.55 75.55 70.55 75.55 " "75.55 70.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon" " text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'" "d3');\ncolor('black');port_label('input',6,'d4');\ncolor('black');port_label('input',7,'d5');\ncolor('black');po" "rt_label('input',8,'d6');\ncolor('black');port_label('input',9,'d7');\n\ncolor('black');disp('\\bf{}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "ROM" SID "1218" Ports [1, 1] Position [430, 312, 490, 368] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "numel(mcs_rom_11ag)" initVector "mcs_rom_11ag" distributed_mem "Block RAM" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "60,56,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36" ".88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36." "88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]" ");\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text')" ";" } Block { BlockType Reference Name "b[0]" SID "1219" Ports [1, 1] Position [590, 332, 630, 348] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[16:7]" SID "1220" Ports [1, 1] Position [590, 487, 630, 503] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[26:17]" SID "1221" Ports [1, 1] Position [590, 527, 630, 543] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "17" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[2:1]" SID "1222" Ports [1, 1] Position [590, 367, 630, 383] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[4:3]" SID "1223" Ports [1, 1] Position [590, 407, 630, 423] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6:5]" SID "1224" Ports [1, 1] Position [590, 447, 630, 463] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "MCS" SID "1225" Position [700, 268, 730, 282] IconDisplay "Port number" } Block { BlockType Outport Name "mod_sel" SID "1226" Position [700, 408, 730, 422] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "code_rate" SID "1227" Position [700, 448, 730, 462] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "N_CBPS" SID "1228" Position [700, 488, 730, 502] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "N_DBPS" SID "1229" Position [700, 528, 730, 542] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "N_SS" SID "1230" Position [700, 368, 730, 382] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "Chan_BW" SID "1231" Position [700, 333, 730, 347] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "RATE Valid" SID "1232" Position [700, 128, 730, 142] Port "8" IconDisplay "Port number" } Line { SrcBlock "MSB" SrcPort 1 DstBlock "RATE Valid" DstPort 1 } Line { SrcBlock "B0" SrcPort 1 DstBlock "4LSB" DstPort 1 } Line { SrcBlock "4LSB" SrcPort 1 Points [10, 0] Branch { DstBlock "MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "3LSB" DstPort 1 } } Line { SrcBlock "Constant24" SrcPort 1 DstBlock "Mux3" DstPort 6 } Line { SrcBlock "Constant23" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Constant22" SrcPort 1 DstBlock "Mux3" DstPort 7 } Line { SrcBlock "Constant21" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Constant20" SrcPort 1 DstBlock "Mux3" DstPort 8 } Line { SrcBlock "Constant19" SrcPort 1 DstBlock "Mux3" DstPort 4 } Line { SrcBlock "Constant18" SrcPort 1 DstBlock "Mux3" DstPort 9 } Line { SrcBlock "Constant17" SrcPort 1 DstBlock "Mux3" DstPort 5 } Line { SrcBlock "Mux3" SrcPort 1 Points [20, 0] Branch { DstBlock "MCS" DstPort 1 } Branch { Points [0, 65] DstBlock "ROM" DstPort 1 } } Line { SrcBlock "ROM" SrcPort 1 Points [65, 0] Branch { DstBlock "b[0]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[2:1]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[4:3]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[6:5]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[16:7]" DstPort 1 } Branch { Points [0, 40] DstBlock "b[26:17]" DstPort 1 } } } } } } Line { SrcBlock "b[6:5]" SrcPort 1 DstBlock "code_rate" DstPort 1 } Line { SrcBlock "b[4:3]" SrcPort 1 DstBlock "mod_sel" DstPort 1 } Line { SrcBlock "b[0]" SrcPort 1 DstBlock "Chan_BW" DstPort 1 } Line { SrcBlock "b[26:17]" SrcPort 1 DstBlock "N_DBPS" DstPort 1 } Line { SrcBlock "b[16:7]" SrcPort 1 DstBlock "N_CBPS" DstPort 1 } Line { SrcBlock "b[2:1]" SrcPort 1 DstBlock "N_SS" DstPort 1 } Line { SrcBlock "3LSB" SrcPort 1 Points [0, 25] DstBlock "Mux3" DstPort 1 } Annotation { Name "Bit R4 is 1 for all valid rate codes" Position [650, 106] } Annotation { Name "Define MCS index values for 11a/g rates\nThese MCS values are not from the standard,\nbut are used th" "roughout this ref design for\nsanity's sake." Position [412, 238] HorizontalAlignment "left" } Annotation { Name "IEEE 802.11-2012 Table 18-6:\n[R4:R1]:\n1011: BPSK 1/2\n1111: BPSK 3/4\n1010: QPSK 1/2\n1110: QPSK 3/" "4\n1001: 16-QAM 1/2\n1101: 16-QAM 3/4\n1000: 64-QAM 2/3\n1100: 64-QAM 3/4\n\nMod Order values:\n0: BPSK\n1: QPSK" "\n2: 16-QAM\n3: 64-QAM\n\nCode Rate values:\n0: 1/2\n1: 2/3\n2: 3/4\n3: 5/6 (HT/VHT only)\n\nN_DBPS values:\nBPS" "K 1/2: 24\nBPSK 3/4: 36\nQPSK 1/2: 48\nQPSK 3/4: 72\n16-QAM 1/2: 96\n16-QAM 3/4: 144\n64-QAM 2/3: 192\n64-QAM 3/" "4: 216" Position [820, 472] HorizontalAlignment "left" } Annotation { Name "% Ouptut word contents:\n% b[ 0]: Chan bandwidth\n% b[ 2: 1]: Num spatial streams\n% b[ 4: 3]: " "Mod order index\n% b[ 6: 5]: Code rate index\n% b[16: 7]: Coded bits per symbol per stream\n% b[26:17]: Data " "bits per symbol per stream" Position [410, 668] HorizontalAlignment "left" FontName "Consolas" FontSize 12 } } } Block { BlockType Reference Name "Relational" SID "1233" Ports [2, 1] Position [265, 740, 300, 780] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "1234" Ports [2, 1] Position [265, 790, 300, 830] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "1235" Ports [2, 1] Position [265, 465, 300, 505] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "SIGNAL Dec" SID "1236" Ports [8] Position [1440, 122, 1475, 243] ZOrder -3 Floating off Location [1305, 473, 2353, 1516] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "1000" YMin "0~-1~-1~-1~52~-1~0~0" YMax "1~1~1~1~60~1~1~30" SaveName "ScopeData18" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Tail & Parity Check" SID "1237" Ports [3, 1] Position [540, 839, 650, 891] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Tail & Parity Check" Location [380, 118, 2362, 1458] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "112" Block { BlockType Inport Name "B0" SID "1238" Position [375, 258, 405, 272] IconDisplay "Port number" } Block { BlockType Inport Name "B1" SID "1239" Position [375, 303, 405, 317] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B2" SID "1240" Position [375, 348, 405, 362] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "2LSB" SID "1241" Ports [1, 1] Position [460, 347, 500, 363] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "2" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "2b XOR" SID "1242" Ports [1, 1] Position [555, 340, 600, 370] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "2b XOR" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "1243" Position [100, 38, 130, 52] IconDisplay "Port number" } Block { BlockType Reference Name "Logical" SID "1244" Ports [2, 1] Position [270, 26, 310, 99] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,73,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 73 73 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 73 73 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[41.55 41." "55 46.55 41.55 46.55 46.55 46.55 41.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[36.55 36.55 41.55 4" "1.55 36.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[31.55 31.55 36.55 36.55 31.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 26.55 31.55 31.55 26.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "1245" Ports [1, 1] Position [185, 36, 225, 54] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "1246" Ports [1, 1] Position [185, 71, 225, 89] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "B" SID "1247" Position [355, 53, 385, 67] IconDisplay "Port number" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "B" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { Points [0, 35] DstBlock "b1" DstPort 1 } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType Reference Name "6MSB" SID "1248" Ports [1, 1] Position [460, 452, 500, 468] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "8b XOR 1" SID "1249" Ports [1, 1] Position [555, 250, 600, 280] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "8b XOR 1" Location [428, 592, 836, 929] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "1250" Position [100, 38, 130, 52] IconDisplay "Port number" } Block { BlockType Reference Name "Logical" SID "1251" Ports [8, 1] Position [285, 25, 330, 310] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,285,8,1,white,blue,0,3d04c15b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 285 285 0 ],[0.77 0." "82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 285 285 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[148" ".66 148.66 154.66 148.66 154.66 154.66 154.66 148.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[142.66" " 142.66 148.66 148.66 142.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[136.66 136.66 142.6" "6 142.66 136.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[130.66 130.66 136.66 130.66 136" ".66 136.66 130.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\n\n\n\n\n\n\n\n\n\ncolor('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "1252" Ports [1, 1] Position [185, 36, 225, 54] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "1253" Ports [1, 1] Position [185, 71, 225, 89] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "1254" Ports [1, 1] Position [185, 106, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "1255" Ports [1, 1] Position [185, 141, 225, 159] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "1256" Ports [1, 1] Position [185, 176, 225, 194] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "1257" Ports [1, 1] Position [185, 211, 225, 229] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "1258" Ports [1, 1] Position [185, 246, 225, 264] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "1259" Ports [1, 1] Position [185, 281, 225, 299] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "B" SID "1260" Position [355, 163, 385, 177] IconDisplay "Port number" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "B" DstPort 1 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Logical" DstPort 8 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Logical" DstPort 7 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Logical" DstPort 6 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Logical" DstPort 5 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Logical" DstPort 4 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Logical" DstPort 3 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "b0" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { Points [0, 35] Branch { DstBlock "b6" DstPort 1 } Branch { Points [0, 35] DstBlock "b7" DstPort 1 } } Branch { DstBlock "b5" DstPort 1 } } Branch { DstBlock "b4" DstPort 1 } } Branch { DstBlock "b3" DstPort 1 } } Branch { DstBlock "b2" DstPort 1 } } Branch { DstBlock "b1" DstPort 1 } } Branch { DstBlock "b0" DstPort 1 } } } } Block { BlockType SubSystem Name "8b XOR 2" SID "1261" Ports [1, 1] Position [555, 295, 600, 325] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "8b XOR 2" Location [36, 222, 2218, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" SID "1262" Position [100, 38, 130, 52] IconDisplay "Port number" } Block { BlockType Reference Name "Logical" SID "1263" Ports [8, 1] Position [285, 25, 330, 310] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,285,8,1,white,blue,0,3d04c15b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 285 285 0 ],[0.77 0." "82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 285 285 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[148" ".66 148.66 154.66 148.66 154.66 154.66 154.66 148.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[142.66" " 142.66 148.66 148.66 142.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[136.66 136.66 142.6" "6 142.66 136.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[130.66 130.66 136.66 130.66 136" ".66 136.66 130.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\n\n\n\n\n\n\n\n\n\ncolor('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "1264" Ports [1, 1] Position [185, 36, 225, 54] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "1265" Ports [1, 1] Position [185, 71, 225, 89] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "1266" Ports [1, 1] Position [185, 106, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "1267" Ports [1, 1] Position [185, 141, 225, 159] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b4" SID "1268" Ports [1, 1] Position [185, 176, 225, 194] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b5" SID "1269" Ports [1, 1] Position [185, 211, 225, 229] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b6" SID "1270" Ports [1, 1] Position [185, 246, 225, 264] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b7" SID "1271" Ports [1, 1] Position [185, 281, 225, 299] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output " "type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "B" SID "1272" Position [355, 163, 385, 177] IconDisplay "Port number" } Line { SrcBlock "A" SrcPort 1 Points [15, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b3" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b4" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b5" DstPort 1 } Branch { Points [0, 35] Branch { Points [0, 35] DstBlock "b7" DstPort 1 } Branch { DstBlock "b6" DstPort 1 } } } } } } } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Logical" DstPort 3 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Logical" DstPort 4 } Line { SrcBlock "b4" SrcPort 1 DstBlock "Logical" DstPort 5 } Line { SrcBlock "b5" SrcPort 1 DstBlock "Logical" DstPort 6 } Line { SrcBlock "b6" SrcPort 1 DstBlock "Logical" DstPort 7 } Line { SrcBlock "b7" SrcPort 1 DstBlock "Logical" DstPort 8 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "B" DstPort 1 } } } Block { BlockType Reference Name "Constant1" SID "1273" Ports [0, 1] Position [615, 469, 640, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1274" Ports [1, 1] Position [785, 301, 810, 319] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "1275" Ports [3, 1] Position [680, 240, 715, 380] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,140,3,1,white,blue,0,86aed425,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 140 140 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 140 140 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[75.55" " 75.55 80.55 75.55 80.55 80.55 80.55 75.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[70.55 70.55 75." "55 75.55 70.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[65.55 65.55 70.55 70.55 65.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[60.55 60.55 65.55 60.55 65.55 65.55 60.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\nco" "lor('black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "1276" Ports [2, 1] Position [935, 300, 975, 340] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,40,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 40 40 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('b" "lack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "1277" Ports [2, 1] Position [680, 450, 715, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,40,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 40 40 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 40 40 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[25.55 25." "55 30.55 25.55 30.55 30.55 30.55 25.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 2" "5.55 20.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[15.55 15.55 20.55 20.55 15.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[10.55 10.55 15.55 10.55 15.55 15.55 10.55 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black')" ";port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Invalid" SID "1278" Position [1025, 313, 1055, 327] IconDisplay "Port number" } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Invalid" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [105, 0; 0, -140] DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "6MSB" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "B2" SrcPort 1 Points [20, 0] Branch { Points [0, 105] DstBlock "6MSB" DstPort 1 } Branch { DstBlock "2LSB" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "2b XOR" SrcPort 1 DstBlock "Logical" DstPort 3 } Line { SrcBlock "8b XOR 2" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "8b XOR 1" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "2LSB" SrcPort 1 DstBlock "2b XOR" DstPort 1 } Line { SrcBlock "B1" SrcPort 1 DstBlock "8b XOR 2" DstPort 1 } Line { SrcBlock "B0" SrcPort 1 DstBlock "8b XOR 1" DstPort 1 } Annotation { Name "SIGNAL field parity bit assures first 17 bits\n(RATE, LENGTH and PARITY) XOR to 0\n(a.k.a. even parit" "y)" Position [594, 416] } } } Block { BlockType Reference Name "int" SID "1279" Ports [1, 1] Position [1275, 123, 1310, 137] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "SIG Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int1" SID "1280" Ports [1, 1] Position [1275, 138, 1310, 152] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "MCS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int2" SID "1281" Ports [1, 1] Position [1275, 153, 1310, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Mod order" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int3" SID "1282" Ports [1, 1] Position [1275, 168, 1310, 182] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Code rate" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int4" SID "1283" Ports [1, 1] Position [1275, 198, 1310, 212] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "SIG Invalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int5" SID "1284" Ports [1, 1] Position [1275, 213, 1310, 227] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "SIG Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int6" SID "1285" Ports [1, 1] Position [1275, 183, 1310, 197] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "Length" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "int7" SID "1286" Ports [1, 1] Position [1275, 228, 1310, 242] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "N_DBPS" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Outport Name "SIGNAL Valid" SID "1287" Position [1285, 718, 1315, 732] IconDisplay "Port number" } Block { BlockType Outport Name "SIGNAL Invalid" SID "1288" Position [1290, 563, 1320, 577] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Length" SID "1289" Position [915, 748, 945, 762] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "MCS" SID "1290" Position [805, 353, 835, 367] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "mod_sel" SID "1291" Position [805, 383, 835, 397] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name "code_rate" SID "1292" Position [805, 413, 835, 427] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name "Chan_BW" SID "1293" Position [805, 533, 835, 547] Port "7" IconDisplay "Port number" } Block { BlockType Outport Name "N_DBPS" SID "1294" Position [805, 473, 835, 487] Port "8" IconDisplay "Port number" } Block { BlockType Outport Name "N_CBPS" SID "1295" Position [805, 443, 835, 457] Port "9" IconDisplay "Port number" } Block { BlockType Outport Name "N_SS" SID "1296" Position [805, 503, 835, 517] Port "10" IconDisplay "Port number" } Block { BlockType Outport Name "SIGNAL Done" SID "1297" Position [915, 1018, 945, 1032] Port "11" IconDisplay "Port number" } Line { SrcBlock "DOUT2" SrcPort 1 Points [10, 0] Branch { Points [0, 90] DstBlock "Tail & Parity Check" DstPort 3 } Branch { DstBlock "LENGTH" DstPort 3 } } Line { SrcBlock "DOUT1" SrcPort 1 Points [20, 0] Branch { Points [0, 125] DstBlock "Tail & Parity Check" DstPort 2 } Branch { Points [40, 0] DstBlock "LENGTH" DstPort 2 } } Line { SrcBlock "DOUT" SrcPort 1 Points [25, 0] Branch { Points [0, 255] Branch { Points [0, 130] DstBlock "Tail & Parity Check" DstPort 1 } Branch { DstBlock "LENGTH" DstPort 1 } } Branch { DstBlock "RATE Decode" DstPort 1 } } Line { SrcBlock "rst" SrcPort 1 Points [270, 0; 0, 50] Branch { DstBlock "DOUT" DstPort 2 } Branch { Points [0, 275] Branch { DstBlock "DOUT1" DstPort 2 } Branch { Points [0, 50] DstBlock "DOUT2" DstPort 2 } } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "DOUT1" DstPort 3 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "DOUT" DstPort 3 } Line { SrcBlock "Logical" SrcPort 1 Points [15, 0] Branch { DstBlock "DOUT2" DstPort 3 } Branch { Points [0, 190] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "byte" SrcPort 1 Points [280, 0; 0, 65] Branch { Points [0, 275] Branch { Points [0, 50] DstBlock "DOUT2" DstPort 1 } Branch { DstBlock "DOUT1" DstPort 1 } } Branch { DstBlock "DOUT" DstPort 1 } } Line { SrcBlock "byte_ind" SrcPort 1 Points [115, 0] Branch { Points [0, 275] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 50] DstBlock "Relational1" DstPort 1 } } Branch { DstBlock "Relational2" DstPort 1 } } Line { Labels [0, 0] SrcBlock "byte_valid" SrcPort 1 Points [205, 0; 0, 25] Branch { Points [0, 275] Branch { Points [0, 50] DstBlock "Logical" DstPort 1 } Branch { DstBlock "Logical1" DstPort 1 } } Branch { DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [15, 0] Branch { DstBlock "Goto2" DstPort 1 } Branch { Points [0, 30] DstBlock "SIGNAL Done" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 1 Points [70, 0] Branch { DstBlock "MCS" DstPort 1 } Branch { Points [0, -215] DstBlock "int1" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 2 Points [75, 0] Branch { DstBlock "mod_sel" DstPort 1 } Branch { Points [0, -230] DstBlock "int2" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 3 Points [80, 0] Branch { DstBlock "code_rate" DstPort 1 } Branch { Points [0, -245] DstBlock "int3" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 4 DstBlock "N_CBPS" DstPort 1 } Line { SrcBlock "RATE Decode" SrcPort 5 Points [85, 0] Branch { DstBlock "N_DBPS" DstPort 1 } Branch { Points [0, -245] DstBlock "int7" DstPort 1 } } Line { SrcBlock "RATE Decode" SrcPort 6 DstBlock "N_SS" DstPort 1 } Line { SrcBlock "RATE Decode" SrcPort 7 DstBlock "Chan_BW" DstPort 1 } Line { SrcBlock "RATE Decode" SrcPort 8 Points [100, 0; 0, 40] DstBlock "Inverter3" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [20, 0] Branch { DstBlock "SIGNAL Invalid" DstPort 1 } Branch { Points [0, -365] DstBlock "int4" DstPort 1 } } Line { SrcBlock "Inverter3" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Tail & Parity Check" SrcPort 1 Points [115, 0; 0, -235] DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 Points [15, 0] Branch { Points [0, -40] DstBlock "Logical3" DstPort 2 } Branch { Points [0, 95] DstBlock "Inverter4" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "Inverter4" SrcPort 1 DstBlock "Logical6" DstPort 1 } Line { SrcBlock "Logical6" SrcPort 1 Points [25, 0] Branch { DstBlock "SIGNAL Valid" DstPort 1 } Branch { Points [0, -505] DstBlock "int5" DstPort 1 } } Line { Name "Length" Labels [0, 0] SrcBlock "LENGTH" SrcPort 1 Points [210, 0] Branch { DstBlock "Length" DstPort 1 } Branch { Points [0, -565] DstBlock "int6" DstPort 1 } } Line { Name "SIG Done" Labels [0, 0] SrcBlock "int" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "int" DstPort 1 } Line { Name "Mod order" Labels [0, 0] SrcBlock "int2" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 3 } Line { Name "MCS" Labels [0, 0] SrcBlock "int1" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 2 } Line { Name "Code rate" Labels [0, 0] SrcBlock "int3" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 4 } Line { Name "SIG Invalid" Labels [0, 0] SrcBlock "int4" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 6 } Line { Name "SIG Valid" Labels [0, 0] SrcBlock "int5" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 7 } Line { Name "Length" Labels [0, 0] SrcBlock "int6" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 5 } Line { Name "N_DBPS" Labels [0, 0] SrcBlock "int7" SrcPort 1 DstBlock "SIGNAL Dec" DstPort 8 } Annotation { Name "Init values of these regs are important - output\nis valid SIGNAL field value on reset." Position [134, 916] HorizontalAlignment "left" } } } Block { BlockType Scope Name "SIGNAL Decode1" SID "2171" Ports [4] Position [1695, 657, 1750, 728] ZOrder -3 Floating off Location [163, 715, 1338, 1572] Open off NumInputPorts "4" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "11440" YMin "-5~-5~-5~-5" YMax "5~5~5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "HT-SIG Bytes" SID "2720" Position [655, 318, 685, 332] IconDisplay "Port number" } Block { BlockType Outport Name "Reset PHY" SID "1298" Position [1555, 853, 1585, 867] Port "2" IconDisplay "Port number" } Line { SrcBlock "Byte Ind" SrcPort 1 Points [55, 0] Branch { DstBlock "SIGNAL Decode" DstPort 1 } Branch { Points [0, 210] DstBlock "HT-SIG Decode" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 Points [50, 0] Branch { DstBlock "SIGNAL Decode" DstPort 2 } Branch { Points [0, 220] DstBlock "HT-SIG Decode" DstPort 2 } } Line { SrcBlock "Byte" SrcPort 1 Points [45, 0] Branch { DstBlock "SIGNAL Decode" DstPort 3 } Branch { Points [0, 230] DstBlock "HT-SIG Decode" DstPort 3 } } Line { SrcBlock "From" SrcPort 1 Points [100, 0] Branch { DstBlock "SIGNAL Decode" DstPort 4 } Branch { Points [0, 240] Branch { DstBlock "HT-SIG Decode" DstPort 4 } Branch { Points [0, 170] DstBlock "S-R Latch1" DstPort 2 } } } Line { SrcBlock "SIGNAL Decode" SrcPort 3 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 4 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 5 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 1 Points [40, 0] Branch { DstBlock "Goto2" DstPort 1 } Branch { Points [0, 555] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "SIGNAL Decode" SrcPort 2 Points [35, 0] Branch { DstBlock "Goto1" DstPort 1 } Branch { Points [0, 555] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "SIGNAL Decode" SrcPort 6 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 7 DstBlock "Goto20" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 8 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 9 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "SIGNAL Decode" SrcPort 10 DstBlock "Goto19" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 2 DstBlock "Goto24" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 3 DstBlock "Goto25" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 4 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 5 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 6 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 7 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 8 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 9 DstBlock "Goto21" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 10 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 11 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 12 DstBlock "Goto18" DstPort 1 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Register11" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Mux7" DstPort 2 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Mux7" DstPort 3 } Line { SrcBlock "Mux7" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Mux8" DstPort 2 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Mux8" DstPort 3 } Line { SrcBlock "Mux8" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Mux9" DstPort 2 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Mux9" DstPort 3 } Line { SrcBlock "Mux9" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [235, 0; 0, -90] Branch { DstBlock "Mux3" DstPort 1 } Branch { Points [0, -115] Branch { Points [0, -70] Branch { DstBlock "Mux9" DstPort 1 } Branch { Points [0, -85] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, -75] Branch { DstBlock "Mux8" DstPort 1 } Branch { Points [0, -75] Branch { DstBlock "Mux7" DstPort 1 } Branch { Points [0, -75] DstBlock "Mux4" DstPort 1 } } } } } Branch { DstBlock "Mux5" DstPort 1 } } } Line { SrcBlock "From18" SrcPort 1 DstBlock "Mux4" DstPort 2 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Mux4" DstPort 3 } Line { SrcBlock "Mux4" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "HT-SIG Decode" SrcPort 13 DstBlock "Goto30" DstPort 1 } Line { SrcBlock "From30" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From24" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "From25" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Logical4" DstPort 3 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Reset PHY" DstPort 1 } Line { SrcBlock "From27" SrcPort 1 DstBlock "Mux5" DstPort 2 } Line { SrcBlock "From28" SrcPort 1 DstBlock "Mux5" DstPort 3 } Line { SrcBlock "Mux5" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { SrcBlock "From29" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "From26" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "From23" SrcPort 1 DstBlock "Logical1" DstPort 3 } Line { SrcBlock "SIGNAL Decode" SrcPort 11 DstBlock "Goto36" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto27" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Goto22" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Goto26" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 Points [30, 0] Branch { DstBlock "Goto3" DstPort 1 } Branch { Points [0, 615] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Goto28" DstPort 1 } Line { SrcBlock "Register10" SrcPort 1 DstBlock "Goto34" DstPort 1 } Line { SrcBlock "Register11" SrcPort 1 Points [25, 0] Branch { DstBlock "Goto5" DstPort 1 } Branch { Points [0, 135] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "SIGNAL Decode1" DstPort 2 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "SIGNAL Decode1" DstPort 1 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "SIGNAL Decode1" DstPort 3 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "SIGNAL Decode1" DstPort 4 } Line { SrcBlock "HT-SIG Decode" SrcPort 1 DstBlock "HT-SIG Bytes" DstPort 1 } Annotation { Name "Switch to HT-SIG values only for\n11n waveforms with valid HT-SIG fields" Position [626, 599] } } } Block { BlockType SubSystem Name "Scrambling" SID "1299" Ports [3, 1] Position [1350, 335, 1450, 395] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Scrambling" Location [-1678, 227, -2, 1187] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Bit Valid" SID "1300" Position [440, 403, 470, 417] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Unscrambled" SID "1301" Position [440, 428, 470, 442] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Bit" SID "1302" Position [440, 493, 470, 507] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Convert2" SID "1303" Ports [1, 1] Position [715, 476, 745, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "1304" Ports [1, 1] Position [520, 425, 550, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "1305" Ports [2, 1] Position [875, 462, 915, 513] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,51,2,1,white,blue,0,dc21e094,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 51 51 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[30.55 30.55 35." "55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[25.55 25.55 30.55 30.55 25." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[20.55 20.55 25.55 25.55 20.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('x" "or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1306" Ports [2, 1] Position [620, 398, 655, 447] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,49,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 49 49 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[29.55 29.55 34." "55 29.55 34.55 34.55 34.55 29.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[24.55 24.55 29.55 29.55 24." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[19.55 19.55 24.55 24.55 19.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[14.55 14.55 19.55 14.55 19.55 19.55 14.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1307" Ports [2, 1] Position [800, 448, 835, 497] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,49,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 49 49 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[29.55 29.55 34." "55 29.55 34.55 34.55 34.55 29.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[24.55 24.55 29.55 29.55 24." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[19.55 19.55 24.55 24.55 19.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[14.55 14.55 19.55 14.55 19.55 19.55 14.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Scrambling LFSR" SID "1308" Ports [1, 1] Position [700, 408, 760, 442] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Scrambling LFSR" Location [-1678, 227, -2, 1187] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "en" SID "1309" Position [405, 458, 435, 472] IconDisplay "Port number" } Block { BlockType Reference Name "Assert" SID "1310" Ports [1, 1] Position [845, 192, 890, 208] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware th" "is block costs nothing." assert_type on type_source "Explicitly" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,436" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,9657e937,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "1311" Ports [1, 1] Position [845, 212, 890, 228] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware this" " block costs nothing." assert_type on type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "20,20,356,436" block_type "assert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,16,1,1,white,blue,0,9657e937,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22" " 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22" " 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 " "]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');dis" "p('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "1312" Ports [1, 1] Position [485, 430, 510, 450] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1313" Ports [1, 1] Position [485, 455, 510, 475] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12" ".22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12." "22 10.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1314" Ports [1, 1] Position [635, 106, 665, 124] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22" " 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_" "label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "1315" Position [90, 418, 285, 442] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType From Name "From2" SID "1316" Position [90, 438, 290, 462] ZOrder -9 ShowName off GotoTag "regTx_Reset_Scrambling_LFSR_PerPkt" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "1317" Ports [2, 1] Position [755, 188, 800, 232] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "XOR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,dc21e094,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('xor');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1318" Ports [2, 1] Position [340, 418, 385, 462] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "1319" Ports [3, 1] Position [580, 261, 625, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "1320" Ports [3, 1] Position [665, 261, 710, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1321" Ports [3, 1] Position [755, 261, 800, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "1322" Ports [3, 1] Position [845, 261, 890, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "1323" Ports [3, 1] Position [1005, 261, 1050, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "1324" Ports [3, 1] Position [1095, 261, 1140, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "1325" Ports [3, 1] Position [1180, 261, 1225, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "1" rst on en on dbl_ovrd off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1326" Position [765, 108, 795, 122] NamePlacement "alternate" IconDisplay "Port number" } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 Points [20, 0; 0, -85] DstBlock "Assert" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [-225, 0] Branch { Points [0, -95] DstBlock "Convert2" DstPort 1 } Branch { Points [0, 60] DstBlock "Register" DstPort 1 } } Line { SrcBlock "Register5" SrcPort 1 Points [0, -15] DstBlock "Register6" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 Points [45, 0; 0, -15] Branch { Points [0, -50] DstBlock "Assert1" DstPort 1 } Branch { DstBlock "Register4" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 Points [10, 0; 0, -15] DstBlock "Register3" DstPort 1 } Line { Labels [0, 0] SrcBlock "Register1" SrcPort 1 Points [0, -15] DstBlock "Register2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [5, 0; 0, -15] DstBlock "Register1" DstPort 1 } Line { SrcBlock "Assert" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Assert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "en" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [30, 0] Branch { Points [95, 0] Branch { Points [80, 0] Branch { Points [100, 0] Branch { Points [150, 0] Branch { Points [100, 0] Branch { Points [0, -155] DstBlock "Register5" DstPort 2 } Branch { Labels [2, 0] Points [80, 0; 0, -155] DstBlock "Register6" DstPort 2 } } Branch { Points [0, -155] DstBlock "Register4" DstPort 2 } } Branch { Points [0, -155] DstBlock "Register3" DstPort 2 } } Branch { Points [0, -155] DstBlock "Register2" DstPort 2 } } Branch { Points [0, -155] DstBlock "Register1" DstPort 2 } } Branch { Points [0, -155] DstBlock "Register" DstPort 2 } } Line { SrcBlock "Convert1" SrcPort 1 Points [40, 0] Branch { Points [95, 0] Branch { Points [80, 0] Branch { Points [100, 0] Branch { Points [150, 0] Branch { Points [100, 0] Branch { DstBlock "Register5" DstPort 3 } Branch { Points [75, 0; 0, -165] DstBlock "Register6" DstPort 3 } } Branch { Points [0, -165] DstBlock "Register4" DstPort 3 } } Branch { DstBlock "Register3" DstPort 3 } } Branch { Points [0, -165] DstBlock "Register2" DstPort 3 } } Branch { DstBlock "Register1" DstPort 3 } } Branch { Points [0, -165] DstBlock "Register" DstPort 3 } } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical1" DstPort 2 } Annotation { Position [1228, 301] } Annotation { Name "The standard suggests setting the state of the Tx LFSR to a pseudo-random value for\neach new transmi" "ssion. We implement this by not resetting the LFSR state between\ntransmissions. The reset-per-packet can be ena" "bled by software if required by\na custom application (i.e. if you need to generate the same waveform for a give" "n\npayload many times)." Position [98, 528] HorizontalAlignment "left" } } } Block { BlockType Outport Name "Tx Bit" SID "1327" Position [1000, 483, 1030, 497] IconDisplay "Port number" } Line { SrcBlock "Inverter1" SrcPort 1 Points [30, 0] Branch { DstBlock "Logical2" DstPort 2 } Branch { Points [0, 50] DstBlock "Convert2" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Scrambling LFSR" DstPort 1 } Line { SrcBlock "Scrambling LFSR" SrcPort 1 Points [20, 0] DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Tx Bit" DstPort 1 } Line { SrcBlock "Bit Valid" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Unscrambled" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Bit" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Logical3" DstPort 2 } Annotation { Name "Increment the LFSR once per scrambled bit. Unscrambled\nbits do not update the LFSR state and are not XO" "R'd with\nthe LFSR output." Position [526, 574] HorizontalAlignment "left" } } } Block { BlockType ToWorkspace Name "To Workspace" SID "2325" Ports [1] Position [1300, 621, 1395, 649] ZOrder -7 ShowName off VariableName "tx_bytes" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "2327" Ports [1] Position [1300, 657, 1395, 683] ZOrder -7 ShowName off VariableName "tx_bytes_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace2" SID "2834" Ports [1] Position [1415, 446, 1510, 474] ZOrder -7 ShowName off VariableName "tx_bits" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace3" SID "2835" Ports [1] Position [1415, 482, 1510, 508] ZOrder -7 ShowName off VariableName "tx_bits_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType SubSystem Name "negedge" SID "1328" Ports [1, 1] Position [690, 223, 735, 237] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [380, 118, 2362, 1458] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1329" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "1330" Ports [1, 1] Position [425, 178, 460, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "1331" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1332" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1333" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -25] DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name " Sym Cfg" SID "1334" Position [1170, 753, 1200, 767] IconDisplay "Port number" } Block { BlockType Outport Name "Tx Bit" SID "1335" Position [1500, 358, 1530, 372] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Tx Bit tvalid" SID "1336" Position [1495, 278, 1525, 292] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Tx Bit tlast" SID "1337" Position [1495, 223, 1525, 237] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "DATA Done" SID "1338" Position [1170, 693, 1200, 707] Port "5" IconDisplay "Port number" } Line { SrcBlock "BRAM IF 64b" SrcPort 1 Points [20, 0] Branch { Labels [0, 0] DstBlock "Byte Src Sel" DstPort 4 } Branch { Points [0, 50] Branch { DstBlock "FCS Calc" DstPort 2 } Branch { Points [0, 85] DstBlock "SIGNAL & HT-SIG\nDecode" DstPort 1 } } } Line { SrcBlock "Delay3" SrcPort 1 Points [55, 0] Branch { Points [0, -30] DstBlock "FCS Calc" DstPort 4 } Branch { Points [0, 65] Branch { DstBlock "SIGNAL & HT-SIG\nDecode" DstPort 3 } Branch { Points [0, 30] DstBlock "Delay16" DstPort 1 } } } Line { SrcBlock "FCS Calc" SrcPort 1 Points [45, 0; 0, -45] DstBlock "Byte Src Sel" DstPort 5 } Line { SrcBlock "Byte Src Sel" SrcPort 1 Points [40, 0] Branch { Points [0, 175] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Bit Select" DstPort 2 } } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Delay13" DstPort 1 } Line { SrcBlock "Byte Ind Valid " SrcPort 1 DstBlock "Delay3" DstPort 1 } Line { SrcBlock "Packet Sections" SrcPort 3 DstBlock "Delay19" DstPort 1 } Line { SrcBlock "Byte Ind" SrcPort 1 Points [40, 0] Branch { Points [80, 0] Branch { Points [0, -30] DstBlock "Packet Sections" DstPort 2 } Branch { Points [190, 0] Branch { DstBlock "BRAM IF 64b" DstPort 1 } Branch { Points [0, 65] DstBlock "Delay1" DstPort 1 } } } Branch { Points [0, -330] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Bit Sel" SrcPort 1 Points [45, 0] Branch { Points [75, 0] Branch { DstBlock "Delay5" DstPort 1 } Branch { Points [0, 55] DstBlock "Packet Sections" DstPort 1 } } Branch { Points [0, -190] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "Delay14" DstPort 1 } Line { SrcBlock "Packet Sections" SrcPort 2 DstBlock "Delay6" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 Points [125, 0; 0, 20] DstBlock "Byte Src Sel" DstPort 1 } Line { SrcBlock "SIGNAL & HT-SIG\nDecode" SrcPort 2 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Bit Sel Valid" SrcPort 1 Points [90, 0] Branch { DstBlock "Delay2" DstPort 1 } Branch { Points [0, -55] Branch { Points [0, -65] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "Delay11" DstPort 1 } } } Line { SrcBlock "Bit Select" SrcPort 1 Points [55, 0] Branch { Points [0, -65] DstBlock "Scrambling" DstPort 3 } Branch { Points [0, 10] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [60, 0] Branch { DstBlock "FCS Calc" DstPort 3 } Branch { Points [0, 90] DstBlock "SIGNAL & HT-SIG\nDecode" DstPort 2 } } Line { SrcBlock "Packet Sections" SrcPort 1 Points [55, 0; 0, -20] DstBlock "Delay4" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Delay15" DstPort 1 } Line { SrcBlock "Scrambling" SrcPort 1 DstBlock "Tx Bit" DstPort 1 } Line { SrcBlock "Delay7" SrcPort 1 DstBlock "Byte Src Sel" DstPort 2 } Line { SrcBlock "Sym Cfg" SrcPort 1 DstBlock "Delay8" DstPort 1 } Line { SrcBlock "Delay8" SrcPort 1 DstBlock "Delay18" DstPort 1 } Line { SrcBlock "Packet Sections" SrcPort 5 Points [20, 0; 0, 255] DstBlock "Delay9" DstPort 1 } Line { SrcBlock "Delay9" SrcPort 1 DstBlock "Delay17" DstPort 1 } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Delay12" DstPort 1 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { Name "Byte Ind" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Pkt Data" DstPort 1 } Line { Name "Bit Sel" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Pkt Data" DstPort 2 } Line { Name "Bit Sel valid" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Pkt Data" DstPort 3 } Line { Name "Tx Bit tvalid" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Pkt Data" DstPort 4 } Line { Name "Tx Bit tlast" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Pkt Data" DstPort 5 } Line { Name "Sym Cfg out" Labels [0, 0] SrcBlock "Gateway Out11" SrcPort 1 DstBlock "Pkt Data" DstPort 6 } Line { SrcBlock "SIGNAL & HT-SIG\nDecode" SrcPort 1 Points [55, 0; 0, -110] DstBlock "Byte Src Sel" DstPort 6 } Line { SrcBlock "Packet Sections" SrcPort 4 DstBlock "Delay20" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "To Workspace2" DstPort 1 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "To Workspace3" DstPort 1 } Line { SrcBlock "Delay10" SrcPort 1 DstBlock "Byte Src Sel" DstPort 3 } Line { SrcBlock "Delay11" SrcPort 1 DstBlock "negedge" DstPort 1 } Line { SrcBlock "Delay12" SrcPort 1 Points [110, 0] Branch { DstBlock "Tx Bit tlast" DstPort 1 } Branch { Points [0, -35] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "Delay13" SrcPort 1 Points [105, 0] Branch { DstBlock "Tx Bit tvalid" DstPort 1 } Branch { Points [0, -105] DstBlock "Gateway Out9" DstPort 1 } Branch { Labels [0, 0] Points [0, 60; 125, 0] Branch { DstBlock "Scrambling" DstPort 1 } Branch { Points [0, 150] DstBlock "Gateway Out2" DstPort 1 } } } Line { SrcBlock "Delay14" SrcPort 1 Points [50, 0; 0, 100] DstBlock "Bit Select" DstPort 1 } Line { SrcBlock "Delay15" SrcPort 1 DstBlock "Scrambling" DstPort 2 } Line { SrcBlock "Delay16" SrcPort 1 DstBlock "Gateway Out6" DstPort 1 } Line { SrcBlock "Delay17" SrcPort 1 DstBlock "DATA Done" DstPort 1 } Line { SrcBlock "Delay18" SrcPort 1 Points [40, 0] Branch { Points [0, -30; 430, 0; 0, -520] DstBlock "Gateway Out11" DstPort 1 } Branch { DstBlock " Sym Cfg" DstPort 1 } } Line { SrcBlock "Delay19" SrcPort 1 Points [155, 0; 0, 20] Branch { Points [0, 65] DstBlock "FCS Calc" DstPort 1 } Branch { DstBlock "Delay7" DstPort 1 } } Line { SrcBlock "Delay20" SrcPort 1 Points [100, 0; 0, 20] DstBlock "Delay10" DstPort 1 } Annotation { Name "Bit Sel Valid asserts once per OFDM sym,\nstays high until end of sym. Use falling edge\nto mark l" "ast bit for downstream logic." Position [714, 195] } } } Block { BlockType SubSystem Name "Puncture & Interleave" SID "1339" Ports [6, 3] Position [995, 350, 1135, 455] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Puncture & Interleave" Location [2, 70, 1833, 1180] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "110" Block { BlockType Inport Name "Data Sym Ind" SID "1340" Position [900, 328, 930, 342] IconDisplay "Port number" } Block { BlockType Inport Name "Sym Cfg" SID "1341" Position [215, 353, 245, 367] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Bit A" SID "1342" Position [645, 163, 675, 177] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Bit B" SID "1343" Position [645, 188, 675, 202] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Bits tvalid" SID "1344" Position [645, 258, 675, 272] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Bits tlast" SID "1345" Position [640, 493, 670, 507] Port "6" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "3601" Ports [2, 1] Position [800, 15, 860, 75] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{" "20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "1346" Ports [1, 1] Position [820, 160, 840, 180] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,20,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 " "12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]" ");\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "1347" Ports [1, 1] Position [820, 185, 840, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "20,20,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 " "12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]" ");\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "1348" Ports [1, 1] Position [815, 431, 845, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "1349" Ports [1, 1] Position [815, 486, 845, 514] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "1350" Ports [1, 1] Position [1240, 486, 1270, 514] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "1351" Ports [2, 1] Position [1240, 438, 1270, 467] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,29,2,1,white,blue,0,7c0ac154,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port" "_label('input',2,'en');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "3603" Ports [1, 1] Position [900, 94, 935, 106] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out7" SID "3600" Ports [1, 1] Position [900, 39, 935, 51] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Interleave RAM" SID "1352" Ports [9, 1] Position [1185, 201, 1325, 389] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Interleave RAM" Location [2, 74, 2469, 1576] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Bit A" SID "1353" Position [1045, 568, 1075, 582] IconDisplay "Port number" } Block { BlockType Inport Name "Bit B" SID "1354" Position [1045, 718, 1075, 732] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Bit Addr A" SID "1355" Position [270, 653, 300, 667] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Wr A" SID "1356" Position [270, 458, 300, 472] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Bit Addr B" SID "1357" Position [270, 693, 300, 707] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Wr B" SID "1358" Position [270, 488, 300, 502] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Rd Addr" SID "1359" Position [270, 613, 300, 627] NamePlacement "alternate" Port "7" IconDisplay "Port number" } Block { BlockType Inport Name "Rd Mem Sel" SID "3473" Position [1430, 498, 1460, 512] NamePlacement "alternate" Port "8" IconDisplay "Port number" } Block { BlockType Inport Name "Wr Mem Sel" SID "3474" Position [270, 538, 300, 552] Port "9" IconDisplay "Port number" } Block { BlockType Reference Name "Assert" SID "2307" Ports [1, 1] Position [1065, 514, 1110, 536] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware this b" "lock costs nothing." assert_type on type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "9" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "45,22,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Assert1" SID "3510" Ports [1, 1] Position [1070, 834, 1115, 856] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Assert" SourceType "Xilinx Assert Block" infoedit "Asserts a user-defined sample rate and/or type on a signal.

Hardware notes: In hardware this b" "lock costs nothing." assert_type on type_source "Explicitly" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "9" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" assert_rate on rate_source "Explicitly" period "1" output_port on has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "assert" sg_icon_stat "45,22,1,1,white,blue,0,9657e937,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('Assert');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "2358" Ports [2, 1] Position [840, 498, 900, 547] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,49,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 49 49 0 ]);\npatch([14.425 24.54 31.54 38.54 45.54 31.54 21.425 14.425 ],[31.77 31" ".77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([21.425 31.54 24.54 14.425 21.425 ],[24.77 24.77 31.77" " 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([14.425 24.54 31.54 21.425 14.425 ],[17.77 17.77 24.77 24.77 17.77 ]," "[1 1 1 ]);\npatch([21.425 45.54 38.54 31.54 24.54 14.425 21.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "2359" Ports [0, 1] Position [780, 524, 805, 546] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 14.33 " "17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33 14.33 1" "1.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "3492" Position [585, 455, 660, 475] ZOrder -9 ShowName off GotoTag "WrA" } Block { BlockType From Name "From1" SID "3580" Position [1455, 815, 1530, 835] ZOrder -9 ShowName off GotoTag "WrMemSel" } Block { BlockType From Name "From10" SID "3511" Position [585, 985, 660, 1005] ZOrder -9 ShowName off GotoTag "WrAddrB" } Block { BlockType From Name "From11" SID "3512" Position [585, 775, 660, 795] ZOrder -9 ShowName off GotoTag "WrA" } Block { BlockType From Name "From12" SID "3513" Position [585, 945, 660, 965] ZOrder -9 ShowName off GotoTag "WrB" } Block { BlockType From Name "From13" SID "3514" Position [585, 665, 660, 685] ZOrder -9 ShowName off GotoTag "WrAddrB" } Block { BlockType From Name "From2" SID "3496" Position [585, 475, 660, 495] ZOrder -9 ShowName off GotoTag "WrMemSel" } Block { BlockType From Name "From5" SID "3502" Position [585, 500, 660, 520] ZOrder -9 ShowName off GotoTag "RdAddr" } Block { BlockType From Name "From6" SID "3503" Position [585, 540, 660, 560] ZOrder -9 ShowName off GotoTag "WrAddrA" } Block { BlockType From Name "From8" SID "3507" Position [585, 625, 660, 645] ZOrder -9 ShowName off GotoTag "WrB" } Block { BlockType From Name "From9" SID "3509" Position [585, 795, 660, 815] ZOrder -9 ShowName off GotoTag "WrMemSel" } Block { BlockType Reference Name "Gateway Out1" SID "2698" Ports [1, 1] Position [1555, 304, 1590, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "WrEn A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "3574" Ports [1, 1] Position [1600, 719, 1635, 731] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "WrEn B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out11" SID "3575" Ports [1, 1] Position [1600, 769, 1635, 781] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Addr B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "3576" Ports [1, 1] Position [1600, 794, 1635, 806] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd Mem Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out13" SID "3577" Ports [1, 1] Position [1600, 844, 1635, 856] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "RAM 1 D In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out14" SID "3581" Ports [1, 1] Position [1600, 819, 1635, 831] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Wr Mem Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out15" SID "3582" Ports [1, 1] Position [1600, 869, 1635, 881] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "RAM 1 D Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "2701" Ports [1, 1] Position [1555, 354, 1590, 366] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Addr A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "2699" Ports [1, 1] Position [1555, 329, 1590, 341] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "WrEn B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "2702" Ports [1, 1] Position [1555, 379, 1590, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Addr B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "3482" Ports [1, 1] Position [1555, 404, 1590, 416] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd Mem Sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "3564" Ports [1, 1] Position [1555, 429, 1590, 441] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "RAM 0 Dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "3565" Ports [1, 1] Position [1555, 454, 1590, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "RAM 1 Dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "3572" Ports [1, 1] Position [1600, 694, 1635, 706] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "WrEn A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "3573" Ports [1, 1] Position [1600, 744, 1635, 756] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Addr A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "3491" Position [385, 455, 465, 475] ZOrder -10 ShowName off GotoTag "WrA" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "3493" Position [385, 485, 465, 505] ZOrder -10 ShowName off GotoTag "WrB" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "3494" Position [385, 535, 465, 555] ZOrder -10 ShowName off GotoTag "WrMemSel" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "3497" Position [385, 650, 465, 670] ZOrder -10 ShowName off GotoTag "WrAddrA" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "3498" Position [385, 690, 465, 710] ZOrder -10 ShowName off GotoTag "WrAddrB" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "3501" Position [385, 610, 465, 630] ZOrder -10 ShowName off GotoTag "RdAddr" TagVisibility "local" } Block { BlockType Scope Name "Interleaver Mem" SID "2700" Ports [8] Position [1690, 293, 1725, 502] ZOrder -3 Floating off Location [6, 45, 1926, 1199] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "25000" YMin "0~0~0~0~0~-1~-1~-1" YMax "1~1~500~500~1~1~1~1" SaveName "ScopeData9" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Interleaver RAM 0" SID "1360" Ports [6, 2] Position [1215, 453, 1340, 747] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Black Box" SourceType "Xilinx Black Box Block" infoedit " Incorporates black box HDL and simulation model into a System Generator design.

You must supp" "ly a Black Box with certain information about the HDL component you would like to bring into System Generator. Thi" "s information is provided through a Matlab function.

When \"Simulation mode\" is set to \"Inactive\", you w" "ill typically want to provide a separate simulation model by using a Simulation Multiplexer.
When \"Simulation " "mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design." init_code "interleaver_ram" sim_method "ISE Simulator" verbose off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "blackbox2" sg_icon_stat "125,294,6,2,white,blue,0,77702adb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 125 125 0 0 ],[0 0 294 294 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 125 125 0 0 ],[0 0 294 294 0 ]);\npatch([24.175 48.74 65.74 82.74 99.74 65.74 41.175 24.175 ],[" "165.87 165.87 182.87 165.87 182.87 182.87 182.87 165.87 ],[1 1 1 ]);\npatch([41.175 65.74 48.74 24.175 41.175 ],[1" "48.87 148.87 165.87 165.87 148.87 ],[0.931 0.946 0.973 ]);\npatch([24.175 48.74 65.74 41.175 24.175 ],[131.87 131." "87 148.87 148.87 131.87 ],[1 1 1 ]);\npatch([41.175 99.74 82.74 65.74 48.74 24.175 41.175 ],[114.87 114.87 131.87 " "114.87 131.87 131.87 114.87 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMME" "NT: begin icon text');\ncolor('black');port_label('input',1,'wea');\ncolor('black');port_label('input',2,'addra');" "\ncolor('black');port_label('input',3,'dina');\ncolor('black');port_label('input',4,'web');\ncolor('black');port_l" "abel('input',5,'addrb');\ncolor('black');port_label('input',6,'dinb');\ncolor('black');port_label('output',1,'dout" "a');\ncolor('black');port_label('output',2,'doutb');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Interleaver RAM 1" SID "3470" Ports [6, 2] Position [1215, 773, 1340, 1067] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Black Box" SourceType "Xilinx Black Box Block" infoedit " Incorporates black box HDL and simulation model into a System Generator design.

You must supp" "ly a Black Box with certain information about the HDL component you would like to bring into System Generator. Thi" "s information is provided through a Matlab function.

When \"Simulation mode\" is set to \"Inactive\", you w" "ill typically want to provide a separate simulation model by using a Simulation Multiplexer.
When \"Simulation " "mode\" is set to \"External co-simulator\", you must include a ModelSim block in the design." init_code "interleaver_ram" sim_method "ISE Simulator" verbose off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "blackbox2" sg_icon_stat "125,294,6,2,white,blue,0,77702adb,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 125 125 0 0 ],[0 0 294 294 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 125 125 0 0 ],[0 0 294 294 0 ]);\npatch([24.175 48.74 65.74 82.74 99.74 65.74 41.175 24.175 ],[" "165.87 165.87 182.87 165.87 182.87 182.87 182.87 165.87 ],[1 1 1 ]);\npatch([41.175 65.74 48.74 24.175 41.175 ],[1" "48.87 148.87 165.87 165.87 148.87 ],[0.931 0.946 0.973 ]);\npatch([24.175 48.74 65.74 41.175 24.175 ],[131.87 131." "87 148.87 148.87 131.87 ],[1 1 1 ]);\npatch([41.175 99.74 82.74 65.74 48.74 24.175 41.175 ],[114.87 114.87 131.87 " "114.87 131.87 131.87 114.87 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMME" "NT: begin icon text');\ncolor('black');port_label('input',1,'wea');\ncolor('black');port_label('input',2,'addra');" "\ncolor('black');port_label('input',3,'dina');\ncolor('black');port_label('input',4,'web');\ncolor('black');port_l" "abel('input',5,'addrb');\ncolor('black');port_label('input',6,'dinb');\ncolor('black');port_label('output',1,'dout" "a');\ncolor('black');port_label('output',2,'doutb');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Intlv RAM 1" SID "3579" Ports [8] Position [1735, 683, 1770, 892] ZOrder -3 Floating off Location [-1919, 45, 1, 1199] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "25000" YMin "0~0~0~0~0~-1~-0.1~-1" YMax "1~1~500~500~1~1~1.1~1" SaveName "ScopeData16" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Inverter1" SID "3505" Ports [1, 1] Position [720, 476, 750, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3516" Ports [2, 1] Position [850, 607, 885, 643] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "3517" Ports [2, 1] Position [850, 927, 885, 963] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "3479" Ports [2, 1] Position [850, 457, 885, 493] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "3508" Ports [2, 1] Position [850, 777, 885, 813] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,36,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "3472" Ports [3, 1] Position [1530, 491, 1550, 569] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,78,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[41.22 41.22 43.22 41.22 43.22 43.22 43.22 41.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[39.22 39." "22 41.22 41.22 39.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[37.22 37.22 39.22 39.22 37.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[35.22 35.22 37.22 35.22 37.22 37.22 35.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "1361" Ports [3, 1] Position [985, 486, 1005, 564] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,78,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[41.22 41.22 43.22 41.22 43.22 43.22 43.22 41.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[39.22 39." "22 41.22 41.22 39.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[37.22 37.22 39.22 39.22 37.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[35.22 35.22 37.22 35.22 37.22 37.22 35.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "3506" Ports [3, 1] Position [985, 806, 1005, 884] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,78,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ],[0." "77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 11.1429 66.8571 78 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5" ".55 ],[41.22 41.22 43.22 41.22 43.22 43.22 43.22 41.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[39.22 39." "22 41.22 41.22 39.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[37.22 37.22 39.22 39.22 37.22 ]" ",[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[35.22 35.22 37.22 35.22 37.22 37.22 35.22 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1'" ");\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator" SID "1362" Position [1390, 665, 1410, 685] ZOrder -5 ShowName off } Block { BlockType Terminator Name "Terminator1" SID "3471" Position [1390, 985, 1410, 1005] ZOrder -5 ShowName off } Block { BlockType Outport Name "Sc Bits" SID "1363" Position [1620, 523, 1650, 537] IconDisplay "Port number" } Line { SrcBlock "Logical3" SrcPort 1 Points [70, 0] Branch { Points [0, 25] DstBlock "Mux2" DstPort 1 } Branch { Points [190, 0] Branch { DstBlock "Interleaver RAM 0" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out1" DstPort 1 } } } Line { SrcBlock "Interleaver RAM 0" SrcPort 1 Points [50, 0] Branch { DstBlock "Mux1" DstPort 2 } Branch { Points [0, -95] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Interleaver RAM 0" SrcPort 2 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 Points [275, 0] Branch { DstBlock "Mux2" DstPort 3 } Branch { Points [0, 320] DstBlock "Mux3" DstPort 3 } } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Assert" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Concat" SrcPort 1 Points [40, 0] Branch { DstBlock "Mux2" DstPort 2 } Branch { Points [0, 320] DstBlock "Mux3" DstPort 2 } } Line { Name "WrEn A" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Interleaver Mem" DstPort 1 } Line { Name "WrEn B" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Interleaver Mem" DstPort 2 } Line { Name "Addr A" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Interleaver Mem" DstPort 3 } Line { Name "Addr B" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Interleaver Mem" DstPort 4 } Line { SrcBlock "Interleaver RAM 1" SrcPort 2 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Sc Bits" DstPort 1 } Line { SrcBlock "Interleaver RAM 1" SrcPort 1 Points [60, 0] Branch { Points [45, 0; 0, -295] DstBlock "Mux1" DstPort 3 } Branch { Points [0, -35] Branch { Points [0, -355] DstBlock "Gateway Out7" DstPort 1 } Branch { Points [180, 0] DstBlock "Gateway Out15" DstPort 1 } } } Line { SrcBlock "Rd Mem Sel" SrcPort 1 Points [30, 0] Branch { DstBlock "Mux1" DstPort 1 } Branch { Points [0, -95] DstBlock "Gateway Out5" DstPort 1 } Branch { Points [0, 295] DstBlock "Gateway Out12" DstPort 1 } } Line { Name "Rd Mem Sel" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Interleaver Mem" DstPort 5 } Line { SrcBlock "Wr A" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Wr B" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Wr Mem Sel" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Bit Addr B" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Rd Addr" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Bit Addr A" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical3" DstPort 2 } Branch { Points [0, 130] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Logical4" SrcPort 1 Points [70, 0] Branch { Points [0, 25] DstBlock "Mux3" DstPort 1 } Branch { Points [220, 0] Branch { DstBlock "Interleaver RAM 1" DstPort 1 } Branch { Points [0, -95] DstBlock "Gateway Out8" DstPort 1 } } } Line { SrcBlock "From11" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 Points [100, 0] Branch { DstBlock "Logical4" DstPort 2 } Branch { Points [0, 130] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Assert1" DstPort 1 } Line { SrcBlock "Assert" SrcPort 1 Points [40, 0] Branch { DstBlock "Interleaver RAM 0" DstPort 2 } Branch { Points [0, -165] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Assert1" SrcPort 1 Points [70, 0] Branch { DstBlock "Interleaver RAM 1" DstPort 2 } Branch { Points [0, -95] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "From10" SrcPort 1 Points [530, 0] Branch { DstBlock "Interleaver RAM 1" DstPort 5 } Branch { Points [0, -220] DstBlock "Gateway Out11" DstPort 1 } } Line { SrcBlock "Bit A" SrcPort 1 Points [80, 0] Branch { DstBlock "Interleaver RAM 0" DstPort 3 } Branch { Points [0, 320; 10, 0] Branch { DstBlock "Interleaver RAM 1" DstPort 3 } Branch { Points [0, -45] DstBlock "Gateway Out13" DstPort 1 } } } Line { SrcBlock "Bit B" SrcPort 1 Points [75, 0] Branch { DstBlock "Interleaver RAM 0" DstPort 6 } Branch { Points [0, 320] DstBlock "Interleaver RAM 1" DstPort 6 } } Line { SrcBlock "Logical1" SrcPort 1 Points [285, 0] Branch { DstBlock "Interleaver RAM 0" DstPort 4 } Branch { Points [0, -290] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 Points [295, 0] Branch { DstBlock "Interleaver RAM 1" DstPort 4 } Branch { Points [0, -220] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "From13" SrcPort 1 Points [515, 0] Branch { DstBlock "Interleaver RAM 0" DstPort 5 } Branch { Points [0, -290] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "From8" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { Name "RAM 0 Dout" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Interleaver Mem" DstPort 6 } Line { Name "RAM 1 Dout" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Interleaver Mem" DstPort 7 } Line { Name "WrEn A" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Intlv RAM 1" DstPort 1 } Line { Name "WrEn B" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "Intlv RAM 1" DstPort 2 } Line { Name "Addr A" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Intlv RAM 1" DstPort 3 } Line { Name "Addr B" Labels [0, 0] SrcBlock "Gateway Out11" SrcPort 1 DstBlock "Intlv RAM 1" DstPort 4 } Line { Name "Rd Mem Sel" Labels [0, 0] SrcBlock "Gateway Out12" SrcPort 1 DstBlock "Intlv RAM 1" DstPort 5 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Gateway Out14" DstPort 1 } Line { Name "Wr Mem Sel" Labels [0, 0] SrcBlock "Gateway Out14" SrcPort 1 DstBlock "Intlv RAM 1" DstPort 6 } Line { Name "RAM 1 D In" Labels [0, 0] SrcBlock "Gateway Out13" SrcPort 1 DstBlock "Intlv RAM 1" DstPort 7 } Line { Name "RAM 1 D Out" Labels [0, 0] SrcBlock "Gateway Out15" SrcPort 1 DstBlock "Intlv RAM 1" DstPort 8 } Annotation { Name "Block box wraps single DP RAM block, configured for 512b total storage with write port widths of 1 bit,\n" "read port widths of 8 bits.\n\nWrite address is 9-bit address for a single bit. \n\nRead address is a 9-bit addres" "s, 3LSB ignored, 6MSB read 8-bit value where LSB is lowest-indexed written bit." Position [1150, 1206] HorizontalAlignment "left" } Annotation { Name "Two RAMs used for ping/pong scheme, switching roles with each OFDM symbol. At MCS 7 and 40MSps\nthe inte" "rleaver read for sym N overlaps the write for sym (N-1) by a few cycles. The ping/pong RAMs allows\nsym N to be wr" "itten to a different memory than sym N-1" Position [1148, 1123] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Interleaver Ctrl &\nPuncturing" SID "1364" Ports [2, 4] Position [770, 244, 890, 326] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Interleaver Ctrl &\nPuncturing" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "80" Block { BlockType Inport Name "Bits tvalid" SID "1365" Position [405, 708, 435, 722] IconDisplay "Port number" } Block { BlockType Inport Name "Base Rate" SID "1366" Position [505, 378, 535, 392] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType SubSystem Name "Bit Index Calc" SID "1367" Ports [3, 2] Position [1175, 492, 1275, 588] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off Port { PortNumber 1 Name "Ind A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "Ind B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "Bit Index Calc" Location [214, 74, 2416, 1416] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Inc" SID "1368" Position [715, 383, 745, 397] IconDisplay "Port number" } Block { BlockType Inport Name "Rst" SID "1369" Position [750, 398, 780, 412] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "1370" Position [790, 413, 820, 427] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Accumulator" SID "1371" Ports [3, 1] Position [890, 382, 950, 428] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to ru" "n at the system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "ceil(log2(MAX_NCBPS))" overflow "Wrap" scale "1" rst on infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "accum" sg_icon_stat "60,46,3,1,white,blue,0,ee9eb47a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 46 46 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 46 46 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[29.66" " 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.66 29." "66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 17.66 ]" ",[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'b');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('inpu" "t',3,'en');\ncolor('black');port_label('output',1,'\\bf+=b','texmode','on');\nfprintf('','COMMENT: end icon text" "');" } Block { BlockType Reference Name "AddSub" SID "1372" Ports [2, 1] Position [1010, 507, 1040, 538] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(MAX_NCBPS))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,31,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.4" "4 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 " "15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('in" "put',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','tex" "mode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "1373" Ports [0, 1] Position [940, 522, 960, 538] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 16 16 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[10.22 10." "22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([" "7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'" "1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind A" SID "1374" Position [1280, 398, 1310, 412] IconDisplay "Port number" } Block { BlockType Outport Name "Ind B" SID "1375" Position [1280, 518, 1310, 532] Port "2" IconDisplay "Port number" } Line { SrcBlock "Accumulator" SrcPort 1 Points [15, 0] Branch { Points [0, 110] DstBlock "AddSub" DstPort 1 } Branch { DstBlock "Ind A" DstPort 1 } } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "Ind B" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "AddSub" DstPort 2 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Accumulator" DstPort 2 } Line { SrcBlock "En" SrcPort 1 DstBlock "Accumulator" DstPort 3 } Line { SrcBlock "Inc" SrcPort 1 DstBlock "Accumulator" DstPort 1 } Annotation { Name "Accumulator increments by 1 or 2 bits per cycle, depending\non whether current bit pair has a punctur" "ed value.\nOutputs are used as memory addresses for the interleaver RAM." Position [736, 603] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Constant2" SID "1376" Ports [0, 1] Position [620, 484, 650, 506] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "1377" Ports [1, 1] Position [1405, 738, 1435, 772] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "1378" Ports [1, 1] Position [1405, 778, 1435, 812] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From13" SID "1379" Position [420, 451, 620, 469] ZOrder -9 ShowName off GotoTag "OFDM_TX_DATA_Code_Rate" TagVisibility "global" } Block { BlockType From Name "From14" SID "1380" Position [440, 637, 525, 653] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "1381" Ports [1, 1] Position [1675, 154, 1710, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rate" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "1382" Ports [1, 1] Position [1675, 304, 1710, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Addr A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "1383" Ports [1, 1] Position [1675, 179, 1710, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Base Rate" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "1384" Ports [1, 1] Position [1675, 229, 1710, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "1385" Ports [1, 1] Position [1675, 254, 1710, 266] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Ind A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "1386" Ports [1, 1] Position [1675, 279, 1710, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Ind B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "1387" Ports [1, 1] Position [1675, 329, 1710, 341] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Addr B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "1388" Ports [1, 1] Position [1675, 204, 1710, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Interleave Mapping" SID "1389" Ports [3, 2] Position [1365, 439, 1480, 591] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Interleave Mapping" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "Base Rate Sym" SID "1390" Position [320, 243, 350, 257] IconDisplay "Port number" } Block { BlockType Inport Name "Ind A" SID "1391" Position [320, 328, 350, 342] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Ind B" SID "1392" Position [325, 568, 355, 582] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Concat1" SID "2322" Ports [2, 1] Position [510, 253, 530, 282] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "20,29,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 29 29 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[16.22 16." "22 18.22 16.22 18.22 18.22 18.22 16.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[14.22 14.22 16.22 16.22" " 14.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[12.22 12.22 14.22 14.22 12.22 ],[1 1 1 ]);\n" "patch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 10.22 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_labe" "l('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmo" "de','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "1393" Ports [3, 1] Position [645, 211, 680, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,148,3,1,white,blue,0,61ef8218,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 148 148 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 148 148 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[79.55" " 79.55 84.55 79.55 84.55 84.55 84.55 79.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[74.55 74.55 79." "55 79.55 74.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[69.55 69.55 74.55 74.55 69.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[64.55 64.55 69.55 64.55 69.55 69.55 64.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'hi');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsiz" "e{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat3" SID "1394" Ports [3, 1] Position [645, 451, 680, 599] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "3" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,148,3,1,white,blue,0,61ef8218,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 148 148 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 148 148 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[79.55" " 79.55 84.55 79.55 84.55 84.55 84.55 79.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[74.55 74.55 79." "55 79.55 74.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[69.55 69.55 74.55 74.55 69.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[64.55 64.55 69.55 64.55 69.55 69.55 64.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'hi');\n\ncolor('black');port_label('input',3,'lo');\n\ncolor('black');disp('\\fontsiz" "e{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant8" SID "1395" Ports [0, 1] Position [755, 302, 775, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(MAX_NCBPS))" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 16 16 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[10.22 10." "22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([" "7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'" "0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant9" SID "1396" Ports [0, 1] Position [755, 327, 775, 343] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,16,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 16 16 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 16 16 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[10.22 10." "22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([" "7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'" "0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From14" SID "1397" Position [155, 292, 330, 308] ZOrder -9 ShowName off GotoTag "OFDM_TX_DATA_Mod_Sel" TagVisibility "global" } Block { BlockType From Name "From2" SID "1398" Position [310, 211, 470, 229] ZOrder -9 ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "1399" Ports [1, 1] Position [415, 239, 440, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "1400" Ports [2, 1] Position [555, 205, 585, 265] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 60 60 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[34.44 34.4" "4 38.44 34.44 38.44 38.44 38.44 34.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[30.44 30.44 34.44 34.44 " "30.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[26.44 26.44 30.44 30.44 26.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[22.44 22.44 26.44 22.44 26.44 26.44 22.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2323" Ports [2, 1] Position [555, 255, 585, 315] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 60 60 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 60 60 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[34.44 34.4" "4 38.44 34.44 38.44 38.44 38.44 34.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[30.44 30.44 34.44 34.44 " "30.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[26.44 26.44 30.44 30.44 26.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[22.44 22.44 26.44 22.44 26.44 26.44 22.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Map ROM" SID "1401" Ports [6, 2] Position [835, 265, 910, 430] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "length(wlan_tx_interleave_rom)" initVector "wlan_tx_interleave_rom" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b off en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" sg_icon_stat "75,165,6,2,white,blue,0,28af736d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 75 75 0 0 ],[0 0 165 165 0 ],[0.77 0." "82 0.91 ]);\nplot([0 75 75 0 0 ],[0 0 165 165 0 ]);\npatch([14.75 29.2 39.2 49.2 59.2 39.2 24.75 14.75 ],[93.1 9" "3.1 103.1 93.1 103.1 103.1 103.1 93.1 ],[1 1 1 ]);\npatch([24.75 39.2 29.2 14.75 24.75 ],[83.1 83.1 93.1 93.1 83" ".1 ],[0.931 0.946 0.973 ]);\npatch([14.75 29.2 39.2 24.75 14.75 ],[73.1 73.1 83.1 83.1 73.1 ],[1 1 1 ]);\npatch(" "[24.75 59.2 49.2 39.2 29.2 14.75 24.75 ],[63.1 63.1 73.1 63.1 73.1 73.1 63.1 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "addra');\ncolor('black');port_label('input',2,'dina');\ncolor('black');port_label('input',3,'wea');\ncolor('blac" "k');port_label('input',4,'addrb');\ncolor('black');port_label('input',5,'dinb');\ncolor('black');port_label('inp" "ut',6,'web');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_label('output',2,'B');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Outport Name "Addr A" SID "1402" Position [990, 303, 1020, 317] IconDisplay "Port number" } Block { BlockType Outport Name "Addr B" SID "1403" Position [990, 383, 1020, 397] Port "2" IconDisplay "Port number" } Line { SrcBlock "Base Rate Sym" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [45, 0] Branch { DstBlock "Logical" DstPort 2 } Branch { Points [0, 10] Branch { DstBlock "Concat1" DstPort 1 } Branch { Points [0, 15] DstBlock "Concat1" DstPort 2 } } } Line { SrcBlock "Logical" SrcPort 1 Points [30, 0] Branch { DstBlock "Concat2" DstPort 1 } Branch { Points [0, 240] DstBlock "Concat3" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 Points [20, 0] Branch { DstBlock "Concat2" DstPort 2 } Branch { Points [0, 240] DstBlock "Concat3" DstPort 2 } } Line { SrcBlock "Ind A" SrcPort 1 DstBlock "Concat2" DstPort 3 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 DstBlock "Map ROM" DstPort 1 } Line { SrcBlock "Ind B" SrcPort 1 DstBlock "Concat3" DstPort 3 } Line { SrcBlock "Concat3" SrcPort 1 Points [65, 0; 0, -165] DstBlock "Map ROM" DstPort 4 } Line { SrcBlock "Constant8" SrcPort 1 Points [30, 0] Branch { DstBlock "Map ROM" DstPort 2 } Branch { Points [0, 75] DstBlock "Map ROM" DstPort 5 } } Line { SrcBlock "Constant9" SrcPort 1 Points [25, 0] Branch { DstBlock "Map ROM" DstPort 3 } Branch { Points [0, 75] DstBlock "Map ROM" DstPort 6 } } Line { SrcBlock "Map ROM" SrcPort 1 DstBlock "Addr A" DstPort 1 } Line { SrcBlock "Map ROM" SrcPort 2 DstBlock "Addr B" DstPort 1 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Logical1" DstPort 1 } } } Block { BlockType Scope Name "Interleaver Control" SID "1404" Ports [8] Position [1810, 143, 1845, 352] ZOrder -3 Floating off Location [-1919, 45, 1, 1199] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "5000" YMin "0~0~0~0~0~0~0~0" YMax "1~1~1~1~400~400~500~500" SaveName "ScopeData38" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Logical2" SID "1405" Ports [2, 1] Position [630, 629, 660, 696] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,67,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 67 67 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 67 67 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[37.44 37.44 41.4" "4 37.44 41.44 41.44 41.44 37.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[33.44 33.44 37.44 37.44 33.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[29.44 29.44 33.44 33.44 29.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[25.44 25.44 29.44 25.44 29.44 29.44 25.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "1406" Ports [3, 1] Position [720, 407, 740, 513] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,106,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 15.1429 90.8571 106 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 15.1429 90.8571 106 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55" " 5.55 ],[55.22 55.22 57.22 55.22 57.22 57.22 57.22 55.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[53.22 5" "3.22 55.22 55.22 53.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[51.22 51.22 53.22 53.22 51.22" " ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[49.22 49.22 51.22 49.22 51.22 51.22 49.22 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d" "1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Puncturing" SID "1407" Ports [3, 3] Position [905, 484, 1000, 626] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Puncturing" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Code Rate" SID "1408" Position [205, 158, 235, 172] IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "1409" Position [205, 208, 235, 222] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "1410" Position [205, 243, 235, 257] Port "3" IconDisplay "Port number" } Block { BlockType From Name "From1" SID "1411" Position [610, 181, 710, 199] ZOrder -9 ShowName off GotoTag "R12_INC_A" } Block { BlockType From Name "From10" SID "1412" Position [610, 571, 710, 589] ZOrder -9 ShowName off GotoTag "R56_SKIP_B" } Block { BlockType From Name "From11" SID "1413" Position [610, 386, 710, 404] ZOrder -9 ShowName off GotoTag "R34_SKIP_A" } Block { BlockType From Name "From12" SID "1414" Position [610, 546, 710, 564] ZOrder -9 ShowName off GotoTag "R34_SKIP_B" } Block { BlockType From Name "From2" SID "1415" Position [610, 256, 710, 274] ZOrder -9 ShowName off GotoTag "R56_INC_A" } Block { BlockType From Name "From3" SID "1416" Position [610, 336, 710, 354] ZOrder -9 ShowName off GotoTag "R12_SKIP_A" } Block { BlockType From Name "From4" SID "1417" Position [610, 496, 710, 514] ZOrder -9 ShowName off GotoTag "R12_SKIP_B" } Block { BlockType From Name "From5" SID "1418" Position [610, 206, 710, 224] ZOrder -9 ShowName off GotoTag "R23_INC_A" } Block { BlockType From Name "From6" SID "1419" Position [610, 411, 710, 429] ZOrder -9 ShowName off GotoTag "R56_SKIP_A" } Block { BlockType From Name "From7" SID "1420" Position [610, 361, 710, 379] ZOrder -9 ShowName off GotoTag "R23_SKIP_A" } Block { BlockType From Name "From8" SID "1421" Position [610, 521, 710, 539] ZOrder -9 ShowName off GotoTag "R23_SKIP_B" } Block { BlockType From Name "From9" SID "1422" Position [610, 231, 710, 249] ZOrder -9 ShowName off GotoTag "R34_INC_A" } Block { BlockType Goto Name "Goto" SID "1423" Position [415, 291, 515, 309] ZOrder -10 ShowName off GotoTag "R23_INC_A" TagVisibility "local" } Block { BlockType Goto Name "Goto1" SID "1424" Position [415, 481, 515, 499] ZOrder -10 ShowName off GotoTag "R56_INC_A" TagVisibility "local" } Block { BlockType Goto Name "Goto10" SID "1425" Position [415, 221, 515, 239] ZOrder -10 ShowName off GotoTag "R12_SKIP_A" TagVisibility "local" } Block { BlockType Goto Name "Goto11" SID "1426" Position [415, 241, 515, 259] ZOrder -10 ShowName off GotoTag "R12_SKIP_B" TagVisibility "local" } Block { BlockType Goto Name "Goto2" SID "1427" Position [415, 311, 515, 329] ZOrder -10 ShowName off GotoTag "R23_SKIP_A" TagVisibility "local" } Block { BlockType Goto Name "Goto3" SID "1428" Position [415, 331, 515, 349] ZOrder -10 ShowName off GotoTag "R23_SKIP_B" TagVisibility "local" } Block { BlockType Goto Name "Goto4" SID "1429" Position [415, 381, 515, 399] ZOrder -10 ShowName off GotoTag "R34_INC_A" TagVisibility "local" } Block { BlockType Goto Name "Goto5" SID "1430" Position [415, 506, 515, 524] ZOrder -10 ShowName off GotoTag "R56_SKIP_A" TagVisibility "local" } Block { BlockType Goto Name "Goto6" SID "1431" Position [415, 406, 515, 424] ZOrder -10 ShowName off GotoTag "R34_SKIP_A" TagVisibility "local" } Block { BlockType Goto Name "Goto7" SID "1432" Position [415, 431, 515, 449] ZOrder -10 ShowName off GotoTag "R34_SKIP_B" TagVisibility "local" } Block { BlockType Goto Name "Goto8" SID "1433" Position [415, 201, 515, 219] ZOrder -10 ShowName off GotoTag "R12_INC_A" TagVisibility "local" } Block { BlockType Goto Name "Goto9" SID "1434" Position [415, 531, 515, 549] ZOrder -10 ShowName off GotoTag "R56_SKIP_B" TagVisibility "local" } Block { BlockType Reference Name "Inverter" SID "1435" Ports [1, 1] Position [840, 359, 865, 381] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "1436" Ports [1, 1] Position [840, 519, 865, 541] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,22,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 22 22 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[14.33 " "14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 " "1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "1437" Ports [2, 1] Position [945, 361, 980, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1438" Ports [2, 1] Position [945, 521, 980, 559] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black" "');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "1439" Ports [5, 1] Position [765, 464, 785, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,132,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 18.8571 113.143 132 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 18.8571 113.143 132 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[68.22 68.22 70.22 68.22 70.22 70.22 70.22 68.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[66.22 66.22 68.22 68.22 66.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[64.22 64.22 66.22 6" "6.22 64.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[62.22 62.22 64.22 62.22 64.22 64.22 62." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "1440" Ports [5, 1] Position [765, 304, 785, 436] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,132,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 18.8571 113.143 132 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 18.8571 113.143 132 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[68.22 68.22 70.22 68.22 70.22 70.22 70.22 68.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[66.22 66.22 68.22 68.22 66.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[64.22 64.22 66.22 6" "6.22 64.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[62.22 62.22 64.22 62.22 64.22 64.22 62." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux4" SID "1441" Ports [5, 1] Position [765, 149, 785, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "4" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,132,5,1,white,blue,3,d6c79293,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 18.8571 113.143 132 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 18.8571 113.143 132 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[68.22 68.22 70.22 68.22 70.22 70.22 70.22 68.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[66.22 66.22 68.22 68.22 66.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[64.22 64.22 66.22 6" "6.22 64.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[62.22 62.22 64.22 62.22 64.22 64.22 62." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\ncolor('black');port_label('input',5,'d3');\n\nc" "olor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Rate 1/2" SID "1442" Ports [2, 3] Position [285, 196, 360, 264] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rate 1/2" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "1443" Position [210, 263, 240, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "1444" Position [210, 288, 240, 302] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant2" SID "1445" Ports [0, 1] Position [375, 219, 405, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "1446" Ports [0, 1] Position [375, 334, 405, 356] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind Inc" SID "1447" Position [525, 338, 555, 352] IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "1448" Position [525, 223, 555, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "1449" Position [525, 268, 555, 282] Port "3" IconDisplay "Port number" } Line { SrcBlock "Constant2" SrcPort 1 Points [70, 0] Branch { DstBlock "Skip A" DstPort 1 } Branch { Points [0, 45] DstBlock "Skip B" DstPort 1 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Ind Inc" DstPort 1 } } } Block { BlockType SubSystem Name "Rate 2/3" SID "1450" Ports [2, 3] Position [285, 286, 360, 354] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rate 2/3" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "1451" Position [210, 263, 240, 277] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "1452" Position [210, 288, 240, 302] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1453" Ports [0, 1] Position [375, 294, 405, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "1454" Ports [0, 1] Position [375, 219, 405, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "1455" Ports [0, 1] Position [445, 424, 475, 446] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "1456" Ports [0, 1] Position [445, 474, 475, 496] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "1457" Ports [3, 1] Position [530, 357, 550, 513] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,156,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 22.2857 133.714 156 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 22.2857 133.714 156 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[80.22 80.22 82.22 80.22 82.22 82.22 82.22 80.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[78.22 78.22 80.22 80.22 78.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[76.22 76.22 78.22 7" "8.22 76.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[74.22 74.22 76.22 74.22 76.22 76.22 74." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "1458" Ports [2, 1] Position [445, 276, 480, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "[0:1]" SID "1459" Ports [2, 1] Position [275, 259, 330, 306] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "5" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "1" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,47,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 47 47 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[29.66" " 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[23.66 23.66 29." "66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[17.66 17.66 23.66 23.66 17.66 ]" ",[1 1 1 ]);\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\font" "size{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind Inc" SID "1460" Position [630, 428, 660, 442] IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "1461" Position [525, 223, 555, 237] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "1462" Position [525, 288, 555, 302] Port "3" IconDisplay "Port number" } Line { SrcBlock "[0:1]" SrcPort 1 DstBlock "Relational" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [15, 0] Branch { DstBlock "Skip B" DstPort 1 } Branch { Points [0, 90] DstBlock "Mux3" DstPort 1 } } Line { SrcBlock "Rst" SrcPort 1 DstBlock "[0:1]" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "[0:1]" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Skip A" DstPort 1 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Ind Inc" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux3" DstPort 3 } } } Block { BlockType SubSystem Name "Rate 3/4" SID "1463" Ports [2, 3] Position [285, 380, 360, 450] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rate 3/4" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rst" SID "1464" Position [530, 443, 560, 457] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "1465" Position [530, 468, 560, 482] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "1466" Ports [2, 1] Position [905, 588, 930, 632] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,44,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 44 44 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[25.33 " "25.33 28.33 25.33 28.33 28.33 28.33 25.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[22.33 22.33 25.33" " 25.33 22.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[19.33 19.33 22.33 22.33 19.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 16.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "1467" Ports [0, 1] Position [695, 474, 725, 496] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "1468" Ports [0, 1] Position [695, 514, 725, 536] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "1469" Ports [0, 1] Position [900, 644, 930, 666] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "1470" Ports [0, 1] Position [900, 689, 930, 711] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "1471" Ports [0, 1] Position [900, 734, 930, 756] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "1472" Ports [4, 1] Position [985, 589, 1005, 766] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,177,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 25.2857 151.714 177 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 25.2857 151.714 177 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[90.22 90.22 92.22 90.22 92.22 92.22 92.22 90.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[88.22 88.22 90.22 90.22 88.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[86.22 86.22 88.22 8" "8.22 86.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[84.22 84.22 86.22 84.22 86.22 86.22 84." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "1473" Ports [2, 1] Position [765, 456, 800, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "1474" Ports [2, 1] Position [765, 496, 800, 534] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "[0:2]" SID "1475" Ports [2, 1] Position [595, 439, 650, 486] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Count Limited" cnt_to "2" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "2" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,47,2,1,white,blue,0,131a2a7a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 47 47 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[29.66" " 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[23.66 23.66 29." "66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[17.66 17.66 23.66 23.66 17.66 ]" ",[1 1 1 ]);\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\font" "size{14}\\bf\\lceil++\\rceil}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind Inc" SID "1476" Position [1085, 673, 1115, 687] IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "1477" Position [965, 468, 995, 482] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "1478" Position [965, 508, 995, 522] Port "3" IconDisplay "Port number" } Line { SrcBlock "En" SrcPort 1 DstBlock "[0:2]" DstPort 2 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "[0:2]" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 Points [65, 0] Branch { DstBlock "Skip B" DstPort 1 } Branch { Points [0, 85] DstBlock "Concat" DstPort 1 } } Line { SrcBlock "Relational" SrcPort 1 Points [60, 0] Branch { DstBlock "Skip A" DstPort 1 } Branch { Points [0, 145] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "[0:2]" SrcPort 1 Points [85, 0] Branch { Points [0, 40] DstBlock "Relational2" DstPort 1 } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Ind Inc" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Mux3" DstPort 1 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Mux3" DstPort 4 } } } Block { BlockType SubSystem Name "Rate 5/6" SID "1479" Ports [2, 3] Position [285, 480, 360, 550] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rate 5/6" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "Rst" SID "1480" Position [125, 138, 155, 152] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "1481" Position [125, 163, 155, 177] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "1482" Ports [2, 1] Position [515, 338, 540, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point " "at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "25,44,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 44 44 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[25.33 " "25.33 28.33 25.33 28.33 28.33 28.33 25.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[22.33 22.33 25.33" " 25.33 22.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[19.33 19.33 22.33 22.33 19.33 ],[1" " 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[16.33 16.33 19.33 16.33 19.33 19.33 16.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{2" "0}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "1483" Ports [0, 1] Position [285, 249, 315, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "1484" Ports [0, 1] Position [285, 169, 315, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "1485" Ports [0, 1] Position [510, 394, 540, 416] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "1486" Ports [0, 1] Position [510, 439, 540, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "1487" Ports [0, 1] Position [285, 289, 315, 311] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "3" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,279a71c8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'3');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant6" SID "1488" Ports [0, 1] Position [285, 209, 315, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "4" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,85f36853,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'4');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant7" SID "1489" Ports [0, 1] Position [510, 484, 540, 506] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "1490" Ports [2, 1] Position [430, 151, 460, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,78,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 78 78 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 78 78 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[43.44 43.4" "4 47.44 43.44 47.44 47.44 47.44 43.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[39.44 39.44 43.44 43.44 " "39.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[35.44 35.44 39.44 39.44 35.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[31.44 31.44 35.44 31.44 35.44 35.44 31.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1491" Ports [2, 1] Position [430, 231, 460, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,78,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 78 78 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 78 78 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[43.44 43.4" "4 47.44 43.44 47.44 47.44 47.44 43.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[39.44 39.44 43.44 43.44 " "39.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[35.44 35.44 39.44 39.44 35.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[31.44 31.44 35.44 31.44 35.44 35.44 31.44 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp" "('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux3" SID "1492" Ports [4, 1] Position [595, 339, 615, 516] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,177,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 25.2857 151.714 177 0 " "],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 25.2857 151.714 177 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.4" "4 7.55 5.55 ],[90.22 90.22 92.22 90.22 92.22 92.22 92.22 90.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ]," "[88.22 88.22 90.22 90.22 88.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[86.22 86.22 88.22 8" "8.22 86.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[84.22 84.22 86.22 84.22 86.22 86.22 84." "22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_lab" "el('input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "1493" Ports [2, 1] Position [360, 151, 395, 189] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "1494" Ports [2, 1] Position [360, 231, 395, 269] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "1495" Ports [2, 1] Position [360, 191, 395, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "1496" Ports [2, 1] Position [360, 271, 395, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 38 38 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 38 38 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[24.55 24." "55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[19.55 19.55 24.55 2" "4.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1" " 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa " "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "[0:4]" SID "1497" Ports [2, 1] Position [190, 134, 245, 181] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited count" "er is implemented by combining a counter with a comparator." cnt_type "Count Limited" cnt_to "4" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "3" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "55,47,2,1,white,blue,0,131a2a7a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 47 47 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 47 47 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[29.66" " 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[23.66 23.66 29." "66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[17.66 17.66 23.66 23.66 17.66 ]" ",[1 1 1 ]);\npatch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\font" "size{14}\\bf\\lceil++\\rceil}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Ind Inc" SID "1498" Position [695, 423, 725, 437] IconDisplay "Port number" } Block { BlockType Outport Name "Skip A" SID "1499" Position [525, 183, 555, 197] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Skip B" SID "1500" Position [525, 263, 555, 277] Port "3" IconDisplay "Port number" } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Mux3" DstPort 4 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Mux3" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Ind Inc" DstPort 1 } Line { SrcBlock "[0:4]" SrcPort 1 Points [85, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 40] DstBlock "Relational3" DstPort 1 } } } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "[0:4]" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "[0:4]" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [25, 0] Branch { DstBlock "Skip A" DstPort 1 } Branch { Points [0, 180] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [30, 0] Branch { DstBlock "Skip B" DstPort 1 } Branch { Points [0, 80] DstBlock "Concat" DstPort 1 } } } } Block { BlockType Outport Name "Index Inc" SID "1501" Position [1070, 208, 1100, 222] IconDisplay "Port number" } Block { BlockType Outport Name "Wr A" SID "1502" Position [1070, 373, 1100, 387] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Wr B" SID "1503" Position [1070, 533, 1100, 547] Port "3" IconDisplay "Port number" } Line { SrcBlock "Mux3" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Rate 1/2" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Rate 1/2" SrcPort 2 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Rate 1/2" SrcPort 3 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "Rate 2/3" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Rate 2/3" SrcPort 2 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Rate 2/3" SrcPort 3 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Rate 3/4" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Rate 3/4" SrcPort 2 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Rate 3/4" SrcPort 3 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Mux3" DstPort 2 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Mux3" DstPort 3 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Mux3" DstPort 4 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Mux1" DstPort 4 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Mux4" DstPort 2 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Mux4" DstPort 3 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Mux4" DstPort 4 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Mux4" DstPort 5 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Mux3" DstPort 5 } Line { SrcBlock "Rate 5/6" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Rate 5/6" SrcPort 2 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Rate 5/6" SrcPort 3 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Mux1" DstPort 5 } Line { SrcBlock "Code Rate" SrcPort 1 Points [500, 0] Branch { DstBlock "Mux4" DstPort 1 } Branch { Points [0, 155] Branch { DstBlock "Mux3" DstPort 1 } Branch { Points [0, 160] DstBlock "Mux1" DstPort 1 } } } Line { SrcBlock "Mux4" SrcPort 1 DstBlock "Index Inc" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 Points [15, 0] Branch { DstBlock "Rate 1/2" DstPort 1 } Branch { Points [0, 90] Branch { DstBlock "Rate 2/3" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Rate 3/4" DstPort 1 } Branch { Points [0, 100] DstBlock "Rate 5/6" DstPort 1 } } } } Line { SrcBlock "En" SrcPort 1 Points [20, 0] Branch { DstBlock "Rate 1/2" DstPort 2 } Branch { Points [0, 90] Branch { DstBlock "Rate 2/3" DstPort 2 } Branch { Points [0, 95] Branch { DstBlock "Rate 3/4" DstPort 2 } Branch { Points [0, 100] Branch { DstBlock "Rate 5/6" DstPort 2 } Branch { Points [0, 95; 645, 0; 0, -80] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -160] DstBlock "Logical" DstPort 2 } } } } } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Wr A" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Wr B" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "1504" Ports [1, 1] Position [515, 673, 560, 687] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [13, 209, 1798, 1427] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1505" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "1506" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "1507" Ports [1, 1] Position [475, 181, 500, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1508" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1509" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "Addr A" SID "1510" Position [1545, 473, 1575, 487] IconDisplay "Port number" } Block { BlockType Outport Name "Wr A" SID "1511" Position [1545, 748, 1575, 762] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Addr B" SID "1512" Position [1545, 548, 1575, 562] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Wr B" SID "1513" Position [1545, 788, 1575, 802] Port "4" IconDisplay "Port number" } Line { SrcBlock "Puncturing" SrcPort 1 DstBlock "Bit Index Calc" DstPort 1 } Line { Name "Rate" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Interleaver Control" DstPort 1 } Line { Name "En" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Interleaver Control" DstPort 4 } Line { Name "Ind A" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Interleaver Control" DstPort 5 } Line { SrcBlock "Mux2" SrcPort 1 Points [145, 0] Branch { DstBlock "Puncturing" DstPort 1 } Branch { Points [0, -300] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 Points [160, 0] Branch { Points [240, 0; 0, -125; 50, 0] Branch { DstBlock "Bit Index Calc" DstPort 2 } Branch { Points [0, -330] DstBlock "Gateway Out8" DstPort 1 } } Branch { Points [0, -110] DstBlock "Puncturing" DstPort 2 } } Line { SrcBlock "Bits tvalid" SrcPort 1 Points [40, 0] Branch { Points [0, -35] DstBlock "negedge" DstPort 1 } Branch { Points [350, 0] Branch { Points [240, 0; 0, -145; 50, 0] Branch { DstBlock "Bit Index Calc" DstPort 3 } Branch { Points [0, -335] DstBlock "Gateway Out4" DstPort 1 } } Branch { Points [0, -115] DstBlock "Puncturing" DstPort 3 } } } Line { Name "Ind A" Labels [0, 0] SrcBlock "Bit Index Calc" SrcPort 1 Points [30, 0] Branch { Points [0, -255] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Interleave Mapping" DstPort 2 } } Line { Name "Ind B" Labels [0, 0] SrcBlock "Bit Index Calc" SrcPort 2 Points [35, 0] Branch { Points [0, -280] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "Interleave Mapping" DstPort 3 } } Line { Name "Ind B" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Interleaver Control" DstPort 6 } Line { SrcBlock "Puncturing" SrcPort 2 Points [40, 0; 0, 200] DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Puncturing" SrcPort 3 Points [35, 0; 0, 195] DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Base Rate" SrcPort 1 Points [130, 0] Branch { Points [0, 40] DstBlock "Mux2" DstPort 1 } Branch { Points [415, 0] Branch { Points [0, 80] DstBlock "Interleave Mapping" DstPort 1 } Branch { Points [0, -200] DstBlock "Gateway Out3" DstPort 1 } } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { Name "Base Rate" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Interleaver Control" DstPort 2 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Wr A" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Wr B" DstPort 1 } Line { SrcBlock "Interleave Mapping" SrcPort 1 Points [10, 0] Branch { DstBlock "Addr A" DstPort 1 } Branch { Points [0, -170] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Interleave Mapping" SrcPort 2 Points [15, 0] Branch { DstBlock "Addr B" DstPort 1 } Branch { Points [0, -220] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { Name "Addr A" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Interleaver Control" DstPort 7 } Line { Name "Addr B" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Interleaver Control" DstPort 8 } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Interleaver Control" DstPort 3 } Annotation { Name "The code puncturing is implemented as part of the interleaver. The\ninterleaver RAM can record 2 coded b" "its per cycle (the A and B outputs\nof the convolutional encoder). A coded bit is punctured by not being\nwritten " "to the interleaver RAM.\n\nThis interleaver design operates at the effective rate of 1 uncoded data bit\nper cycle" ", allowing the overall architecture to achieve a data rate equal\nto the master clock frequency. This is achieved " "by writing 2 coded bits\nper cycle to the interleave RAM (2 coded bits = 1 data bit). It would be \nsimpler to ser" "ialize the coded bits, but this would cut the max data rate\nin half, which would complicate implementation of HT4" "0 and N_SS=2 modes\nin the future.\n\nThe interleaver RAM outputs coded bits in groups. The number of valid\nbits " "in each group equals the number of coded bits in a subcarrier for\nthe current symbol's MCS. This architecture (wr" "ite 2 bits per cycle, read all\nbits for a subcarrier in 1 cycle) minimizes latency through the interleaver." Position [442, 199] HorizontalAlignment "left" } } } Block { BlockType Reference Name "MCode" SID "2586" Ports [1, 8] Position [385, 300, 635, 415] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input po" "rts of the block are input arguments of the function. The output ports of the block are output arguments of the" " function." mfname "sym_config_decode" explicit_period on period "1" inputsTable "{'boundInpExpr'=>[''],'inputs'=>['sym_cfg']}" outputsTable "{'outputs'=>['load_base_rate','rotate_bpsk','load_htstf','load_htltf','load_full_rate','pil" "ot_shift','cyclic_prefix','cyclic_shift'],'suppressOut'=>['off','off','off','off','off','off','off','off']}" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "250,115,1,8,white,blue,0,d3620376,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 250 250 0 0 ],[0 0 115 115 0 ],[0." "77 0.82 0.91 ]);\nplot([0 250 250 0 0 ],[0 0 115 115 0 ]);\npatch([89.4 112.52 128.52 144.52 160.52 128.52 105." "4 89.4 ],[74.76 74.76 90.76 74.76 90.76 90.76 90.76 74.76 ],[1 1 1 ]);\npatch([105.4 128.52 112.52 89.4 105.4 ]" ",[58.76 58.76 74.76 74.76 58.76 ],[0.931 0.946 0.973 ]);\npatch([89.4 112.52 128.52 105.4 89.4 ],[42.76 42.76 5" "8.76 58.76 42.76 ],[1 1 1 ]);\npatch([105.4 160.52 144.52 128.52 112.52 89.4 105.4 ],[26.76 26.76 42.76 26.76 4" "2.76 42.76 26.76 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\ncolor('black');port_label('input',1,'sym_cfg');\ncolor('black');port_label('output',1,'load_bas" "e_rate');\ncolor('black');port_label('output',2,'rotate_bpsk');\ncolor('black');port_label('output',3,'load_hts" "tf');\ncolor('black');port_label('output',4,'load_htltf');\ncolor('black');port_label('output',5,'load_full_rat" "e');\ncolor('black');port_label('output',6,'pilot_shift');\ncolor('black');port_label('output',7,'cyclic_prefix" "');\ncolor('black');port_label('output',8,'cyclic_shift');\ncolor('black');disp('\\bf{sym\\_config\\_decode}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Mem Sel" SID "3484" Ports [1, 2] Position [1015, 347, 1075, 383] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mem Sel" Location [921, 416, 1350, 526] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "3486" Position [750, 733, 780, 747] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType From Name "From14" SID "3481" Position [695, 772, 780, 788] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "3480" Ports [1, 1] Position [1100, 711, 1130, 729] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "3488" Ports [2, 1] Position [850, 718, 885, 747] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 29 29 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3489" Ports [2, 1] Position [850, 747, 885, 778] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "3490" Ports [2, 1] Position [925, 758, 960, 787] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,29,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 29 29 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "3456" Ports [2, 1] Position [1000, 709, 1035, 796] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "3457" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "3458" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "3459" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "3460" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "3461" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3462" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3463" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Outport Name "Rd" SID "3487" Position [1190, 748, 1220, 762] IconDisplay "Port number" } Block { BlockType Outport Name "Wr" SID "3485" Position [1190, 713, 1220, 727] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [15, 0] Branch { Points [0, -35] DstBlock "Inverter" DstPort 1 } Branch { DstBlock "Rd" DstPort 1 } Branch { Points [0, 60; -240, 0; 0, -45] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [20, 0] Branch { DstBlock "Wr" DstPort 1 } Branch { Points [0, -30; -340, 0; 0, 35] DstBlock "Logical" DstPort 1 } } Line { SrcBlock "En" SrcPort 1 Points [30, 0] Branch { DstBlock "Logical" DstPort 2 } Branch { Points [0, 15] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Logical2" DstPort 2 } Annotation { Name "Simple circuit to toggle between 0 and 1 each time the En signal asserts." Position [966, 845] } } } Block { BlockType ToWorkspace Name "To Workspace" SID "3599" Ports [1] Position [985, 30, 1045, 60] ZOrder -7 VariableName "tx_bits_enc" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "3602" Ports [1] Position [985, 85, 1045, 115] ZOrder -7 VariableName "tx_bits_enc_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Outport Name " Sym Cfg" SID "1530" Position [1390, 448, 1420, 462] IconDisplay "Port number" } Block { BlockType Outport Name "Sc Bits" SID "1531" Position [1405, 288, 1435, 302] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Sym Bits Rdy" SID "1532" Position [1390, 493, 1420, 507] Port "3" IconDisplay "Port number" } Line { SrcBlock "Delay2" SrcPort 1 Points [320, 0; 0, 40] DstBlock "Interleave RAM" DstPort 2 } Line { SrcBlock "Delay1" SrcPort 1 Points [325, 0] DstBlock "Interleave RAM" DstPort 1 } Line { SrcBlock "Interleaver Ctrl &\nPuncturing" SrcPort 4 Points [205, 0] Branch { DstBlock "Interleave RAM" DstPort 6 } Branch { Points [0, 145] DstBlock "Delay6" DstPort 2 } } Line { SrcBlock "Interleaver Ctrl &\nPuncturing" SrcPort 3 DstBlock "Interleave RAM" DstPort 5 } Line { SrcBlock "Interleaver Ctrl &\nPuncturing" SrcPort 2 DstBlock "Interleave RAM" DstPort 4 } Line { SrcBlock "Interleaver Ctrl &\nPuncturing" SrcPort 1 DstBlock "Interleave RAM" DstPort 3 } Line { SrcBlock "MCode" SrcPort 1 DstBlock "Interleaver Ctrl &\nPuncturing" DstPort 2 } Line { SrcBlock "Bits tvalid" SrcPort 1 Points [25, 0] Branch { DstBlock "Interleaver Ctrl &\nPuncturing" DstPort 1 } Branch { Points [0, -165] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Bit B" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay2" DstPort 1 } Branch { Points [0, -165] DstBlock "Concat" DstPort 1 } } Line { SrcBlock "Bit A" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay1" DstPort 1 } Branch { Points [0, -110] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Interleave RAM" SrcPort 1 DstBlock "Sc Bits" DstPort 1 } Line { SrcBlock "Data Sym Ind" SrcPort 1 DstBlock "Interleave RAM" DstPort 7 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Delay6" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock " Sym Cfg" DstPort 1 } Line { SrcBlock "Sym Cfg" SrcPort 1 Points [95, 0] Branch { Points [0, 85] DstBlock "Delay3" DstPort 1 } Branch { DstBlock "MCode" DstPort 1 } } Line { SrcBlock "Bits tlast" SrcPort 1 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 Points [120, 0] Branch { DstBlock "Delay5" DstPort 1 } Branch { Points [0, -135] DstBlock "Mem Sel" DstPort 1 } } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "Sym Bits Rdy" DstPort 1 } Line { SrcBlock "Mem Sel" SrcPort 1 DstBlock "Interleave RAM" DstPort 8 } Line { SrcBlock "Mem Sel" SrcPort 2 DstBlock "Interleave RAM" DstPort 9 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Gateway Out7" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Annotation { Name "Interleaver RAM stores all bits for one OFDM\nsymbol. Bits can be read immediately after last\nbit" " for this OFDM sym is written to the RAM." Position [510, 502] } } } Block { BlockType Outport Name " Sym Cfg" SID "1533" Position [1550, 378, 1580, 392] IconDisplay "Port number" } Block { BlockType Outport Name "IQ stream" SID "1534" Position [1550, 443, 1580, 457] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "DATA Done" SID "1535" Position [855, 483, 885, 497] Port "3" IconDisplay "Port number" } Line { SrcBlock "Start Sym" SrcPort 1 DstBlock "Index Gen" DstPort 2 } Line { SrcBlock "Sym Cfg" SrcPort 1 DstBlock "Index Gen" DstPort 1 } Line { SrcBlock "Index Gen" SrcPort 1 DstBlock "Pkt Data" DstPort 1 } Line { SrcBlock "Index Gen" SrcPort 2 DstBlock "Pkt Data" DstPort 2 } Line { SrcBlock "Index Gen" SrcPort 3 DstBlock "Pkt Data" DstPort 3 } Line { SrcBlock "Index Gen" SrcPort 4 DstBlock "Pkt Data" DstPort 4 } Line { SrcBlock "Index Gen" SrcPort 5 DstBlock "Pkt Data" DstPort 5 } Line { SrcBlock "Pkt Data" SrcPort 1 DstBlock "Convolutional Encoder" DstPort 1 } Line { SrcBlock "Pkt Data" SrcPort 2 DstBlock "Convolutional Encoder" DstPort 2 } Line { SrcBlock "Pkt Data" SrcPort 3 DstBlock "Convolutional Encoder" DstPort 3 } Line { SrcBlock "Pkt Data" SrcPort 5 Points [20, 0; 0, 30] DstBlock "DATA Done" DstPort 1 } Line { SrcBlock "Pkt Data" SrcPort 4 DstBlock "Convolutional Encoder" DstPort 4 } Line { SrcBlock "Convolutional Encoder" SrcPort 1 DstBlock "Puncture & Interleave" DstPort 2 } Line { SrcBlock "Convolutional Encoder" SrcPort 2 DstBlock "Puncture & Interleave" DstPort 3 } Line { SrcBlock "Convolutional Encoder" SrcPort 3 DstBlock "Puncture & Interleave" DstPort 4 } Line { SrcBlock "Convolutional Encoder" SrcPort 4 DstBlock "Puncture & Interleave" DstPort 5 } Line { SrcBlock "Convolutional Encoder" SrcPort 5 DstBlock "Puncture & Interleave" DstPort 6 } Line { SrcBlock "Modulate" SrcPort 1 Points [10, 0; 0, -20; -360, 0; 0, 25] DstBlock "Puncture & Interleave" DstPort 1 } Line { SrcBlock "Puncture & Interleave" SrcPort 2 DstBlock "Modulate" DstPort 2 } Line { SrcBlock "Puncture & Interleave" SrcPort 1 DstBlock "Modulate" DstPort 1 } Line { SrcBlock "Puncture & Interleave" SrcPort 3 DstBlock "Modulate" DstPort 3 } Line { Name "I" Labels [0, 0] SrcBlock "Modulate" SrcPort 3 DstBlock "Bus Creator" DstPort 1 } Line { Name "Q" Labels [0, 0] SrcBlock "Modulate" SrcPort 4 DstBlock "Bus Creator" DstPort 2 } Line { SrcBlock "Bus Creator" SrcPort 1 DstBlock "IQ stream" DstPort 1 } Line { Name "IQ tvalid" Labels [0, 0] SrcBlock "Modulate" SrcPort 5 DstBlock "Bus Creator" DstPort 3 } Line { Name "IQ tlast" Labels [0, 0] SrcBlock "Modulate" SrcPort 6 DstBlock "Bus Creator" DstPort 4 } Line { SrcBlock "Modulate" SrcPort 2 DstBlock " Sym Cfg" DstPort 1 } Line { SrcBlock "IQ FIFO tready" SrcPort 1 Points [80, 0] DstBlock "Modulate" DstPort 4 } Annotation { Name "This block implements the actual Tx PHY pipeline, from data bits to I/Q samples." Position [941, 590] } } } Block { BlockType SubSystem Name "Preamble & Outputs" SID "1536" Ports [4] Position [1005, 83, 1085, 222] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Preamble & Outputs" Location [70, 90, 1679, 993] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Tx Start" SID "1537" Position [75, 368, 105, 382] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "1538" Position [495, 528, 525, 542] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "1539" Position [495, 558, 525, 572] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ tvalid" SID "1540" Position [495, 588, 525, 602] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "DAC Outputs" SID "1543" Ports [3, 2] Position [1215, 366, 1270, 534] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off Port { PortNumber 1 Name "DAC I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "DAC Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "DAC Outputs" Location [1400, 621, 1835, 888] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "1545" Position [350, 193, 380, 207] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "1546" Position [350, 283, 380, 297] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "En" SID "1544" Position [350, 208, 380, 222] Port "3" IconDisplay "Port number" } Block { BlockType SubSystem Name "Ant Enables" SID "1547" Ports [0, 4] Position [145, 227, 185, 288] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Ant Enables" Location [283, 306, 538, 989] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType From Name "From1" SID "1548" Position [145, 456, 280, 474] ZOrder -9 ShowName off GotoTag "regTx_AntB_Tx_En" TagVisibility "global" } Block { BlockType From Name "From2" SID "1549" Position [145, 341, 280, 359] ZOrder -9 ShowName off GotoTag "regTx_AntA_Tx_En" TagVisibility "global" } Block { BlockType From Name "From3" SID "1550" Position [145, 596, 280, 614] ZOrder -9 ShowName off GotoTag "regTx_AntC_Tx_En" TagVisibility "global" } Block { BlockType From Name "From4" SID "1551" Position [145, 721, 280, 739] ZOrder -9 ShowName off GotoTag "regTx_AntD_Tx_En" TagVisibility "global" } Block { BlockType From Name "From5" SID "1552" Position [110, 187, 245, 203] ZOrder -9 ShowName off GotoTag "MAC_Tx_Ant_Mask" TagVisibility "global" } Block { BlockType From Name "From6" SID "1553" Position [145, 397, 315, 413] ZOrder -9 ShowName off GotoTag "regTx_Use_MAC_Ant_Masks" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "1554" Ports [2, 1] Position [400, 376, 445, 414] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp(" "'and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1555" Ports [2, 1] Position [475, 341, 520, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp(" "'or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1556" Ports [2, 1] Position [405, 491, 450, 529] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp(" "'and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "1557" Ports [2, 1] Position [480, 456, 525, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp(" "'or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "1558" Ports [2, 1] Position [405, 631, 450, 669] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp(" "'and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "1559" Ports [2, 1] Position [480, 596, 525, 634] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp(" "'or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "1560" Ports [2, 1] Position [405, 756, 450, 794] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp(" "'and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "1561" Ports [2, 1] Position [480, 721, 525, 759] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp(" "'or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "1562" Ports [1, 1] Position [280, 187, 325, 203] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "1563" Ports [1, 1] Position [280, 222, 325, 238] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "1564" Ports [1, 1] Position [280, 262, 325, 278] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "1565" Ports [1, 1] Position [280, 297, 325, 313] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "A En" SID "1566" Position [600, 353, 630, 367] IconDisplay "Port number" } Block { BlockType Outport Name "B En" SID "1567" Position [600, 468, 630, 482] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "C En" SID "1568" Position [600, 608, 630, 622] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "D En" SID "1569" Position [600, 733, 630, 747] Port "4" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "A En" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 Points [5, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 35] DstBlock "b3" DstPort 1 } } } } Line { SrcBlock "Logical1" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical2" DstPort 2 } Line { SrcBlock "From6" SrcPort 1 Points [0, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 115] Branch { DstBlock "Logical3" DstPort 2 } Branch { Points [0, 140] Branch { DstBlock "Logical5" DstPort 2 } Branch { Points [0, 125] DstBlock "Logical7" DstPort 2 } } } } Line { SrcBlock "b0" SrcPort 1 Points [45, 0; 0, 190] DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical4" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 Points [40, 0; 0, 270] DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical5" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical6" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical6" DstPort 1 } Line { SrcBlock "b2" SrcPort 1 Points [35, 0; 0, 370] DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical8" DstPort 2 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Logical8" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "B En" DstPort 1 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "C En" DstPort 1 } Line { SrcBlock "b3" SrcPort 1 Points [30, 0; 0, 460] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Logical8" SrcPort 1 DstBlock "D En" DstPort 1 } } } Block { BlockType Reference Name "Inverter1" SID "1570" Ports [1, 1] Position [695, 216, 720, 234] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "1571" Ports [1, 1] Position [695, 431, 720, 449] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter3" SID "1572" Ports [1, 1] Position [695, 621, 720, 639] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter4" SID "1573" Ports [1, 1] Position [690, 811, 715, 829] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "1574" Ports [2, 1] Position [570, 206, 615, 244] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1575" Ports [2, 1] Position [570, 421, 615, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1576" Ports [2, 1] Position [570, 611, 615, 649] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1577" Ports [2, 1] Position [565, 801, 610, 839] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFA DAC I" SID "1578" Ports [1, 1] Position [885, 205, 945, 225] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFA DAC Q" SID "1579" Ports [1, 1] Position [885, 295, 945, 315] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFB DAC I" SID "1580" Ports [1, 1] Position [885, 420, 945, 440] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFB DAC Q" SID "1581" Ports [1, 1] Position [885, 510, 945, 530] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFC DAC I" SID "1582" Ports [1, 1] Position [885, 610, 945, 630] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFC DAC Q" SID "1583" Ports [1, 1] Position [885, 700, 945, 720] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFD DAC I" SID "1584" Ports [1, 1] Position [885, 800, 945, 820] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RFD DAC Q" SID "1585" Ports [1, 1] Position [885, 890, 945, 910] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "1586" Ports [2, 1] Position [760, 189, 820, 236] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,47,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 47 47 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[2" "9.66 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.6" "6 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 1" "7.66 ],[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.6" "6 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_lab" "el('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "1587" Ports [2, 1] Position [760, 279, 820, 326] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,47,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 47 47 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[2" "9.66 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.6" "6 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 1" "7.66 ],[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.6" "6 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_lab" "el('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register10" SID "1588" Ports [1, 1] Position [480, 275, 515, 305] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1589" Ports [2, 1] Position [760, 404, 820, 451] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,47,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 47 47 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[2" "9.66 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.6" "6 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 1" "7.66 ],[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.6" "6 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_lab" "el('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "1590" Ports [2, 1] Position [760, 494, 820, 541] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,47,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 47 47 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[2" "9.66 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.6" "6 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 1" "7.66 ],[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.6" "6 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_lab" "el('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "1591" Ports [2, 1] Position [760, 594, 820, 641] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,47,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 47 47 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[2" "9.66 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.6" "6 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 1" "7.66 ],[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.6" "6 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_lab" "el('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "1592" Ports [2, 1] Position [760, 684, 820, 731] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,47,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 47 47 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[2" "9.66 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.6" "6 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 1" "7.66 ],[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.6" "6 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_lab" "el('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "1593" Ports [2, 1] Position [760, 784, 820, 831] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,47,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 47 47 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[2" "9.66 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.6" "6 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 1" "7.66 ],[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.6" "6 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_lab" "el('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "1594" Ports [2, 1] Position [760, 874, 820, 921] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "60,47,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 47 47 0 ]);\npatch([16.65 25.32 31.32 37.32 43.32 31.32 22.65 16.65 ],[2" "9.66 29.66 35.66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([22.65 31.32 25.32 16.65 22.65 ],[23.66 23.6" "6 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([16.65 25.32 31.32 22.65 16.65 ],[17.66 17.66 23.66 23.66 1" "7.66 ],[1 1 1 ]);\npatch([22.65 43.32 37.32 31.32 25.32 16.65 22.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.6" "6 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_lab" "el('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "1595" Ports [1, 1] Position [480, 185, 515, 215] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register9" SID "1596" Ports [1, 1] Position [480, 200, 515, 230] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " I" SID "1597" Position [970, 208, 1000, 222] IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "1598" Position [970, 298, 1000, 312] Port "2" IconDisplay "Port number" } Line { SrcBlock "Register1" SrcPort 1 DstBlock "RFA DAC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "RFA DAC I" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 Points [10, 0] Branch { DstBlock "Register" DstPort 2 } Branch { Points [0, 90] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Inverter1" DstPort 1 } Line { SrcBlock "I" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "RFA DAC I" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { SrcBlock "RFA DAC Q" SrcPort 1 DstBlock " Q" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "RFB DAC Q" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "RFB DAC I" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "Ant Enables" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Inverter2" DstPort 1 } Line { SrcBlock "Inverter2" SrcPort 1 Points [5, 0] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, 90] DstBlock "Register3" DstPort 2 } } Line { SrcBlock "Ant Enables" SrcPort 2 Points [55, 0; 0, 200] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "RFC DAC Q" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "RFC DAC I" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Inverter3" DstPort 1 } Line { SrcBlock "Inverter3" SrcPort 1 Points [5, 0] Branch { Points [0, 90] DstBlock "Register5" DstPort 2 } Branch { DstBlock "Register4" DstPort 2 } } Line { SrcBlock "Register7" SrcPort 1 DstBlock "RFD DAC Q" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "RFD DAC I" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Inverter4" DstPort 1 } Line { SrcBlock "Inverter4" SrcPort 1 Points [5, 0] Branch { DstBlock "Register6" DstPort 2 } Branch { Points [0, 90] DstBlock "Register7" DstPort 2 } } Line { SrcBlock "Ant Enables" SrcPort 4 Points [25, 0; 0, 550] DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Register8" SrcPort 1 Points [160, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 215] Branch { DstBlock "Register2" DstPort 1 } Branch { Points [0, 190] Branch { DstBlock "Register4" DstPort 1 } Branch { Points [0, 190] DstBlock "Register6" DstPort 1 } } } } Line { SrcBlock "Register9" SrcPort 1 Points [25, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 215] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 190] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 190] DstBlock "Logical3" DstPort 1 } } } } Line { SrcBlock "Register10" SrcPort 1 Points [150, 0] Branch { DstBlock "Register1" DstPort 1 } Branch { Points [0, 215] Branch { DstBlock "Register3" DstPort 1 } Branch { Points [0, 190] Branch { DstBlock "Register5" DstPort 1 } Branch { Points [0, 190] DstBlock "Register7" DstPort 1 } } } } Line { SrcBlock "Ant Enables" SrcPort 3 Points [35, 0; 0, 375] DstBlock "Logical2" DstPort 2 } } } Block { BlockType Reference Name "Delay2" SID "1600" Ports [1, 1] Position [1065, 705, 1100, 735] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "12" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,30,1,1,white,blue,0,aa753640,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-12}','texmode','on')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "End of Tx Ctrl" SID "3528" Ports [2, 1] Position [1005, 606, 1100, 659] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "End of Tx Ctrl" Location [-788, 811, -448, 896] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "94" Block { BlockType Inport Name "FIFO Emtpy" SID "3529" Position [350, 388, 380, 402] IconDisplay "Port number" } Block { BlockType Inport Name "Tx Started" SID "3531" Position [350, 358, 380, 372] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Delay2" SID "3532" Ports [1, 1] Position [520, 380, 555, 410] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,30,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "3547" Position [410, 414, 505, 436] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Logical3" SID "3548" Ports [2, 1] Position [640, 388, 675, 417] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,29,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 29 29 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "3533" Ports [1, 1] Position [435, 358, 480, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "3534" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "3535" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "3536" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3537" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3538" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge1" SID "3549" Ports [1, 1] Position [435, 388, 480, 402] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "3550" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "3551" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "3552" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3553" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3554" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } } } Block { BlockType SubSystem Name "S-R Latch" SID "3539" Ports [2, 1] Position [715, 346, 755, 424] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [13, 209, 2156, 1324] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "3540" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "3541" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "3542" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "3543" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "3544" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3545" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "3546" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType Outport Name "Output En" SID "3530" Position [870, 378, 900, 392] IconDisplay "Port number" } Line { SrcBlock "FIFO Emtpy" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Tx Started" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "From" SrcPort 1 Points [55, 0; 0, -15] DstBlock "Logical3" DstPort 2 } Line { SrcBlock "S-R Latch" SrcPort 1 DstBlock "Output En" DstPort 1 } Annotation { Name "Delay for latency between FIFO and \nDAC outputs (scaling mults, output regs)" Position [536, 252] } } } Block { BlockType SubSystem Name "FIFO" SID "1601" Ports [5, 3] Position [780, 484, 865, 646] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FIFO" Location [323, 656, 1078, 838] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Reset" SID "1602" Position [265, 478, 295, 492] IconDisplay "Port number" } Block { BlockType Inport Name "FFT I" SID "1603" Position [290, 188, 320, 202] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "FFT Q" SID "1604" Position [290, 213, 320, 227] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Write" SID "1605" Position [290, 273, 320, 287] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Rd" SID "1606" Position [435, 303, 465, 317] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Constant2" SID "1541" Ports [0, 1] Position [860, 344, 890, 366] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "1542" Ports [0, 1] Position [290, 136, 320, 164] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "-1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,28,0,1,white,blue,0,43c97d40,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('output',1,'-1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1607" Ports [1, 1] Position [350, 476, 370, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "20,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('o" "utput',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "1608" Ports [1, 1] Position [310, 396, 335, 424] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "12" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,aa753640,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncol" "or('black');disp('z^{-12}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FIFO" SID "1609" Ports [4, 4] Position [670, 238, 750, 352] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/FIFO" SourceType "Xilinx FIFO Block Block" mem_type "Block RAM" performance_options "Standard_FIFO" infoedit1 "Available only for V4, V5, V6, V7, K7, A7 and Zynq devices." embedded_registers on depth "256" percent_nbits "1" rst on en off use_dcount on use_percent_full_port off use_almost_empty off almost_empty_thresh "2" use_almost_full off almost_full_thresh "14" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" explicit_period "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fifo" sg_icon_stat "80,114,4,4,white,blue,0,fe9860ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 114 114 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 114 114 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.5" "25 ],[69.21 69.21 80.21 69.21 80.21 80.21 80.21 69.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[" "58.21 58.21 69.21 69.21 58.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[47.21 47.21 " "58.21 58.21 47.21 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[36.21 36.21 47.21 36.21 " "47.21 47.21 36.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: beg" "in icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'we');\ncolor" "('black');port_label('input',3,'re');\ncolor('black');port_label('input',4,'rst');\ncolor('black');port_label('" "output',1,'dout');\ncolor('black');port_label('output',2,'empty');\ncolor('black');port_label('output',3,'full'" ");\ncolor('black');port_label('output',4,'dcount');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From4" SID "1610" Position [155, 399, 250, 421] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "1647" Position [895, 302, 1045, 318] ZOrder -10 ShowName off GotoTag "OUTPUT_FIFO_OCC" TagVisibility "global" } Block { BlockType SubSystem Name "I/Q Concat" SID "1611" Ports [2, 1] Position [385, 182, 425, 233] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Concat" Location [522, 447, 879, 615] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "1612" Position [105, 123, 135, 137] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "1613" Position [105, 158, 135, 172] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "1614" Ports [2, 1] Position [500, 110, 535, 185] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,75,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 75 75 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 75 75 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[42.55 42.55 47." "55 42.55 47.55 47.55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 42.55 37." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[32.55 32.55 37.55 37.55 32.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 27.55 32.55 32.55 27.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "1615" Ports [1, 1] Position [275, 120, 300, 140] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cas" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1616" Ports [1, 1] Position [275, 155, 300, 175] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14" ".22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22" " ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9." "55 16.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cas" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "FFT Clip" SID "1617" Ports [4] Position [495, 271, 535, 334] ZOrder -3 Floating off Location [1255, 123, 2246, 1467] Open off NumInputPorts "4" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" } TimeRange "30000" YMin "0~0~0~-0.1" YMax "300~300~1~1.1" SaveName "ScopeData11" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out1" SID "1618" Ports [1, 1] Position [395, 289, 430, 301] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out14" SID "1619" Ports [1, 1] Position [395, 274, 430, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out2" SID "1620" Ports [1, 1] Position [395, 319, 430, 331] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out3" SID "1621" Ports [1, 1] Position [395, 304, 430, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Reinterpret" SID "1622" Ports [1, 1] Position [390, 119, 430, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "1623" Ports [1, 1] Position [390, 154, 430, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ" SID "1624" Position [605, 143, 635, 157] IconDisplay "Port number" } Line { SrcBlock "Q" SrcPort 1 Points [100, 0] Branch { DstBlock "Convert1" DstPort 1 } Branch { Points [0, 130] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Concat" SrcPort 1 DstBlock "IQ" DstPort 1 } Line { SrcBlock "I" SrcPort 1 Points [105, 0] Branch { DstBlock "Convert" DstPort 1 } Branch { Points [0, 150] DstBlock "Gateway Out14" DstPort 1 } } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [25, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, 180] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [20, 0] Branch { DstBlock "Reinterpret1" DstPort 1 } Branch { Points [0, 160] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Gateway Out14" SrcPort 1 DstBlock "FFT Clip" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FFT Clip" DstPort 2 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FFT Clip" DstPort 3 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FFT Clip" DstPort 4 } } } Block { BlockType SubSystem Name "I/Q Slice" SID "1625" Ports [1, 2] Position [800, 230, 850, 265] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Slice" Location [1155, 565, 1558, 696] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "1626" Position [190, 123, 220, 137] IconDisplay "Port number" } Block { BlockType Reference Name "Reinterpret2" SID "1627" Ports [1, 1] Position [350, 119, 390, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "1628" Ports [1, 1] Position [350, 144, 390, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "1629" Ports [1, 1] Position [265, 119, 300, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "1630" Ports [1, 1] Position [265, 144, 300, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "1631" Position [450, 123, 480, 137] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "1632" Position [450, 148, 480, 162] Port "2" IconDisplay "Port number" } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 Points [15, 0] Branch { Points [0, 25] DstBlock "Slice1" DstPort 1 } Branch { DstBlock "Slice" DstPort 1 } } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType Reference Name "Logical4" SID "1633" Ports [2, 1] Position [465, 403, 500, 432] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,29,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 29 29 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 29 29 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "2599" Ports [1, 1] Position [590, 236, 615, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "2600" Ports [1, 1] Position [590, 266, 615, 294] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2601" Ports [1, 1] Position [590, 326, 615, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "1683" Ports [2, 1] Position [950, 330, 990, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "40,35,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55" " 22.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22" ".55 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output'," "1,'\\bfa = b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " I" SID "1634" Position [990, 233, 1020, 247] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "1635" Position [990, 248, 1020, 262] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " Empty" SID "1636" Position [1060, 343, 1090, 357] Port "3" IconDisplay "Port number" } Line { SrcBlock "FFT Q" SrcPort 1 DstBlock "I/Q Concat" DstPort 2 } Line { SrcBlock "FFT I" SrcPort 1 DstBlock "I/Q Concat" DstPort 1 } Line { SrcBlock "I/Q Slice" SrcPort 2 DstBlock " Q" DstPort 1 } Line { SrcBlock "I/Q Slice" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "I/Q Concat" SrcPort 1 Points [65, 0; 0, 40] DstBlock "Register" DstPort 1 } Line { SrcBlock "Write" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "FIFO" SrcPort 1 DstBlock "I/Q Slice" DstPort 1 } Line { SrcBlock "Rd" SrcPort 1 DstBlock "FIFO" DstPort 3 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 Points [45, 0; 0, -80] DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 Points [35, 0; 0, -60] DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "FIFO" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "FIFO" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "FIFO" DstPort 4 } Line { SrcBlock "FIFO" SrcPort 4 Points [95, 0] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, -30] DstBlock "Goto2" DstPort 1 } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock " Empty" DstPort 1 } Annotation { Name "Use constant in place of actual FFT signal to debug timing\nof samples at FIFO output and preamble" "/payload mux " Position [309, 113] } Annotation { Name "The register blocks around the FIFO fix apparent issues in hardware\nwhere the FIFO would, on some" " downloads, insert an extra sample\nafter the preamble, before the payload. This is a sim/hardwrae mismatch\nI " "never traced to a root cause. It definitely felt like a problem with\ncombinational signals driving the FIFO po" "rts, somehow inducing\nunexpected, seemingly asychronous, behaviors in hardware that do \nnot occur in simulati" "on. The DFFs around the FIFO fixed it." Position [632, 517] HorizontalAlignment "left" } } } Block { BlockType From Name "From" SID "1637" Position [15, 389, 110, 411] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType From Name "From1" SID "2606" Position [1165, 192, 1300, 208] ZOrder -9 ShowName off GotoTag "OUTPUT_FIFO_OCC" TagVisibility "global" } Block { BlockType From Name "From6" SID "1638" Position [140, 632, 275, 648] ZOrder -9 ShowName off GotoTag "TX_IQ_SAMP_CE" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "1639" Ports [1, 1] Position [1405, 179, 1440, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Preamble Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out14" SID "1640" Ports [1, 1] Position [1405, 164, 1440, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Tx Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "1641" Ports [1, 1] Position [1405, 194, 1440, 206] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO Occ" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "1642" Ports [1, 1] Position [1405, 209, 1440, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO Rd En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "1644" Ports [1, 1] Position [1405, 254, 1440, 266] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO Wr En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto1" SID "1646" Position [1160, 712, 1340, 728] ZOrder -10 ShowName off GotoTag "LAST_SAMP_OUTPUT_TO_DACS" TagVisibility "global" } Block { BlockType Reference Name "Logical2" SID "1650" Ports [3, 1] Position [625, 601, 660, 649] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,48,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 48 48 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[29.55 29.55 34.55" " 29.55 34.55 34.55 34.55 29.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[24.55 24.55 29.55 29.55 24.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[19.55 19.55 24.55 24.55 19.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[14.55 14.55 19.55 14.55 19.55 19.55 14.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "2380" Ports [2, 1] Position [975, 703, 1010, 732] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,29,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 29 29 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.44 " "18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Scope Name "Outputs" SID "1653" Ports [10] Position [1575, 167, 1610, 308] ZOrder -3 Floating off Location [6, 40, 1841, 1194] Open off NumInputPorts "10" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "6000" YMin "0~0~0~0~-1~-1~-0.1~-1~-0.5~-1" YMax "1~1~250~1~1~1~1.1~0.5~0.5~1" SaveName "ScopeData20" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Posedge" SID "1654" Ports [1, 1] Position [165, 368, 210, 382] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1655" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "1656" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "1657" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1658" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1659" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "Preamble Gen" SID "1660" Ports [2, 4] Position [435, 367, 555, 453] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Preamble Gen" Location [905, 651, 1420, 870] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "121" Block { BlockType Inport Name "Tx Running" SID "1661" Position [390, 338, 420, 352] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Rd En" SID "1662" Position [390, 358, 420, 372] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant3" SID "1663" Ports [0, 1] Position [755, 404, 785, 426] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "length(Preamble_IQ)-1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "ceil(log2(length(Preamble_IQ)))" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,93ce2787,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'319');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "1664" Ports [2, 1] Position [670, 333, 720, 377] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(length(Preamble_IQ)))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "50,44,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 44 44 0 ]);\npatch([11.65 20.32 26.32 32.32 38.32 26.32 17.65 11.65 ],[2" "8.66 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([17.65 26.32 20.32 11.65 17.65 ],[22.66 22.6" "6 28.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([11.65 20.32 26.32 17.65 11.65 ],[16.66 16.66 22.66 22.66 1" "6.66 ],[1 1 1 ]);\npatch([17.65 38.32 32.32 26.32 20.32 11.65 17.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.6" "6 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n" "color('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp(" "'{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "1665" Ports [1, 1] Position [485, 216, 510, 244] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "4" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "25,28,1,1,white,blue,0,d390c2d8,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17" ".33 17.33 20.33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 " "17.33 17.33 14.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncol" "or('black');disp('z^{-4}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "1666" Position [305, 219, 400, 241] ZOrder -9 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "1667" Ports [1, 1] Position [755, 270, 785, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,20,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1668" Ports [3, 1] Position [565, 338, 600, 392] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,54,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 54 54 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 54 54 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55" " 32.55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32" ".55 32.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Preamble I" SID "1669" Ports [1, 1] Position [825, 337, 895, 373] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(Preamble_IQ_scaled)" initVector "real(Preamble_IQ_scaled)" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "70,36,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 70 70 0 0 ],[0 0 36 36 0 ]);\npatch([23.875 31.1 36.1 41.1 46.1 36.1 28.875 23.875 ],[23." "55 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([28.875 36.1 31.1 23.875 28.875 ],[18.55 18.55" " 23.55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([23.875 31.1 36.1 28.875 23.875 ],[13.55 13.55 18.55 18.55 1" "3.55 ],[1 1 1 ]);\npatch([28.875 46.1 41.1 36.1 31.1 23.875 28.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT:" " end icon text');" } Block { BlockType Reference Name "Preamble Q" SID "1670" Ports [1, 1] Position [825, 427, 895, 463] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "length(Preamble_IQ_scaled)" initVector "imag(Preamble_IQ_scaled)" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "70,36,1,1,white,blue,0,bbc23d60,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 36 36 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 70 70 0 0 ],[0 0 36 36 0 ]);\npatch([23.875 31.1 36.1 41.1 46.1 36.1 28.875 23.875 ],[23." "55 23.55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([28.875 36.1 31.1 23.875 28.875 ],[18.55 18.55" " 23.55 23.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([23.875 31.1 36.1 28.875 23.875 ],[13.55 13.55 18.55 18.55 1" "3.55 ],[1 1 1 ]);\npatch([28.875 46.1 41.1 36.1 31.1 23.875 28.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolo" "r('black');port_label('input',1,'addr');\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT:" " end icon text');" } Block { BlockType Reference Name "Register" SID "1671" Ports [3, 1] Position [840, 274, 885, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,42,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27." "66 27.66 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 2" "7.66 27.66 21.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input" "',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "1672" Ports [3, 1] Position [1000, 289, 1045, 331] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,42,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27." "66 27.66 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 2" "7.66 27.66 21.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input" "',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1673" Ports [3, 1] Position [1000, 349, 1045, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,42,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27." "66 27.66 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 2" "7.66 27.66 21.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input" "',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "1674" Ports [3, 1] Position [1000, 439, 1045, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,42,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27." "66 27.66 33.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 2" "7.66 27.66 21.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input" "',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf(" "'','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "1675" Ports [2, 1] Position [675, 390, 715, 425] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1688" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1689" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1690" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1691" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "Scaling" SID "2608" Ports [5, 2] Position [1005, 363, 1110, 477] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Scaling" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Payload Sel" SID "2609" Position [280, 363, 310, 377] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Preamble I" SID "2610" Position [280, 418, 310, 432] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Preamble Q" SID "2611" Position [280, 508, 310, 522] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Payload I" SID "2623" Position [280, 438, 310, 452] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Payload Q" SID "2624" Position [280, 528, 310, 542] Port "5" IconDisplay "Port number" } Block { BlockType Display Name "Display" SID "2612" Ports [1] Position [950, 720, 1040, 750] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "2613" Ports [1] Position [950, 765, 1040, 795] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From" SID "2614" Position [570, 618, 750, 642] ZOrder -9 ShowName off GotoTag "regTx_Scaling_Preamble" TagVisibility "global" } Block { BlockType From Name "From1" SID "2615" Position [570, 588, 750, 612] ZOrder -9 ShowName off GotoTag "regTx_Scaling_Payload" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "2616" Ports [1, 1] Position [865, 774, 900, 786] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out5" SID "2617" Ports [1, 1] Position [865, 729, 900, 741] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "2618" Ports [2, 1] Position [995, 540, 1050, 595] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier " "you must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric " "(LUTs), the Speed or Area optimization will take effect only if it's supported by IP for the particular device " "family. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" quantization "Truncate" overflow "Saturate" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,55,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 55 55 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[34.77 34.77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[27.7" "7 27.77 34.77 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[20.77 20.77 27.7" "7 27.77 20.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[13.77 13.77 20.77 13.77 20.7" "7 20.77 13.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black" "');port_label('output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','" "on');\ncolor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "2619" Ports [2, 1] Position [995, 630, 1050, 685] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier " "you must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric " "(LUTs), the Speed or Area optimization will take effect only if it's supported by IP for the particular device " "family. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" quantization "Truncate" overflow "Saturate" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "55,55,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 55 55 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[34.77 34.77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[27.7" "7 27.77 34.77 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[20.77 20.77 27.7" "7 27.77 20.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[13.77 13.77 20.77 13.77 20.7" "7 20.77 13.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black" "');port_label('output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','" "on');\ncolor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "2625" Ports [3, 1] Position [410, 392, 445, 458] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,66,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 9.42857 56.5714 66 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 9.42857 56.5714 66 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1" " 10.875 5.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 43.55 38.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10" ".875 ],[33.55 33.55 38.55 38.55 33.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[28.55 28" ".55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[23.55 23.55 28.55 23.55 2" "8.55 28.55 23.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor(" "'black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end" " icon text');" } Block { BlockType Reference Name "Mux1" SID "2620" Ports [3, 1] Position [810, 556, 840, 644] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,88,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 12.5714 75.4286 88 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 12.5714 75.4286 88 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15" ".88 10.1 6.1 ],[48.44 48.44 52.44 48.44 52.44 52.44 52.44 48.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 " "],[44.44 44.44 48.44 48.44 44.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[40.44 40.44 44.44" " 44.44 40.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[36.44 36.44 40.44 36.44 40.44 40.44 " "36.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text" "');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');po" "rt_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text'" ");" } Block { BlockType Reference Name "Mux2" SID "2626" Ports [3, 1] Position [410, 482, 445, 548] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "35,66,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 9.42857 56.5714 66 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 9.42857 56.5714 66 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1" " 10.875 5.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 43.55 38.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10" ".875 ],[33.55 33.55 38.55 38.55 33.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[28.55 28" ".55 33.55 33.55 28.55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[23.55 23.55 28.55 23.55 2" "8.55 28.55 23.55 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi" "n icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor(" "'black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end" " icon text');" } Block { BlockType Reference Name "Register1" SID "2627" Ports [1, 1] Position [535, 503, 560, 527] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "2628" Ports [1, 1] Position [535, 358, 560, 382] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "2629" Ports [1, 1] Position [535, 413, 560, 437] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "25,24,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ]" ",[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode" "','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " I" SID "2621" Position [1115, 563, 1145, 577] IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "2622" Position [1115, 653, 1145, 667] Port "2" IconDisplay "Port number" } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Display1" DstPort 1 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "From" SrcPort 1 Points [15, 0] Branch { Points [0, 150] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "Mux1" DstPort 3 } } Line { SrcBlock "Register5" SrcPort 1 Points [170, 0; 0, 200] DstBlock "Mux1" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [25, 0] Branch { Points [0, 135] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "Mux1" DstPort 2 } } Line { SrcBlock "Mux1" SrcPort 1 Points [60, 0] Branch { Points [0, 45] DstBlock "Mult1" DstPort 1 } Branch { Points [0, -20] DstBlock "Mult" DstPort 2 } } Line { SrcBlock "Register1" SrcPort 1 Points [320, 0; 0, 155] DstBlock "Mult1" DstPort 2 } Line { SrcBlock "Register8" SrcPort 1 Points [325, 0; 0, 130] DstBlock "Mult" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 DstBlock " Q" DstPort 1 } Line { SrcBlock "Mult" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Payload Sel" SrcPort 1 Points [65, 0] Branch { DstBlock "Register5" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 90] DstBlock "Mux2" DstPort 1 } } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Payload I" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Payload Q" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Preamble I" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Preamble Q" SrcPort 1 DstBlock "Mux2" DstPort 2 } } } Block { BlockType ToWorkspace Name "To Workspace" SID "1707" Ports [1] Position [1480, 475, 1540, 505] ZOrder -7 VariableName "wlan_tx_out" MaxDataPoints "inf" Decimation "160 / tx_sim.samp_rate" SampleTime "-1" SaveFormat "Array" } Line { Labels [0, 0] SrcBlock "Logical2" SrcPort 1 Points [15, 0] Branch { DstBlock "Register3" DstPort 1 } Branch { Points [0, 100] DstBlock "Register4" DstPort 1 } } Line { SrcBlock "Posedge" SrcPort 1 Points [25, 0] Branch { DstBlock "S-R Latch" DstPort 1 } Branch { Points [0, 130] DstBlock "FIFO" DstPort 1 } } Line { SrcBlock "Tx Start" SrcPort 1 Points [20, 0] Branch { DstBlock "Posedge" DstPort 1 } Branch { Points [0, -205] DstBlock "Gateway Out14" DstPort 1 } } Line { SrcBlock "From" SrcPort 1 DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [35, 0] Branch { DstBlock "Preamble Gen" DstPort 1 } Branch { Points [0, 235] Branch { DstBlock "Logical2" DstPort 2 } Branch { Labels [0, 0] Points [0, 50; 600, 0; 0, -30] DstBlock "End of Tx Ctrl" DstPort 2 } } } Line { SrcBlock "Q" SrcPort 1 DstBlock "FIFO" DstPort 3 } Line { SrcBlock "IQ tvalid" SrcPort 1 Points [225, 0] Branch { DstBlock "FIFO" DstPort 4 } Branch { Points [0, -335] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "FIFO" SrcPort 1 Points [70, 0; 0, -70] DstBlock "Scaling" DstPort 4 } Line { Name "DAC I" SrcBlock "DAC Outputs" SrcPort 1 Points [75, 0] Branch { Points [0, 70] DstBlock "Real-Imag to\nComplex" DstPort 1 } Branch { Labels [-1, 0] Points [0, -135] DstBlock "Outputs" DstPort 8 } } Line { SrcBlock "Preamble Gen" SrcPort 2 DstBlock "Scaling" DstPort 2 } Line { Name "Tx Start" Labels [-1, 0] SrcBlock "Gateway Out14" SrcPort 1 DstBlock "Outputs" DstPort 1 } Line { Name "Preamble Done" Labels [-1, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Outputs" DstPort 2 } Line { Name "FIFO Occ" Labels [-1, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Outputs" DstPort 3 } Line { Name "FIFO Rd En" Labels [-1, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Outputs" DstPort 4 } Line { SrcBlock "Preamble Gen" SrcPort 1 Points [375, 0] Branch { Points [0, -195] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "Scaling" DstPort 1 } } Line { SrcBlock "Real-Imag to\nComplex" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { Name "DAC Q" SrcBlock "DAC Outputs" SrcPort 2 Points [70, 0] Branch { DstBlock "Real-Imag to\nComplex" DstPort 2 } Branch { Labels [-1, 0] Points [0, -205] DstBlock "Outputs" DstPort 9 } } Line { SrcBlock "Preamble Gen" SrcPort 3 DstBlock "Scaling" DstPort 3 } Line { SrcBlock "FIFO" SrcPort 2 Points [75, 0; 0, -105] DstBlock "Scaling" DstPort 5 } Line { SrcBlock "Scaling" SrcPort 1 DstBlock "DAC Outputs" DstPort 1 } Line { Name "FIFO Wr En" Labels [-1, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Outputs" DstPort 7 } Line { SrcBlock "Preamble Gen" SrcPort 4 Points [20, 0; 0, 170] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "I" SrcPort 1 DstBlock "FIFO" DstPort 2 } Line { SrcBlock "FIFO" SrcPort 3 Points [30, 0] Branch { Points [0, 90] DstBlock "Logical3" DstPort 1 } Branch { Labels [0, 0] DstBlock "End of Tx Ctrl" DstPort 1 } } Line { SrcBlock "From6" SrcPort 1 Points [35, 0] Branch { DstBlock "Logical2" DstPort 3 } Branch { Points [0, -205] DstBlock "Register2" DstPort 1 } } Line { SrcBlock "End of Tx Ctrl" SrcPort 1 Points [70, 0; 0, -130] DstBlock "DAC Outputs" DstPort 3 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Preamble Gen" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 Points [5, 0] Branch { DstBlock "FIFO" DstPort 5 } Branch { Points [0, -410] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Gateway Out2" DstPort 1 } Line { SrcBlock "Scaling" SrcPort 2 DstBlock "DAC Outputs" DstPort 2 } Annotation { Name "1 sample period + margin\nfor ctrl latencies" Position [1092, 755] } Annotation { Name "DFFs to isolate FIFO inputs from combinational\nsignals, part of the hardware/sim mismatch debug.\nSee no" "te in FIFO block for more info." Position [734, 760] } } } Block { BlockType SubSystem Name "Radio Controller\n& MAC IO" SID "2385" Ports [] Position [770, 354, 828, 414] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio Controller\n& MAC IO" Location [2, 74, 2469, 1176] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Constant Name "Constant" SID "2477" Position [310, 300, 335, 320] ZOrder -4 ShowName off Value "0" } Block { BlockType Constant Name "Constant1" SID "2478" Position [310, 250, 335, 270] ZOrder -4 ShowName off } Block { BlockType Constant Name "Constant3" SID "2522" Position [230, 370, 335, 390] ZOrder -4 ShowName off Value "tx_sim.PHY_mode" } Block { BlockType Reference Name "Convert1" SID "2492" Ports [1, 1] Position [545, 116, 570, 134] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "2493" Ports [1, 1] Position [1235, 116, 1260, 134] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Delay Name "Delay" SID "2559" Ports [1, 1] Position [425, 172, 450, 198] ShowName off InputPortMap "u0" DelayLength "16" ExternalReset "None" } Block { BlockType From Name "From1" SID "2475" Position [175, 432, 350, 448] ZOrder -9 BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_STARTED" TagVisibility "global" } Block { BlockType From Name "From11" SID "2488" Position [900, 537, 1055, 553] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TX_GAIN_C" TagVisibility "global" } Block { BlockType From Name "From12" SID "2489" Position [900, 577, 1055, 593] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TX_GAIN_D" TagVisibility "global" } Block { BlockType From Name "From2" SID "2476" Position [175, 477, 350, 493] ZOrder -9 BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_DONE" TagVisibility "global" } Block { BlockType From Name "From3" SID "2481" Position [900, 182, 1055, 198] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TXEN_A" TagVisibility "global" } Block { BlockType From Name "From4" SID "2482" Position [900, 222, 1055, 238] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TXEN_B" TagVisibility "global" } Block { BlockType From Name "From5" SID "2483" Position [900, 262, 1055, 278] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TXEN_C" TagVisibility "global" } Block { BlockType From Name "From6" SID "2484" Position [900, 302, 1055, 318] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TXEN_D" TagVisibility "global" } Block { BlockType From Name "From7" SID "2485" Position [900, 377, 1055, 393] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_RXEN" TagVisibility "global" } Block { BlockType From Name "From8" SID "2486" Position [900, 457, 1055, 473] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TX_GAIN_A" TagVisibility "global" } Block { BlockType From Name "From9" SID "2487" Position [900, 497, 1055, 513] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TX_GAIN_B" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "2523" Position [610, 372, 785, 388] BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_PHY_MODE" TagVisibility "global" } Block { BlockType Goto Name "Goto10" SID "2415" Position [610, 117, 785, 133] BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_START" TagVisibility "global" } Block { BlockType Goto Name "Goto11" SID "2479" Position [1290, 117, 1445, 133] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_PHY_START" TagVisibility "global" } Block { BlockType Goto Name "Goto13" SID "2426" Position [610, 252, 790, 268] BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_ANT_MASK" TagVisibility "global" } Block { BlockType Goto Name "Goto14" SID "2434" Position [610, 302, 785, 318] BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_PKT_BUF" TagVisibility "global" } Block { BlockType Reference Name "PHY_TX_ANT_MASK" SID "2425" Ports [1, 1] Position [405, 250, 470, 270] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "PHY_TX_DONE" SID "2419" Ports [1, 1] Position [410, 475, 470, 495] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "PHY_TX_PHY_MODE" SID "2521" Ports [1, 1] Position [405, 370, 470, 390] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "PHY_TX_PKT_BUF" SID "2433" Ports [1, 1] Position [405, 300, 470, 320] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "4" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "PHY_TX_START" SID "2413" Ports [1, 1] Position [405, 115, 470, 135] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "PHY_TX_STARTED" SID "2420" Ports [1, 1] Position [410, 430, 470, 450] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "PHY_TX_STARTED" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "RC_PHY_START" SID "2037" Ports [1, 1] Position [1105, 115, 1170, 135] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Reference Name "RC_TX_GAIN_A" SID "2381" Ports [1, 1] Position [1110, 455, 1170, 475] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "RC_TX_GAIN_B" SID "2382" Ports [1, 1] Position [1110, 495, 1170, 515] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "RC_TX_GAIN_C" SID "2383" Ports [1, 1] Position [1110, 535, 1170, 555] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "RC_TX_GAIN_D" SID "2384" Ports [1, 1] Position [1110, 575, 1170, 595] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "RC_USR_RXEN" SID "2402" Ports [1, 1] Position [1110, 375, 1170, 395] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "RC_USR_TXEN_A" SID "2121" Ports [1, 1] Position [1110, 180, 1170, 200] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "RC_USR_TXEN_B" SID "2122" Ports [1, 1] Position [1110, 220, 1170, 240] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "RC_USR_TXEN_C" SID "2123" Ports [1, 1] Position [1110, 260, 1170, 280] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "RC_USR_TXEN_D" SID "2124" Ports [1, 1] Position [1110, 300, 1170, 320] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType SubSystem Name "Simulation Start-Stop" SID "3391" Ports [1, 1] Position [410, 537, 565, 583] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Simulation Start-Stop" Location [1272, 388, 2027, 560] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Sim TX_DONE" SID "3392" Position [320, 363, 350, 377] IconDisplay "Port number" } Block { BlockType Constant Name "Constant1" SID "3370" Position [725, 375, 830, 395] ZOrder -4 ShowName off Value "tx_sim.num_pkts" } Block { BlockType Reference Name "Counter" SID "3367" Ports [1, 1] Position [530, 340, 590, 400] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "8" bin_pt "0" load_pin off rst off en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,60,1,1,white,blue,0,b089e9c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','C" "OMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "3433" Ports [1, 1] Position [545, 249, 580, 281] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "500" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,32,1,1,white,blue,0,5c475973,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 32 32 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-500}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "3434" Ports [1, 1] Position [745, 274, 780, 306] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "32" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,32,1,1,white,blue,0,05c6467a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 32 32 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 " "20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 2" "0.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-32}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Delay Name "Delay2" SID "3374" Ports [1, 1] Position [955, 363, 990, 397] InputPortMap "u0" DelayLength "400" ExternalReset "None" SampleTime "1" Port { PortNumber 1 Name "Stop" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Disregard Subsystem" SID "3432" Tag "discardX" Ports [] Position [124, 462, 182, 520] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0." "1 0.1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 3" "7.88 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.8" "8 37.88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.8" "8 ],[0.33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 1" "3.88 ],[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "3360" Ports [1, 1] Position [665, 364, 700, 376] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "3437" Ports [1, 1] Position [950, 274, 985, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3421" Ports [1, 1] Position [1190, 564, 1225, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TX_DONE" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "3422" Ports [1, 1] Position [1190, 579, 1225, 591] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt Count" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Logic Name "Logical Operator" SID "3377" Ports [2, 1] Position [1120, 227, 1150, 258] ZOrder -11 ShowName off Operator "OR" AllPortsSameDT off OutDataTypeStr "boolean" Port { PortNumber 1 Name "START" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Posedge3" SID "3361" Ports [1, 1] Position [430, 361, 475, 379] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge3" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "3362" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "3363" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "3364" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3365" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3366" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator1" SID "2414" Ports [0, 1] Position [1030, 199, 1060, 231] ZOrder -13 ShowName off Period "1e9" PulseWidth "100" PhaseDelay "150" } Block { BlockType Scope Name "Radio TxEn-RxEn" SID "3423" Ports [7] Position [1315, 568, 1350, 662] ZOrder -3 Floating off Location [6, 202, 1686, 1206] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "14000" YMin "-1~2~-1~-1~-1~-1~-1" YMax "1~2~1~1~1~1~1" SaveName "ScopeData14" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType RelationalOperator Name "Relational Operator" SID "3369" Ports [2, 1] Position [870, 362, 900, 393] ZOrder -14 ShowName off InputSameDT off OutDataTypeStr "boolean" } Block { BlockType SubSystem Name "S-R Latch1" SID "3424" Ports [2, 1] Position [820, 253, 865, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off Port { PortNumber 1 Name "Start" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "3425" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "3426" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "3427" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "3428" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "3429" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "3430" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "3431" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Stop Name "Stop Simulation" SID "3368" Position [1115, 362, 1150, 398] ZOrder -4 } Block { BlockType Outport Name "Sim TX_START" SID "3583" Position [1205, 238, 1235, 252] ZOrder -23 IconDisplay "Port number" } Line { SrcBlock "Posedge3" SrcPort 1 Points [15, 0] Branch { DstBlock "Counter" DstPort 1 } Branch { Points [0, -105] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, 215] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational Operator" DstPort 2 } Line { SrcBlock "Relational Operator" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Relational Operator" DstPort 1 } Line { SrcBlock "Sim TX_DONE" SrcPort 1 Points [55, 0] Branch { DstBlock "Posedge3" DstPort 1 } Branch { Points [0, 200] DstBlock "Gateway Out3" DstPort 1 } } Line { Name "Stop" SrcBlock "Delay2" SrcPort 1 Points [0, 0] Branch { DstBlock "Stop Simulation" DstPort 1 } Branch { Labels [2, 0] Points [0, 220] DstBlock "Radio TxEn-RxEn" DstPort 3 } } Line { Name "Start" Labels [0, 0] SrcBlock "S-R Latch1" SrcPort 1 Points [40, 0] Branch { Points [0, -50; -180, 0] DstBlock "Delay1" DstPort 1 } Branch { DstBlock "Gateway Out2" DstPort 1 } } Line { Name "TX_DONE" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Radio TxEn-RxEn" DstPort 1 } Line { Name "Pkt Count" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Radio TxEn-RxEn" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { Name "Start" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [15, 0; 0, -30] DstBlock "Logical Operator" DstPort 2 } Line { SrcBlock "Pulse\nGenerator1" SrcPort 1 Points [20, 0; 0, 20] DstBlock "Logical Operator" DstPort 1 } Line { Name "START" SrcBlock "Logical Operator" SrcPort 1 Points [15, 0] Branch { DstBlock "Sim TX_START" DstPort 1 } Branch { Labels [2, 0] Points [0, 370] DstBlock "Radio TxEn-RxEn" DstPort 4 } } Annotation { Name "Pulse starts first Tx, TX_DONE starts all subsequent Tx events" Position [1165, 181] } } } Line { SrcBlock "PHY_TX_START" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "PHY_TX_ANT_MASK" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "PHY_TX_PKT_BUF" SrcPort 1 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "PHY_TX_STARTED" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [10, 0] Branch { DstBlock "PHY_TX_DONE" DstPort 1 } Branch { Points [0, 75] DstBlock "Simulation Start-Stop" DstPort 1 } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "PHY_TX_PKT_BUF" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "PHY_TX_ANT_MASK" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 DstBlock "RC_USR_TXEN_A" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "RC_USR_TXEN_D" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "RC_USR_TXEN_C" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "RC_USR_TXEN_B" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "RC_USR_RXEN" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "RC_TX_GAIN_A" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "RC_TX_GAIN_B" DstPort 1 } Line { SrcBlock "From11" SrcPort 1 DstBlock "RC_TX_GAIN_C" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "RC_TX_GAIN_D" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "PHY_TX_PHY_MODE" DstPort 1 } Line { SrcBlock "PHY_TX_PHY_MODE" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [340, 0; 0, -60] DstBlock "RC_PHY_START" DstPort 1 } Line { SrcBlock "RC_PHY_START" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Simulation Start-Stop" SrcPort 1 Points [50, 0; 0, 95; -480, 0; 0, -530; 235, 0] Branch { DstBlock "PHY_TX_START" DstPort 1 } Branch { Points [0, 60] DstBlock "Delay" DstPort 1 } } Annotation { Name "MAC I/O" Position [433, 81] FontName "Arial" FontSize 18 } Annotation { Name "Radio Controller I/O" Position [1128, 81] FontName "Arial" FontSize 18 } Annotation { Name "Mimic hardware delay between MAC start and RC start" Position [625, 196] } } } Block { BlockType SubSystem Name "Registers" SID "1725" Ports [] Position [486, 355, 543, 414] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Registers" Location [397, 869, 920, 1011] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "112" Block { BlockType Reference Name "Constant" SID "1726" Ports [0, 1] Position [955, 64, 975, 86] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13.22 15.22" " 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22 11.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 14.4" "4 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register1" SID "1727" Ports [0, 1] Position [40, 500, 80, 530] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'FFT_Config'" init "REG_TX_FFT_Config" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register2" SID "1728" Ports [0, 1] Position [40, 720, 80, 750] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'TX_START'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register3" SID "1729" Ports [0, 1] Position [40, 820, 80, 850] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Output_Scaling'" init "REG_TX_Output_Scaling" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register4" SID "1730" Ports [0, 1] Position [40, 930, 80, 960] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'PKT_BUF_SEL'" init "REG_TX_PKT_BUF_SEL" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register5" SID "1731" Ports [0, 1] Position [40, 25, 80, 55] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Config'" init "REG_TX_Config" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register6" SID "1732" Ports [0, 1] Position [40, 1165, 80, 1195] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Timing'" init "REG_Tx_Timing" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "40,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 30 30 0 ]);\npatch([11.1 16.88 20.88 24.88 28.88 20.88 15.1 11.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([15.1 20.88 16.88 11.1 15.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([11.1 16.88 20.88 15.1 11.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([15." "1 28.88 24.88 20.88 16.88 11.1 15.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto1" SID "1733" Position [450, 505, 650, 525] ShowName off GotoTag "regTx_NUM_SC" TagVisibility "global" } Block { BlockType Goto Name "Goto10" SID "1734" Position [450, 935, 650, 955] ShowName off GotoTag "regTx_PKT_BUF_SEL" TagVisibility "global" } Block { BlockType Goto Name "Goto11" SID "3438" Position [435, 1210, 635, 1230] ShowName off GotoTag "regTx_PostTx_RF_En_Extension" TagVisibility "global" } Block { BlockType Goto Name "Goto12" SID "1736" Position [450, 1080, 650, 1100] ShowName off GotoTag "regTx_Pkt_Buf_Addr_Offset" TagVisibility "global" } Block { BlockType Goto Name "Goto15" SID "1739" Position [450, 60, 650, 80] ShowName off GotoTag "regTx_Reset_Scrambling_LFSR_PerPkt" TagVisibility "global" } Block { BlockType Goto Name "Goto16" SID "1740" Position [450, 95, 650, 115] ShowName off GotoTag "regTx_AntA_Tx_En" TagVisibility "global" } Block { BlockType Goto Name "Goto17" SID "1741" Position [450, 125, 650, 145] ShowName off GotoTag "regTx_AntB_Tx_En" TagVisibility "global" } Block { BlockType Goto Name "Goto18" SID "1742" Position [450, 165, 650, 185] ShowName off GotoTag "regTx_AntC_Tx_En" TagVisibility "global" } Block { BlockType Goto Name "Goto19" SID "1743" Position [450, 195, 650, 215] ShowName off GotoTag "regTx_AntD_Tx_En" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "1744" Position [450, 545, 650, 565] ShowName off GotoTag "regTx_CP_LEN" TagVisibility "global" } Block { BlockType Goto Name "Goto22" SID "1747" Position [450, 230, 650, 250] ShowName off GotoTag "regTx_Use_MAC_Ant_Masks" TagVisibility "global" } Block { BlockType Goto Name "Goto23" SID "1748" Position [450, 270, 650, 290] ShowName off GotoTag "regTx_TxRunning_Output_Sel" TagVisibility "global" } Block { BlockType Goto Name "Goto25" SID "2553" Position [450, 365, 650, 385] ShowName off GotoTag "regTx_SW_TX_PHY_MODE" TagVisibility "global" } Block { BlockType Goto Name "Goto26" SID "3439" Position [435, 1170, 635, 1190] ShowName off GotoTag "regTx_PostTx_Extension" TagVisibility "global" } Block { BlockType Goto Name "Goto27" SID "3440" Position [435, 1265, 635, 1285] ShowName off GotoTag "regTx_PostTx_RxSig_Valid" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "1750" Position [450, 725, 650, 745] ShowName off GotoTag "regTx_Start_Direct" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "1751" Position [450, 825, 650, 845] ShowName off GotoTag "regTx_Scaling_Preamble" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "1752" Position [450, 860, 650, 880] ShowName off GotoTag "regTx_Scaling_Payload" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "1753" Position [450, 615, 650, 635] ShowName off GotoTag "regTx_FFT_SCALING" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "1754" Position [450, 765, 650, 785] ShowName off GotoTag "regTx_Start_Indirect" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "1755" Position [450, 30, 650, 50] ShowName off GotoTag "regTx_RC_RXEN_ENABLE" TagVisibility "global" } Block { BlockType Goto Name "Goto9" SID "1756" Position [450, 460, 650, 480] ShowName off GotoTag "regTx_RESET" TagVisibility "global" } Block { BlockType Reference Name "LSB" SID "1757" Ports [1, 1] Position [140, 728, 180, 742] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "1758" Ports [1, 1] Position [315, 25, 350, 55] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register10" SID "1759" Ports [1, 1] Position [315, 610, 350, 640] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register11" SID "1760" Ports [1, 1] Position [315, 720, 350, 750] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register12" SID "1761" Ports [1, 1] Position [315, 760, 350, 790] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register13" SID "1762" Ports [1, 1] Position [315, 820, 350, 850] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register14" SID "1763" Ports [1, 1] Position [315, 855, 350, 885] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register15" SID "1764" Ports [1, 1] Position [315, 930, 350, 960] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register16" SID "1765" Ports [1, 1] Position [315, 1075, 350, 1105] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register17" SID "3441" Ports [1, 1] Position [315, 1165, 350, 1195] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register2" SID "1769" Ports [1, 1] Position [315, 55, 350, 85] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register20" SID "1770" Ports [1, 1] Position [880, 30, 915, 60] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register23" SID "1773" Ports [1, 1] Position [315, 225, 350, 255] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register24" SID "1774" Ports [1, 1] Position [315, 265, 350, 295] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register26" SID "2554" Ports [1, 1] Position [315, 360, 350, 390] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register27" SID "3442" Ports [1, 1] Position [315, 1205, 350, 1235] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register28" SID "3443" Ports [1, 1] Position [315, 1260, 350, 1290] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register3" SID "1776" Ports [1, 1] Position [315, 90, 350, 120] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register4" SID "1777" Ports [1, 1] Position [315, 120, 350, 150] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register5" SID "1778" Ports [1, 1] Position [315, 160, 350, 190] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register6" SID "1779" Ports [1, 1] Position [315, 190, 350, 220] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register7" SID "1780" Ports [1, 1] Position [315, 455, 350, 485] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register8" SID "1781" Ports [1, 1] Position [315, 500, 350, 530] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register9" SID "1782" Ports [1, 1] Position [315, 540, 350, 570] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Reinterpret" SID "1783" Ports [1, 1] Position [210, 824, 255, 846] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "12" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "45,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "1784" Ports [1, 1] Position [210, 859, 255, 881] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between si" "gned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
<" "br>Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned" " with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 " "in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "12" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "45,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Status Bits" SID "1785" Ports [0, 1] Position [780, 28, 830, 62] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Status Bits" Location [913, 332, 1334, 452] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Concat" SID "1786" Ports [2, 1] Position [275, 205, 335, 265] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "60,60,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{" "20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "1787" Ports [0, 1] Position [200, 210, 230, 230] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "31" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "1788" Position [45, 239, 200, 261] ZOrder -9 ShowName off GotoTag "regTx_TX_RUNNING" TagVisibility "global" } Block { BlockType Outport Name "32b" SID "1789" Position [410, 228, 440, 242] IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "32b" DstPort 1 } } } Block { BlockType Terminator Name "Terminator" SID "1790" Position [1095, 55, 1105, 65] ShowName off } Block { BlockType Reference Name "To Register" SID "1791" Ports [2, 1] Position [1020, 32, 1080, 88] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'STATUS'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "b[0]1" SID "1792" Ports [1, 1] Position [140, 33, 180, 47] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[14:12]" SID "2555" Ports [1, 1] Position [140, 368, 180, 382] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "3" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[15:0]" SID "1794" Ports [1, 1] Position [140, 828, 180, 842] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[15:8]" SID "1796" Ports [1, 1] Position [135, 548, 175, 562] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[19:10]" SID "3444" Ports [1, 1] Position [140, 1213, 180, 1227] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "10" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[1]" SID "1798" Ports [1, 1] Position [140, 63, 180, 77] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[1] " SID "1799" Ports [1, 1] Position [140, 768, 180, 782] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[23:16] " SID "1801" Ports [1, 1] Position [140, 1083, 180, 1097] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[29:20]" SID "3445" Ports [1, 1] Position [140, 1268, 180, 1282] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "20" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[29:24]" SID "1802" Ports [1, 1] Position [135, 618, 175, 632] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "6" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[2]" SID "1803" Ports [1, 1] Position [140, 98, 180, 112] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[31:16]" SID "1804" Ports [1, 1] Position [140, 863, 180, 877] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[31]" SID "1805" Ports [1, 1] Position [140, 463, 180, 477] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "31" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[3:0]" SID "1806" Ports [1, 1] Position [140, 938, 180, 952] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[3]" SID "1807" Ports [1, 1] Position [140, 128, 180, 142] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[4]" SID "1808" Ports [1, 1] Position [140, 168, 180, 182] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[5]" SID "1809" Ports [1, 1] Position [140, 198, 180, 212] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "5" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[6]" SID "1810" Ports [1, 1] Position [140, 233, 180, 247] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "6" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7:0]" SID "1811" Ports [1, 1] Position [135, 508, 175, 522] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "8" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[7]" SID "1813" Ports [1, 1] Position [140, 273, 180, 287] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "7" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b[9:0]" SID "3446" Ports [1, 1] Position [140, 1173, 180, 1187] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "10" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,398" block_type "slice" block_version "VER_STRING_GOES_HERE" sg_icon_stat "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24" ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "From Register5" SrcPort 1 Points [30, 0] Branch { DstBlock "b[0]1" DstPort 1 } Branch { Points [0, 30] Branch { DstBlock "b[1]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[2]" DstPort 1 } Branch { Points [0, 30] Branch { DstBlock "b[3]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[4]" DstPort 1 } Branch { Points [0, 30] Branch { DstBlock "b[5]" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "b[6]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[7]" DstPort 1 } Branch { Points [0, 95] Branch { Points [0, 95] DstBlock "b[31]" DstPort 1 } Branch { DstBlock "b[14:12]" DstPort 1 } } } } } } } } } } Line { SrcBlock "From Register1" SrcPort 1 Points [20, 0] Branch { DstBlock "b[7:0]" DstPort 1 } Branch { Points [0, 40] Branch { DstBlock "b[15:8]" DstPort 1 } Branch { Points [0, 70] DstBlock "b[29:24]" DstPort 1 } } } Line { SrcBlock "b[7:0]" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "b[15:8]" SrcPort 1 DstBlock "Register9" DstPort 1 } Line { SrcBlock "b[29:24]" SrcPort 1 DstBlock "Register10" DstPort 1 } Line { SrcBlock "From Register2" SrcPort 1 Points [25, 0] Branch { DstBlock "LSB" DstPort 1 } Branch { Points [0, 40] DstBlock "b[1] " DstPort 1 } } Line { SrcBlock "LSB" SrcPort 1 DstBlock "Register11" DstPort 1 } Line { SrcBlock "From Register3" SrcPort 1 Points [20, 0] Branch { DstBlock "b[15:0]" DstPort 1 } Branch { Points [0, 35] DstBlock "b[31:16]" DstPort 1 } } Line { SrcBlock "b[15:0]" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "b[31:16]" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Register13" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Register14" DstPort 1 } Line { SrcBlock "b[1] " SrcPort 1 DstBlock "Register12" DstPort 1 } Line { SrcBlock "b[0]1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "b[31]" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "To Register" DstPort 2 } Line { SrcBlock "Status Bits" SrcPort 1 DstBlock "Register20" DstPort 1 } Line { SrcBlock "To Register" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "From Register4" SrcPort 1 Points [35, 0] Branch { DstBlock "b[3:0]" DstPort 1 } Branch { Points [0, 145] DstBlock "b[23:16] " DstPort 1 } } Line { SrcBlock "b[3:0]" SrcPort 1 DstBlock "Register15" DstPort 1 } Line { SrcBlock "b[23:16] " SrcPort 1 DstBlock "Register16" DstPort 1 } Line { SrcBlock "From Register6" SrcPort 1 Points [25, 0] Branch { Points [0, 40] Branch { Points [0, 55] DstBlock "b[29:20]" DstPort 1 } Branch { DstBlock "b[19:10]" DstPort 1 } } Branch { DstBlock "b[9:0]" DstPort 1 } } Line { SrcBlock "b[1]" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "b[2]" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "b[3]" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "b[4]" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "b[5]" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Goto18" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Goto19" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Register9" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Register10" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Register11" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Register12" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "Register13" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Register14" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Register15" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Register16" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "Register20" SrcPort 1 DstBlock "To Register" DstPort 1 } Line { SrcBlock "b[6]" SrcPort 1 DstBlock "Register23" DstPort 1 } Line { SrcBlock "Register23" SrcPort 1 DstBlock "Goto22" DstPort 1 } Line { SrcBlock "b[7]" SrcPort 1 DstBlock "Register24" DstPort 1 } Line { SrcBlock "Register24" SrcPort 1 DstBlock "Goto23" DstPort 1 } Line { SrcBlock "b[14:12]" SrcPort 1 DstBlock "Register26" DstPort 1 } Line { SrcBlock "Register26" SrcPort 1 DstBlock "Goto25" DstPort 1 } Line { SrcBlock "b[9:0]" SrcPort 1 DstBlock "Register17" DstPort 1 } Line { SrcBlock "b[19:10]" SrcPort 1 DstBlock "Register27" DstPort 1 } Line { SrcBlock "b[29:20]" SrcPort 1 DstBlock "Register28" DstPort 1 } Line { SrcBlock "Register17" SrcPort 1 DstBlock "Goto26" DstPort 1 } Line { SrcBlock "Register27" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "Register28" SrcPort 1 DstBlock "Goto27" DstPort 1 } } } Block { BlockType SubSystem Name "Resets" SID "1815" Ports [] Position [571, 355, 628, 414] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Resets" Location [148, 798, 658, 882] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Constant" SID "1816" Ports [0, 1] Position [650, 168, 675, 192] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,24,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 18" ".33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 12.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npatch([" "8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1817" Ports [1, 1] Position [680, 199, 720, 221] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "40,22,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_lab" "el('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "1818" Ports [1, 1] Position [780, 319, 815, 351] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "16" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,32,1,1,white,blue,0,f89f7887,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 32 32 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 32 32 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-16}','texmode','on')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "1819" Position [230, 247, 460, 263] ZOrder -9 ShowName off GotoTag "LAST_SAMP_OUTPUT_TO_DACS" TagVisibility "global" } Block { BlockType From Name "From1" SID "1820" Position [445, 202, 670, 218] ZOrder -9 ShowName off GotoTag "regTx_RESET" TagVisibility "global" } Block { BlockType From Name "From2" SID "1821" Position [230, 267, 455, 283] ZOrder -9 ShowName off GotoTag "TX_SIG_DECODE_ERROR" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "1822" Ports [1, 1] Position [1120, 424, 1155, 436] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Last Samp Tx" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "1823" Ports [1, 1] Position [1120, 439, 1155, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Last Samp SR" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "1824" Ports [1, 1] Position [1120, 454, 1155, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "TX_RESET" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "2561" Ports [1, 1] Position [1120, 499, 1155, 511] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Goto Name "Goto1" SID "1825" Position [1130, 202, 1280, 218] ZOrder -10 ShowName off GotoTag "TX_RESET" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "1826" Position [1130, 122, 1280, 138] ZOrder -10 ShowName off GotoTag "TX_FORCE_RESET" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "1827" Position [825, 537, 975, 553] ZOrder -10 ShowName off GotoTag "TX_PHY_DONE" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "1828" Ports [3, 1] Position [900, 150, 950, 270] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "50,120,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 120 120 0 ],[0.77 0.82 0." "91 ]);\nplot([0 50 50 0 0 ],[0 0 120 120 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[67.77 67" ".77 74.77 67.77 74.77 74.77 74.77 67.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[60.77 60.77 67.77 6" "7.77 60.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[53.77 53.77 60.77 60.77 53.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[46.77 46.77 53.77 46.77 53.77 53.77 46.77 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('bl" "ack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1829" Ports [2, 1] Position [565, 244, 620, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "55,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 42 42 0 ]);\npatch([13.65 22.32 28.32 34.32 40.32 28.32 19.65 13.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([19.65 28.32 22.32 13.65 19.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([13.65 22.32 28.32 19.65 13.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\np" "atch([19.65 40.32 34.32 28.32 22.32 13.65 19.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or')" ";\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "1830" Ports [1, 1] Position [645, 256, 690, 274] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1831" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "1832" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "1833" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1834" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1835" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Scope Name "Resets" SID "1836" Ports [7] Position [1245, 413, 1280, 507] ZOrder -3 Floating off Location [406, 123, 2246, 1467] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "0~0~0~-0.1~0~-0.1~-0.1" YMax "1~1~1~1.1~25~1.1~1.1" SaveName "ScopeData18" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "S-R Latch" SID "1837" Ports [2, 1] Position [775, 238, 820, 287] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [13, 209, 2156, 1324] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1838" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1839" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1840" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1841" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1842" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1843" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1844" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "Sim Reset" SID "1845" Ports [0, 1] Position [580, 103, 625, 137] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sim Reset" Location [255, 165, 565, 247] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Disregard Subsystem" SID "1846" Tag "discardX" Ports [] Position [193, 127, 251, 185] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0." "1 0.1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 3" "7.88 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.8" "8 37.88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.8" "8 ],[0.33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 1" "3.88 ],[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Sim Reset" SID "1847" Ports [1, 1] Position [165, 30, 230, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Step Name "Step" SID "1848" Position [25, 25, 55, 55] ZOrder -22 Time "10" Before "1" After "0" SampleTime "1" } Block { BlockType Outport Name "Out1" SID "1849" Position [255, 33, 285, 47] IconDisplay "Port number" } Line { SrcBlock "Step" SrcPort 1 DstBlock "Sim Reset" DstPort 1 } Line { SrcBlock "Sim Reset" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Block { BlockType Reference Name "Simulation Multiplexer" SID "1850" Ports [2, 1] Position [775, 151, 815, 189] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "simmux" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Line { SrcBlock "S-R Latch" SrcPort 1 Points [30, 0] Branch { Points [0, 70] DstBlock "Delay" DstPort 1 } Branch { Points [0, -15; 20, 0] Branch { Points [0, 195] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "Logical" DstPort 3 } } } Line { SrcBlock "Logical" SrcPort 1 Points [25, 0] Branch { DstBlock "Goto1" DstPort 1 } Branch { Points [0, 250] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [-25, 0; 0, -60] DstBlock "S-R Latch" DstPort 2 } Line { Name "Last Samp Tx" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Resets" DstPort 2 } Line { Name "Last Samp SR" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Resets" DstPort 3 } Line { Name "TX_RESET" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Resets" DstPort 4 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 Points [145, 0] Branch { Points [0, -80] DstBlock "Goto2" DstPort 1 } Branch { DstBlock "Logical" DstPort 2 } } Line { SrcBlock "From" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [75, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 230] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Posedge1" SrcPort 1 Points [20, 0] Branch { Points [0, 165] Branch { DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, 115] DstBlock "Goto3" DstPort 1 } } Branch { Points [0, -15] DstBlock "S-R Latch" DstPort 1 } } Line { SrcBlock "Simulation Multiplexer" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Simulation Multiplexer" DstPort 2 } Line { SrcBlock "Sim Reset" SrcPort 1 Points [100, 0; 0, 40] DstBlock "Simulation Multiplexer" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Resets" DstPort 7 } } } Block { BlockType SubSystem Name "Sampling Clock" SID "2491" Ports [] Position [875, 354, 933, 414] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sampling Clock" Location [457, 1164, 1222, 1300] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Convert2" SID "1921" Ports [1, 1] Position [495, 41, 520, 59] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "1978" Position [590, 40, 710, 60] ZOrder -10 ShowName off GotoTag "TX_IQ_SAMP_CE" TagVisibility "global" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator2" SID "2035" Ports [0, 1] Position [215, 34, 245, 66] ZOrder -13 ShowName off Period "160 / tx_sim.samp_rate" } Block { BlockType Reference Name "SAMP_CE" SID "1929" Ports [1, 1] Position [330, 40, 395, 60] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" } Line { SrcBlock "Pulse\nGenerator2" SrcPort 1 DstBlock "SAMP_CE" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "SAMP_CE" SrcPort 1 DstBlock "Convert2" DstPort 1 } Annotation { Name "Core runs at 160MHz via sysgen_clk port. All synchronous elements in the core\nare clocked by the 160MHz " "sysgen_clk signal. The SAMP_CE input acts as a\nclock enable throughout the sections of the PHY that process indivi" "dual samples.\n\nThe SAMP_CE frequency may change at run time. MAC code should avoid changing\nSAMP_CE frequency du" "ring a transmission.\n\nThe SAMP_CE signal must:\n* Be valid in the sysgen_clk domain\n* Assert for exactly 1 cycle" " per period\n* Have duty cycle of:\n (1/32): 5MSps I/Q\n (1/16): 10MSps I/Q\n (1/8): 20MSps I/Q\n (1/4): 40" "MSps I/Q\n\nOther duty cycles are not tested, and are not supported on WARP v3 hardware." Position [211, 204] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Start Ctrl" SID "1852" Ports [0, 1] Position [65, 176, 160, 214] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Start Ctrl" Location [2, 70, 1817, 1180] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType SubSystem Name "Add MAC Extension" SID "1853" Ports [2, 1] Position [1005, 316, 1095, 369] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Add MAC Extension" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Tx Start" SID "1856" Position [315, 448, 345, 462] IconDisplay "Port number" } Block { BlockType Inport Name "IQ Done" SID "1854" Position [290, 278, 320, 292] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Counter1" SID "1857" Ports [2, 1] Position [615, 226, 675, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,78,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 78 78 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[47.8" "8 47.88 55.88 47.88 55.88 55.88 55.88 47.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[39.88 39.88 47.8" "8 47.88 39.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[31.88 31.88 39.88 39.88 31.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[23.88 23.88 31.88 23.88 31.88 31.88 23.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsiz" "e{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "1858" Position [525, 365, 720, 385] BackgroundColor "green" ShowName off CloseFcn "tagdialog Close" GotoTag "regTx_PostTx_Extension" TagVisibility "global" } Block { BlockType From Name "From5" SID "1965" Position [95, 242, 270, 258] ZOrder -9 ShowName off GotoTag "TX_FORCE_RESET" TagVisibility "global" } Block { BlockType From Name "From6" SID "1859" Position [190, 357, 325, 373] ZOrder -9 ShowName off GotoTag "TX_IQ_SAMP_CE" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "1860" Ports [2, 1] Position [515, 284, 545, 331] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,47,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 47 47 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[27.44 " "27.44 31.44 27.44 31.44 31.44 31.44 27.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[23.44 23.44 27.44 2" "7.44 23.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 23.44 19.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 15.44 19.44 19.44 15.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('blac" "k');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1861" Ports [2, 1] Position [355, 227, 390, 258] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "1862" Ports [2, 1] Position [805, 250, 840, 310] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,60,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 60 60 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[35.55" " 35.55 40.55 35.55 40.55 40.55 40.55 35.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[30.55 30.55 35" ".55 35.55 30.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[25.55 25.55 30.55 30.55 25.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 20.55 25.55 25.55 20.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "1863" Ports [2, 1] Position [430, 278, 465, 307] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1864" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1865" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1866" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1867" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1868" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1869" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "1870" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "1871" Ports [2, 1] Position [430, 448, 465, 477] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1872" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1873" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1874" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1875" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1876" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1877" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "1878" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Outport Name "Tx Active" SID "1879" Position [860, 458, 890, 472] IconDisplay "Port number" } Line { SrcBlock "Relational3" SrcPort 1 Points [25, 0; 0, -80; -530, 0] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [60, 0; 0, -80] DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [10, 0] Branch { DstBlock "Counter1" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "S-R Latch1" DstPort 2 } Branch { Points [0, 170] DstBlock "S-R Latch2" DstPort 2 } } } Line { SrcBlock "Logical1" SrcPort 1 Points [30, 0; 0, -25] DstBlock "Counter1" DstPort 2 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "IQ Done" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 Points [170, 0] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Tx Start" SrcPort 1 DstBlock "S-R Latch2" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 DstBlock "Tx Active" DstPort 1 } Annotation { Name "The 802.11 spec defines a 6 usec \"extension\" period that occurs\nafter the last sample is transm" "itted. The PHY does not transmit\nanything during this extension. The extension is implemented by\ndelaying the" " \"TX_DONE\" output to the MAC." Position [415, 548] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Add TXEN Extension" SID "1880" Ports [1, 2] Position [335, 520, 460, 575] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Add TXEN Extension" Location [260, 204, 2045, 1422] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ Done" SID "1881" Position [235, 488, 265, 502] IconDisplay "Port number" } Block { BlockType Reference Name "Counter1" SID "1883" Ports [2, 1] Position [665, 436, 725, 514] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,78,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 78 78 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[47.8" "8 47.88 55.88 47.88 55.88 55.88 55.88 47.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[39.88 39.88 47.8" "8 47.88 39.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[31.88 31.88 39.88 39.88 31.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[23.88 23.88 31.88 23.88 31.88 31.88 23.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsiz" "e{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "3399" Ports [1] Position [940, 570, 1030, 600] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "3401" Ports [1] Position [905, 270, 995, 300] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From1" SID "1884" Position [575, 385, 770, 405] BackgroundColor "green" ShowName off CloseFcn "tagdialog Close" GotoTag "regTx_PostTx_RxSig_Valid" TagVisibility "global" } Block { BlockType From Name "From2" SID "1885" Position [575, 575, 770, 595] BackgroundColor "green" ShowName off CloseFcn "tagdialog Close" GotoTag "regTx_PostTx_RF_En_Extension" TagVisibility "global" } Block { BlockType From Name "From3" SID "1966" Position [90, 452, 265, 468] ZOrder -9 ShowName off GotoTag "TX_FORCE_RESET" TagVisibility "global" } Block { BlockType From Name "From6" SID "1886" Position [240, 567, 375, 583] ZOrder -9 ShowName off GotoTag "TX_IQ_SAMP_CE" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "3397" Ports [1, 1] Position [1330, 749, 1365, 761] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "3394" Ports [1, 1] Position [1330, 719, 1365, 731] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3395" Ports [1, 1] Position [1330, 734, 1365, 746] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Done Latch" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "3398" Ports [1, 1] Position [1330, 764, 1365, 776] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Disable RF Tx" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "3400" Ports [1, 1] Position [865, 579, 900, 591] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out6" SID "3402" Ports [1, 1] Position [830, 279, 865, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1887" Ports [2, 1] Position [565, 494, 595, 541] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,47,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 47 47 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 47 47 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[27.44 " "27.44 31.44 27.44 31.44 31.44 31.44 27.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[23.44 23.44 27.44 2" "7.44 23.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 23.44 19.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 15.44 19.44 19.44 15.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('blac" "k');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1888" Ports [2, 1] Position [405, 437, 440, 468] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1889" Ports [2, 1] Position [965, 467, 1000, 498] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge1" SID "1890" Ports [1, 1] Position [335, 488, 380, 502] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1891" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "1892" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "1893" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1894" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1895" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } } } Block { BlockType SubSystem Name "Posedge2" SID "1896" Ports [1, 1] Position [1145, 478, 1190, 492] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge2" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1897" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "1898" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "1899" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1900" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1901" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge3" SID "1902" Ports [1, 1] Position [1145, 373, 1190, 387] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge3" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1903" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "1904" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "1905" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1906" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1907" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } } } Block { BlockType Reference Name "Relational1" SID "1908" Ports [2, 1] Position [855, 350, 890, 410] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,60,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 60 60 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[35.55" " 35.55 40.55 35.55 40.55 40.55 40.55 35.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[30.55 30.55 35" ".55 35.55 30.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[25.55 25.55 30.55 30.55 25.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 20.55 25.55 25.55 20.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "1909" Ports [2, 1] Position [855, 460, 890, 520] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,60,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 60 60 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[35.55" " 35.55 40.55 35.55 40.55 40.55 40.55 35.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[30.55 30.55 35" ".55 35.55 30.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[25.55 25.55 30.55 30.55 25.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[20.55 20.55 25.55 20.55 25.55 25.55 20.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "1910" Ports [2, 1] Position [480, 488, 515, 517] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1911" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1912" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1913" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1914" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1915" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1916" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "1917" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Scope Name "TxEn Extension" SID "3396" Ports [7] Position [1485, 723, 1520, 817] ZOrder -3 Floating off Location [6, 202, 1686, 1206] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "14000" YMin "0~0~-1~-1~-1~-1~-1" YMax "1~1~1~1~1~1~1" SaveName "ScopeData10" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "RxSig Valid" SID "1918" Position [1270, 373, 1300, 387] IconDisplay "Port number" } Block { BlockType Outport Name "Disable RF Tx" SID "1919" Position [1275, 478, 1305, 492] Port "2" IconDisplay "Port number" } Line { SrcBlock "From6" SrcPort 1 Points [170, 0] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [15, 0] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 235] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "IQ Done" SrcPort 1 Points [30, 0] Branch { DstBlock "Posedge1" DstPort 1 } Branch { Points [0, 230] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [35, 0; 0, -25] DstBlock "Counter1" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "S-R Latch1" DstPort 2 } Branch { DstBlock "Counter1" DstPort 1 } } Line { SrcBlock "Counter1" SrcPort 1 Points [65, 0] Branch { Points [0, 0] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, -110] DstBlock "Relational1" DstPort 1 } } Branch { Points [0, 280] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "From2" SrcPort 1 Points [60, 0] Branch { Points [0, -80] DstBlock "Relational3" DstPort 2 } Branch { DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 Points [15, 0] Branch { DstBlock "Relational1" DstPort 2 } Branch { Points [0, -110] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Posedge2" SrcPort 1 Points [20, 0] Branch { DstBlock "Disable RF Tx" DstPort 1 } Branch { Points [0, 285] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Relational1" SrcPort 1 Points [45, 0] Branch { Points [0, -45; -550, 0] DstBlock "Logical2" DstPort 1 } Branch { DstBlock "Posedge3" DstPort 1 } Branch { Points [0, 95] DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "Posedge3" SrcPort 1 DstBlock "RxSig Valid" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Posedge2" DstPort 1 } Line { Name "IQ Done" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "TxEn Extension" DstPort 1 } Line { Name "IQ Done Latch" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "TxEn Extension" DstPort 2 } Line { Name "Counter" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "TxEn Extension" DstPort 3 } Line { Name "Disable RF Tx" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "TxEn Extension" DstPort 4 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Display1" DstPort 1 } Annotation { Name "Handle case of bad timing values (RxSig must\nbe later than RF Tx Dis; this OR handles case\nof co" "de getting this backwards)" Position [1021, 536] } Annotation { Name "This block delays de-assertion of the radio's TXEN signal\nfor a software-programmed duration afte" "r the last sample\nhas been output to the DACs. This delay accounts for\nthe non-zero latency from the DAC inpu" "t to the radio's\nRF output. Without this delay the radio and amplifier\nwill be disabled too early, clipping t" "he last few usec\nof the transmitted waveform.\n\nThe RxSig Valid output is used by the Rx PHY to unmask its\nI" "Q inputs. This control path avoids any unintentional Rx\nevents during a Tx (i.e. due to RF coupling or transie" "nts\nat the start of a Tx)." Position [233, 241] HorizontalAlignment "left" } } } Block { BlockType Display Name "Display" SID "2556" Ports [1] Position [1190, 1055, 1280, 1075] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From" SID "1960" Position [130, 627, 305, 643] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_Start_Indirect" TagVisibility "global" } Block { BlockType From Name "From1" SID "1961" Position [565, 132, 720, 148] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_Start_Direct" TagVisibility "global" } Block { BlockType From Name "From10" SID "2417" Position [565, 152, 720, 168] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_PHY_START" TagVisibility "global" } Block { BlockType From Name "From11" SID "2437" Position [130, 347, 305, 363] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_X" } Block { BlockType From Name "From12" SID "2438" Position [130, 307, 305, 323] ZOrder -9 BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_X" } Block { BlockType From Name "From13" SID "2439" Position [130, 367, 305, 383] ZOrder -9 ShowName off GotoTag "X" } Block { BlockType From Name "From14" SID "2472" Position [650, 1297, 825, 1313] ZOrder -9 BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_ANT_MASK" TagVisibility "global" } Block { BlockType From Name "From15" SID "2494" Position [535, 782, 690, 798] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_Start_Direct" TagVisibility "global" } Block { BlockType From Name "From16" SID "2495" Position [535, 767, 710, 783] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_Start_Indirect" TagVisibility "global" } Block { BlockType From Name "From17" SID "2496" Position [535, 807, 710, 823] ZOrder -9 BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_START" TagVisibility "global" } Block { BlockType From Name "From18" SID "2497" Position [650, 1322, 825, 1338] ZOrder -9 BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_START" TagVisibility "global" } Block { BlockType From Name "From2" SID "1962" Position [130, 707, 305, 723] ZOrder -9 ShowName off GotoTag "TX_FORCE_RESET" TagVisibility "global" } Block { BlockType From Name "From3" SID "1963" Position [130, 487, 305, 503] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_RC_RXEN_ENABLE" TagVisibility "global" } Block { BlockType From Name "From4" SID "1964" Position [700, 347, 875, 363] ZOrder -9 ShowName off GotoTag "TX_PHY_DONE" TagVisibility "global" } Block { BlockType From Name "From6" SID "3383" Position [685, 182, 820, 198] ZOrder -9 ShowName off GotoTag "TX_IQ_SAMP_CE" TagVisibility "global" } Block { BlockType From Name "From7" SID "1967" Position [130, 542, 305, 558] ZOrder -9 ShowName off GotoTag "TX_PHY_DONE" TagVisibility "global" } Block { BlockType From Name "From8" SID "2436" Position [130, 327, 305, 343] ZOrder -9 BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_X" } Block { BlockType From Name "From9" SID "2416" Position [130, 647, 305, 663] ZOrder -9 BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_START" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out5" SID "2557" Ports [1, 1] Position [1070, 1059, 1100, 1071] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Goto Name "Goto1" SID "1979" Position [1080, 652, 1230, 668] ZOrder -10 BackgroundColor "green" ShowName off GotoTag "regTx_TX_RUNNING" TagVisibility "global" } Block { BlockType Goto Name "Goto10" SID "2421" Position [1300, 292, 1455, 308] BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_STARTED" TagVisibility "global" } Block { BlockType Goto Name "Goto11" SID "1720" Position [1135, 1130, 1335, 1150] ShowName off GotoTag "Tx_PHY_Mode_11n" TagVisibility "global" } Block { BlockType Goto Name "Goto12" SID "1721" Position [1135, 1165, 1335, 1185] ShowName off GotoTag "Tx_PHY_Mode_11ac" TagVisibility "global" } Block { BlockType Goto Name "Goto13" SID "1722" Position [1240, 1230, 1440, 1250] ShowName off GotoTag "Tx_PHY_Mode_11n_ac" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "1980" Position [1080, 792, 1230, 808] ShowName off GotoTag "Tx_PKT_BUF_SEL" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "2394" Position [1075, 887, 1230, 903] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TX_GAIN_A" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "2395" Position [1075, 927, 1230, 943] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TX_GAIN_B" TagVisibility "global" } Block { BlockType Goto Name "Goto5" SID "2396" Position [1075, 967, 1230, 983] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TX_GAIN_C" TagVisibility "global" } Block { BlockType Goto Name "Goto6" SID "2397" Position [1075, 1007, 1230, 1023] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TX_GAIN_D" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "1719" Position [1135, 1095, 1335, 1115] ShowName off GotoTag "Tx_PHY_Mode_11ag" TagVisibility "global" } Block { BlockType Goto Name "Goto8" SID "2422" Position [1300, 337, 1455, 353] BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_DONE" TagVisibility "global" } Block { BlockType Goto Name "Goto9" SID "2079" Position [1095, 1312, 1245, 1328] ShowName off GotoTag "MAC_Tx_Ant_Mask" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "1983" Ports [2, 1] Position [780, 129, 820, 171] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "1984" Ports [2, 1] Position [595, 624, 635, 666] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1723" Ports [2, 1] Position [1165, 1222, 1200, 1253] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 31 31 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "1987" Ports [2, 1] Position [670, 529, 710, 571] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "1988" Ports [2, 1] Position [820, 765, 850, 800] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,35,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 35 35 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.44 " "21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "1989" Ports [2, 1] Position [800, 654, 840, 681] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1" " 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black'" ");disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "1990" Ports [2, 1] Position [800, 559, 840, 586] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1" " 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black'" ");disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "1991" Ports [2, 1] Position [800, 459, 840, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 27 27 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1" " 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black'" ");disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "PHY Mode Sel" SID "2539" Ports [2, 1] Position [915, 1075, 995, 1135] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "PHY Mode Sel" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "Sw Tx" SID "2540" Position [625, 638, 655, 652] IconDisplay "Port number" } Block { BlockType Inport Name "Hw Tx" SID "2541" Position [625, 698, 655, 712] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Convert" SID "2542" Ports [1, 1] Position [695, 636, 720, 654] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2543" Ports [1, 1] Position [695, 696, 720, 714] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "2552" Position [675, 612, 850, 628] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_SW_TX_PHY_MODE" TagVisibility "global" } Block { BlockType From Name "From5" SID "2533" Position [675, 672, 850, 688] ZOrder -9 BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_PHY_MODE" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "2546" Ports [2, 1] Position [935, 544, 975, 586] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "2547" Ports [3, 1] Position [1090, 546, 1110, 724] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,178,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 25.4286 152.571 178" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 25.4286 152.571 178 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 " "10.44 7.55 5.55 ],[91.22 91.22 93.22 91.22 93.22 93.22 93.22 91.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7." "55 ],[89.22 89.22 91.22 91.22 89.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[87.22 87.22 8" "9.22 89.22 87.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[85.22 85.22 87.22 85.22 87.22 87" ".22 85.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType Reference Name "Register1" SID "2548" Ports [2, 1] Position [935, 607, 970, 658] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2549" Ports [2, 1] Position [935, 667, 970, 718] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "2550" Ports [2, 1] Position [1025, 527, 1060, 578] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "PHY Mode" SID "2551" Position [1190, 628, 1220, 642] IconDisplay "Port number" } Line { SrcBlock "Convert1" SrcPort 1 Points [180, 0] Branch { Points [0, -130] Branch { Points [0, -35] DstBlock "Register3" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Branch { DstBlock "Register2" DstPort 2 } } Line { SrcBlock "Convert" SrcPort 1 Points [175, 0] Branch { Points [0, -90] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Register3" DstPort 2 } Line { SrcBlock "Hw Tx" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Sw Tx" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "PHY Mode" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Register2" DstPort 1 } Annotation { Name "Select between software-configured and MAC-hardware-configured\nPHY mode (11a/11n). The mode is ca" "ptured only at the start\nof each Tx. The register/input are ignored at all other times." Position [808, 786] } } } Block { BlockType SubSystem Name "Pkt Buf Sel" SID "1997" Ports [2, 1] Position [915, 770, 995, 830] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Pkt Buf Sel" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Sw Tx" SID "1998" Position [130, 303, 160, 317] IconDisplay "Port number" } Block { BlockType Inport Name "Hw Tx" SID "1999" Position [130, 363, 160, 377] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Convert" SID "2000" Ports [1, 1] Position [200, 301, 225, 319] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2001" Ports [1, 1] Position [200, 361, 225, 379] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "2435" Position [180, 337, 360, 353] ZOrder -9 BackgroundColor "yellow" ShowName off GotoTag "MAC_IO_PHY_TX_PKT_BUF" TagVisibility "global" } Block { BlockType From Name "From6" SID "2002" Position [180, 277, 355, 293] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_PKT_BUF_SEL" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "2003" Ports [2, 1] Position [440, 209, 480, 251] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "2004" Ports [3, 1] Position [595, 211, 615, 389] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,178,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 25.4286 152.571 178" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 25.4286 152.571 178 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 " "10.44 7.55 5.55 ],[91.22 91.22 93.22 91.22 93.22 93.22 93.22 91.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7." "55 ],[89.22 89.22 91.22 91.22 89.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[87.22 87.22 8" "9.22 89.22 87.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[85.22 85.22 87.22 85.22 87.22 87" ".22 85.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black'" ");port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon t" "ext');" } Block { BlockType Reference Name "Register1" SID "2006" Ports [2, 1] Position [440, 272, 475, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2007" Ports [2, 1] Position [440, 332, 475, 383] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "2008" Ports [2, 1] Position [530, 192, 565, 243] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Pkt Buf" SID "2009" Position [695, 293, 725, 307] IconDisplay "Port number" } Line { SrcBlock "From1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Register3" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Pkt Buf" DstPort 1 } Line { SrcBlock "Sw Tx" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Hw Tx" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Register3" DstPort 2 } Line { SrcBlock "Convert" SrcPort 1 Points [175, 0] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, -90] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [180, 0] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, -130] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -35] DstBlock "Register3" DstPort 1 } } } Annotation { Name "Select between software-configured and MAC-hardware-configured\npacket buffer index. The index is " "captured only at the start\nof each Tx. The register/input are ignored at all other times." Position [313, 451] } } } Block { BlockType SubSystem Name "Posedge1" SID "3415" Ports [1, 1] Position [665, 638, 710, 652] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "3416" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "3417" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "3418" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3419" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3420" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge2" SID "2022" Ports [1, 1] Position [1205, 293, 1250, 307] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge2" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "2023" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "2024" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "2025" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2026" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2027" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } } } Block { BlockType SubSystem Name "Posedge4" SID "2498" Ports [1, 1] Position [590, 533, 635, 547] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge4" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "2499" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "2500" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "2501" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2502" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2503" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge5" SID "3409" Ports [1, 1] Position [590, 553, 635, 567] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge5" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "3410" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "3411" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "3412" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "3413" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "3414" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } } } Block { BlockType Reference Name "RX_SIGS_INVALID" SID "2043" Ports [1, 1] Position [1250, 455, 1310, 475] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType SubSystem Name "Radio TXEN/RXEN Control" SID "2440" Ports [2] Position [1150, 554, 1220, 601] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio TXEN/RXEN Control" Location [1173, 413, 2146, 641] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Rx" SID "2442" Position [220, 258, 250, 272] IconDisplay "Port number" } Block { BlockType Inport Name "Tx" SID "2443" Position [220, 353, 250, 367] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Convert1" SID "2449" Ports [1, 1] Position [660, 426, 685, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert7" SID "1926" Ports [1, 1] Position [710, 256, 735, 274] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert8" SID "1927" Ports [1, 1] Position [710, 341, 735, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "1930" Ports [1, 1] Position [340, 326, 370, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "32" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,05c6467a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-32}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "1931" Ports [1, 1] Position [340, 266, 370, 294] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "32" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,28,1,1,white,blue,0,05c6467a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-32}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From14" SID "2446" Position [335, 477, 510, 493] ZOrder -9 ShowName off GotoTag "MAC_Tx_Ant_Mask" TagVisibility "global" } Block { BlockType From Name "From3" SID "2445" Position [25, 242, 200, 258] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_RC_RXEN_ENABLE" TagVisibility "global" } Block { BlockType From Name "From6" SID "2450" Position [335, 426, 525, 444] ZOrder -9 BackgroundColor "green" ShowName off GotoTag "regTx_Use_MAC_Ant_Masks" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out2" SID "3388" Ports [1, 1] Position [1270, 329, 1305, 341] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RC_RXEN" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "3389" Ports [1, 1] Position [1270, 344, 1305, 356] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RC_TXEN_A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto1" SID "2451" Position [1140, 517, 1295, 533] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TXEN_B" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "2452" Position [1140, 572, 1295, 588] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TXEN_C" TagVisibility "global" } Block { BlockType Goto Name "Goto3" SID "2453" Position [1140, 627, 1295, 643] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TXEN_D" TagVisibility "global" } Block { BlockType Goto Name "Goto4" SID "2454" Position [1140, 457, 1295, 473] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_TXEN_A" TagVisibility "global" } Block { BlockType Goto Name "Goto7" SID "2403" Position [1140, 257, 1295, 273] BackgroundColor "lightBlue" ShowName off GotoTag "RC_IO_RXEN" TagVisibility "global" } Block { BlockType Reference Name "Inverter" SID "2455" Ports [1, 1] Position [570, 422, 595, 448] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "25,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16" ".33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncol" "or('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter2" SID "1981" Ports [1, 1] Position [405, 333, 435, 347] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');d" "isp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter3" SID "1982" Ports [1, 1] Position [405, 273, 435, 287] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "30,14,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');d" "isp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2456" Ports [2, 1] Position [760, 516, 805, 554] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical10" SID "2463" Ports [2, 1] Position [925, 444, 965, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "1985" Ports [3, 1] Position [495, 244, 535, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "1986" Ports [2, 1] Position [495, 329, 535, 371] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "2457" Ports [2, 1] Position [760, 456, 805, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "2458" Ports [2, 1] Position [760, 571, 805, 609] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "2459" Ports [2, 1] Position [760, 626, 805, 664] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "45,38,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24." "55 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55" " 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 1" "4.55 ],[1 1 1 ]);\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "2460" Ports [2, 1] Position [925, 504, 965, 546] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical8" SID "2461" Ports [2, 1] Position [925, 559, 965, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical9" SID "2462" Ports [2, 1] Position [925, 614, 965, 656] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Radio TxEn-RxEn" SID "3390" Ports [7] Position [1425, 333, 1460, 427] ZOrder -3 Floating off Location [6, 202, 1686, 1206] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "14000" YMin "0~0~-1~-1~-1~-1~-1" YMax "1~1~1~1~1~1~1" SaveName "ScopeData6" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Register1" SID "2464" Ports [1, 1] Position [1040, 512, 1070, 538] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2465" Ports [1, 1] Position [1040, 567, 1070, 593] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "2466" Ports [1, 1] Position [1040, 622, 1070, 648] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "2048" Ports [1, 1] Position [1040, 252, 1070, 278] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RC_RXEN" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Register5" SID "2467" Ports [1, 1] Position [1040, 452, 1070, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b0" SID "2468" Ports [1, 1] Position [650, 477, 695, 493] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b1" SID "2469" Ports [1, 1] Position [650, 537, 695, 553] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b2" SID "2470" Ports [1, 1] Position [650, 592, 695, 608] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "b3" SID "2471" Ports [1, 1] Position [650, 647, 695, 663] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.
Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "45,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 16 16 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "Logical2" SrcPort 1 Points [30, 0] Branch { Points [0, 40; -245, 0] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Convert7" DstPort 1 } } Line { SrcBlock "Inverter2" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter2" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Inverter3" DstPort 1 } Line { SrcBlock "Inverter3" SrcPort 1 DstBlock "Logical2" DstPort 3 } Line { SrcBlock "Logical3" SrcPort 1 Points [30, 0] Branch { Points [0, -40; -250, 0; 0, -30] DstBlock "Delay1" DstPort 1 } Branch { DstBlock "Convert8" DstPort 1 } } Line { SrcBlock "Convert7" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { Name "RC_RXEN" Labels [0, 0] SrcBlock "Register4" SrcPort 1 Points [40, 0] Branch { DstBlock "Goto7" DstPort 1 } Branch { Points [0, 70] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Convert8" SrcPort 1 Points [130, 0; 0, 105] Branch { DstBlock "Logical10" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "Logical7" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "Logical8" DstPort 1 } Branch { Points [0, 55] DstBlock "Logical9" DstPort 1 } } } } Line { SrcBlock "From3" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Rx" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Tx" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 Points [25, 0] Branch { DstBlock "Goto4" DstPort 1 } Branch { Points [0, -115] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "From14" SrcPort 1 Points [105, 0] Branch { DstBlock "b0" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "b1" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "b2" DstPort 1 } Branch { Points [0, 55] DstBlock "b3" DstPort 1 } } } } Line { SrcBlock "b0" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "b1" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "b2" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "b3" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "Logical10" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical7" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Logical8" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Logical9" DstPort 2 } Line { SrcBlock "Logical10" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Logical8" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Logical9" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0; 0, 30] Branch { DstBlock "Logical4" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "Logical1" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "Logical5" DstPort 1 } Branch { Points [0, 55] DstBlock "Logical6" DstPort 1 } } } } Line { Name "RC_RXEN" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Radio TxEn-RxEn" DstPort 1 } Line { Name "RC_TXEN_A" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Radio TxEn-RxEn" DstPort 2 } Annotation { Name "This logic handles the the transition betwen TX and RX modes in the \nradio circuits. The delayed " "cross-connect between Tx and Rx ensures\nthe radio transitions through standby (TXEN=RXEN=0).\n\nThe PHY genera" "tes a single RXEN signal. The software should configure\nthe radio_controller to use this RXEN signal for which" "ever RF interfaces\nare required. The PHY generates 4 TXEN signals (one per interface),\nallowing the Tx interf" "ace to be selected per packet by the MAC." Position [334, 174] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Register1" SID "2473" Ports [1, 1] Position [990, 1307, 1020, 1333] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2046" Ports [1, 1] Position [1130, 452, 1160, 478] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "3384" Ports [2, 1] Position [925, 139, 960, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,42,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');dis" "p('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "2474" Ports [2, 1] Position [900, 1292, 935, 1343] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55 30.55 35.55" " 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30.55 30.55 25.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');dis" "p('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "2050" Ports [2, 1] Position [905, 633, 950, 682] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "2051" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "2052" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "2053" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2054" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "2055" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2056" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2057" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "S-R Latch1" SID "2058" Ports [2, 1] Position [905, 538, 950, 587] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "2059" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "2060" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "2061" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2062" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "2063" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2064" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2065" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "2066" Ports [2, 1] Position [905, 438, 950, 487] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "2067" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "2068" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "2069" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 " "9.22 ],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch(" "[4.55 11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''" ",'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2070" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "2071" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2072" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30." "66 30.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 3" "0.66 30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2073" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "Slice" SID "2534" Ports [1, 1] Position [1070, 1099, 1100, 1111] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "2535" Ports [1, 1] Position [1070, 1134, 1100, 1146] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice2" SID "2536" Ports [1, 1] Position [1070, 1169, 1100, 1181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'" "[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Tx Active Debug Signal" SID "2428" Ports [1] Position [1205, 218, 1290, 252] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Tx Active Debug Signal" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Tx Active" SID "2429" Position [520, 673, 550, 687] IconDisplay "Port number" } Block { BlockType Reference Name "Convert9" SID "1928" Ports [1, 1] Position [760, 672, 790, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Dly" SID "1932" Ports [1, 1] Position [755, 695, 800, 725] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Dly" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "1933" Position [100, 273, 130, 287] IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "1934" Ports [0, 1] Position [510, 297, 565, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "745" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "16" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "107,239,336,437" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,68c8c276,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'745');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "1935" Ports [0, 1] Position [1145, 312, 1200, 338] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "20" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "8" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "107,239,336,437" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,a4afb800,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'20');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "1936" Ports [1, 1] Position [885, 295, 930, 325] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1937" Ports [1, 1] Position [300, 280, 345, 310] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1938" Ports [1, 1] Position [1255, 175, 1300, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "1939" Ports [2, 1] Position [395, 250, 455, 310] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "658,507,348,661" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "1940" Ports [2, 1] Position [1030, 265, 1090, 325] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "5" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "658,507,348,661" block_type "counter" sg_icon_stat "60,60,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.88 38.88 46" ".88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.88 38.88 30.88" " ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "1941" Ports [2, 1] Position [615, 267, 670, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "1942" Ports [2, 1] Position [1250, 282, 1305, 338] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "55,56,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35" ".77 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77" " 35.77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ]," "[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1," "'\\bfa \\geq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "1943" Ports [2, 1] Position [755, 283, 800, 332] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1944" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1945" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1946" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1947" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1948" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1949" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1950" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "1951" Ports [2, 1] Position [210, 268, 255, 317] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "1952" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "1953" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "1954" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "1955" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "1956" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "1957" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "1958" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Outport Name "Q" SID "1959" Position [1440, 183, 1470, 197] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 DstBlock "S-R Latch2" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Relational" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [30, 0] Branch { DstBlock "Convert" DstPort 1 } Branch { Points [0, -120] DstBlock "Convert2" DstPort 1 } } Line { SrcBlock "Relational1" SrcPort 1 Points [20, 0; 0, 95; -340, 0] Branch { Points [-255, 0] Branch { Points [-375, 0] Branch { Points [0, -140] DstBlock "Counter" DstPort 1 } Branch { Points [-195, 0; 0, -100] DstBlock "S-R Latch2" DstPort 2 } } Branch { Points [0, -85] DstBlock "S-R Latch1" DstPort 2 } } Branch { Points [0, -125] DstBlock "Counter1" DstPort 1 } } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational1" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Counter1" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Q" DstPort 1 } Annotation { Name "Need a delay of ~746 160MHz cycles" Position [527, 204] } Annotation { Name "Hold the signal High for 20 cycles" Position [1137, 204] } Annotation { Name "This delay allows the Tx_Running debug output to directly trigger\npkt detection at another node. The de" "lay value was measured in hardware\nand corresponds to the latencies in the Tx/Rx circuits and the Rx processing\n" "delay from first sample to pkt det firing." Position [545, 470] } } } Block { BlockType From Name "From8" SID "1968" Position [595, 640, 790, 660] ZOrder -9 ShowName off GotoTag "regTx_TxRunning_Output_Sel" TagVisibility "global" } Block { BlockType Reference Name "Mux" SID "1993" Ports [3, 1] Position [865, 634, 885, 726] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "20,92,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 13.1429 78.8571 92 " "0 ],[0.77 0.82 0.91 ]);\nplot([0 20 20 0 0 ],[0 13.1429 78.8571 92 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10" ".44 7.55 5.55 ],[48.22 48.22 50.22 48.22 50.22 50.22 50.22 48.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55" " ],[46.22 46.22 48.22 48.22 46.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[44.22 44.22 46." "22 46.22 44.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[42.22 42.22 44.22 42.22 44.22 44.2" "2 42.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Register" SID "2044" Ports [1, 1] Position [935, 667, 965, 693] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "2045" Ports [1, 1] Position [1005, 667, 1035, 693] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "2049" Ports [1, 1] Position [625, 667, 655, 693] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_TX_RUNNING" SID "2133" Ports [1, 1] Position [1090, 670, 1150, 690] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "Register" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "dbg_TX_RUNNING" DstPort 1 } Line { SrcBlock "Dly" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 Points [70, 0] Branch { Points [0, 30] DstBlock "Dly" DstPort 1 } Branch { DstBlock "Convert9" DstPort 1 } } Line { SrcBlock "Convert9" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Tx Active" SrcPort 1 DstBlock "Register5" DstPort 1 } Annotation { Name "TX_RUNNING is a debug signal usually tied to an FPGA\noutput for real-time observation on an oscil" "loscope. The mux\nhere selects between the raw Tx Active signal or\na delayed version. The raw signal is useful" " for observing\nMAC timing. The delayed version is useful for triggering\npacket detection at an Rx node." Position [683, 825] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Tx Gain" SID "2085" Ports [2, 4] Position [915, 878, 995, 1032] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Tx Gain" Location [48, 93, 1694, 1412] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Sw Tx" SID "2086" Position [130, 303, 160, 317] IconDisplay "Port number" } Block { BlockType Inport Name "Hw Tx" SID "2087" Position [130, 358, 160, 372] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Convert" SID "2088" Ports [1, 1] Position [200, 301, 225, 319] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "2089" Ports [1, 1] Position [200, 356, 225, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2090" Ports [2, 1] Position [425, 348, 465, 372] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,24,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 24 24 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\n\ncolor('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "PHY_TX_GAIN_A" SID "2091" Ports [1, 1] Position [355, 395, 420, 415] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "PHY_TX_GAIN_B" SID "2092" Ports [1, 1] Position [355, 465, 420, 485] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "PHY_TX_GAIN_C" SID "2093" Ports [1, 1] Position [355, 530, 420, 550] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "PHY_TX_GAIN_D" SID "2094" Ports [1, 1] Position [355, 595, 420, 615] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to" " Xilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top l" "evel input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "2095" Ports [1, 1] Position [585, 407, 615, 433] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "2096" Ports [2, 1] Position [510, 392, 545, 443] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "2097" Ports [1, 1] Position [585, 477, 615, 503] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "2098" Ports [2, 1] Position [510, 462, 545, 513] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "2099" Ports [1, 1] Position [585, 542, 615, 568] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "2100" Ports [2, 1] Position [510, 527, 545, 578] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "2101" Ports [1, 1] Position [585, 607, 615, 633] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('" "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "2102" Ports [2, 1] Position [510, 592, 545, 643] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,51,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 51 51 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 51 51 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[30.55" " 30.55 35.55 30.55 35.55 35.55 35.55 30.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[25.55 25.55 30" ".55 30.55 25.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[20.55 20.55 25.55 25.55 20.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[15.55 15.55 20.55 15.55 20.55 20.55 15.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('out" "put',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Tx Gain A" SID "2103" Position [655, 413, 685, 427] IconDisplay "Port number" } Block { BlockType Outport Name "Tx Gain B" SID "2104" Position [655, 483, 685, 497] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Tx Gain C" SID "2105" Position [655, 548, 685, 562] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Tx Gain D" SID "2106" Position [655, 613, 685, 627] Port "4" IconDisplay "Port number" } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Hw Tx" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Sw Tx" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "PHY_TX_GAIN_A" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [175, 0; 0, 45] DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 Points [25, 0; 0, 70] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, 70] Branch { DstBlock "Register4" DstPort 2 } Branch { Points [0, 65] Branch { DstBlock "Register6" DstPort 2 } Branch { DstBlock "Register8" DstPort 2 } } } } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Tx Gain A" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Tx Gain B" DstPort 1 } Line { SrcBlock "PHY_TX_GAIN_B" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register6" SrcPort 1 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Tx Gain C" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "Tx Gain D" DstPort 1 } Line { SrcBlock "PHY_TX_GAIN_C" SrcPort 1 DstBlock "Register6" DstPort 1 } Line { SrcBlock "PHY_TX_GAIN_D" SrcPort 1 DstBlock "Register8" DstPort 1 } Annotation { Name "Pass through MAC Tx gain setting to radio controller" Position [502, 175] } } } Block { BlockType SubSystem Name "negedge" SID "2134" Ports [1, 1] Position [1205, 338, 1250, 352] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [384, 656, 940, 879] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "2135" Position [265, 183, 295, 197] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "2136" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "2137" Ports [1, 1] Position [480, 181, 505, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('no" "t');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "2138" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32." "66 32.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 3" "2.66 32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "2139" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [85, 0] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "PHY Start" SID "2146" Position [1260, 153, 1290, 167] IconDisplay "Port number" } Line { SrcBlock "S-R Latch" SrcPort 1 Points [55, 0] Branch { DstBlock "Goto1" DstPort 1 } Branch { Labels [0, 0] Points [0, -70] DstBlock "Radio TXEN/RXEN Control" DstPort 2 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "From" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 DstBlock "Radio TXEN/RXEN Control" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 Points [20, 0] Branch { DstBlock "S-R Latch1" DstPort 1 } Branch { Points [0, 110] DstBlock "Logical6" DstPort 1 } } Line { SrcBlock "Add TXEN Extension" SrcPort 2 DstBlock "Posedge5" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Add TXEN Extension" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Add TXEN Extension" SrcPort 1 Points [60, 0; 0, -70] DstBlock "Logical8" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "RX_SIGS_INVALID" DstPort 1 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "S-R Latch" DstPort 2 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "Logical8" SrcPort 1 DstBlock "S-R Latch2" DstPort 2 } Line { SrcBlock "From2" SrcPort 1 Points [435, 0; 0, -40] Branch { DstBlock "Logical6" DstPort 2 } Branch { Points [0, -95] Branch { Points [0, -100] DstBlock "Logical8" DstPort 2 } Branch { DstBlock "Logical7" DstPort 2 } } } Line { SrcBlock "Logical5" SrcPort 1 Points [25, 0] Branch { DstBlock "Pkt Buf Sel" DstPort 1 } Branch { Points [0, 135] Branch { DstBlock "Tx Gain" DstPort 1 } Branch { Points [0, 170] DstBlock "PHY Mode Sel" DstPort 1 } } } Line { SrcBlock "Pkt Buf Sel" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Tx Gain" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Tx Gain" SrcPort 2 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Tx Gain" SrcPort 3 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Tx Gain" SrcPort 4 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "From17" SrcPort 1 Points [160, 0] Branch { DstBlock "Pkt Buf Sel" DstPort 2 } Branch { Points [0, 180] Branch { DstBlock "Tx Gain" DstPort 2 } Branch { Points [0, 125] DstBlock "PHY Mode Sel" DstPort 2 } } } Line { SrcBlock "From18" SrcPort 1 DstBlock "Register4" DstPort 2 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 Points [10, 0] Branch { DstBlock "PHY Start" DstPort 1 } Branch { Points [0, 170] DstBlock "Add MAC Extension" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Add MAC Extension" DstPort 2 } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Posedge2" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Add MAC Extension" SrcPort 1 Points [50, 0] Branch { DstBlock "negedge" DstPort 1 } Branch { Points [0, -45] Branch { DstBlock "Posedge2" DstPort 1 } Branch { Points [0, -65] DstBlock "Tx Active Debug Signal" DstPort 1 } } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "Slice1" SrcPort 1 Points [10, 0] Branch { DstBlock "Goto11" DstPort 1 } Branch { Points [0, 90] DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "Slice2" SrcPort 1 Points [5, 0] Branch { DstBlock "Goto12" DstPort 1 } Branch { Points [0, 70] DstBlock "Logical3" DstPort 2 } } Line { SrcBlock "PHY Mode Sel" SrcPort 1 Points [35, 0] Branch { DstBlock "Slice" DstPort 1 } Branch { Points [0, 35] Branch { DstBlock "Slice1" DstPort 1 } Branch { Points [0, 35] DstBlock "Slice2" DstPort 1 } } Branch { Points [0, -40] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 Points [40, 0; 0, -20] DstBlock "Register3" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 Points [240, 0; 0, 45] DstBlock "Posedge4" DstPort 1 } Line { SrcBlock "Posedge4" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Posedge5" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Posedge1" SrcPort 1 Points [25, 0] Branch { DstBlock "S-R Latch" DstPort 1 } Branch { Points [0, -80] Branch { Points [0, -115] DstBlock "S-R Latch2" DstPort 1 } Branch { DstBlock "Logical7" DstPort 1 } } } Annotation { Name "Radio Controller I/O" Position [330, 317] HorizontalAlignment "left" } Annotation { Name "Software Register" Position [329, 357] HorizontalAlignment "left" } Annotation { Name "MAC Core I/O" Position [327, 337] HorizontalAlignment "left" } Annotation { Name "Internal Control Signal" Position [329, 377] HorizontalAlignment "left" } Annotation { Name "PHY status register uses this SR latch as \"Tx running\" to avoid\nthe race of monitoring the status bit " "in the brief period in between\nthe assertion of MAC_IO_PHY_TX_START and RC_IO_PHY_START." Position [1239, 661] HorizontalAlignment "left" } Annotation { Name "In normal operation the MAC software selects various Tx params for each transmission. These\nparams are s" "et in the MAC core then passed to the Tx PHY when the MAC core initiates\nthe transmission. The Tx PHY logic captur" "es these params at the start of the Tx and applies\nthem to the next Tx waveform. This path (software > mac_hw > ph" "y) allows software to\nselect params when a packet is created, much cleaner than trying to set params via PHY\nregi" "sters in between actual Tx events.\n\nThe Tx PHY is responsible for initiating the TX mode of the radio circuit via" " the radio_controller\ncore. The PHY asserts the radio_controller's usr_RFx_TXEN signal. Some time later the\nradio" "_controller asserts its PHY_Start ouput. This output drives the PHY's RC_PHY_START\ninput port, which begins the wa" "veform generation pipeilne. The PHY -> RC -> PHY path\nis indirect, but it allows good separation of hardware-depen" "dent parameters in the RF front end\n(sequencing of Radio/PA/PHY enables; Tx VGA gain ramp timing; etc) and the har" "dware-\nindependent waveform generation of the PHY." Position [64, 208] HorizontalAlignment "left" } } } Line { SrcBlock "IFFT and Cyclic Prefix" SrcPort 1 DstBlock "Preamble & Outputs" DstPort 2 } Line { SrcBlock "IFFT and Cyclic Prefix" SrcPort 2 DstBlock "Preamble & Outputs" DstPort 3 } Line { SrcBlock "IFFT and Cyclic Prefix" SrcPort 3 DstBlock "Preamble & Outputs" DstPort 4 } Line { SrcBlock "Mux" SrcPort 5 Points [15, 0] Branch { Points [0, 60; -555, 0; 0, -80] DstBlock "OFDM Symbol Ctrl" DstPort 2 } Branch { DstBlock "IFFT and Cyclic Prefix" DstPort 5 } } Line { SrcBlock "HT Preamble Gen" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "HT Preamble Gen" SrcPort 2 DstBlock "Mux" DstPort 2 } Line { SrcBlock "PSDU Syms Gen" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "PSDU Syms Gen" SrcPort 2 DstBlock "Mux" DstPort 4 } Line { SrcBlock "OFDM Symbol Ctrl" SrcPort 1 Points [25, 0] Branch { DstBlock "PSDU Syms Gen" DstPort 1 } Branch { Points [0, -65] DstBlock "HT Preamble Gen" DstPort 1 } } Line { SrcBlock "OFDM Symbol Ctrl" SrcPort 2 Points [35, 0] Branch { Points [0, -75] DstBlock "HT Preamble Gen" DstPort 2 } Branch { DstBlock "PSDU Syms Gen" DstPort 2 } } Line { SrcBlock "Start Ctrl" SrcPort 1 Points [55, 0] Branch { DstBlock "OFDM Symbol Ctrl" DstPort 1 } Branch { Points [0, -95] DstBlock "Preamble & Outputs" DstPort 1 } } Line { SrcBlock "IFFT and Cyclic Prefix" SrcPort 4 Points [30, 0; 0, 75; -560, 0; 0, -55] Branch { Points [0, -85] DstBlock "HT Preamble Gen" DstPort 3 } Branch { DstBlock "PSDU Syms Gen" DstPort 3 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "IFFT and Cyclic Prefix" DstPort 1 } Line { SrcBlock "Mux" SrcPort 2 DstBlock "IFFT and Cyclic Prefix" DstPort 2 } Line { SrcBlock "Mux" SrcPort 3 DstBlock "IFFT and Cyclic Prefix" DstPort 3 } Line { SrcBlock "Mux" SrcPort 4 DstBlock "IFFT and Cyclic Prefix" DstPort 4 } Line { SrcBlock "PSDU Syms Gen" SrcPort 3 Points [0, 30; -345, 0] DstBlock "OFDM Symbol Ctrl" DstPort 3 } Annotation { Name "Copyright 2017 Mango Communications, Inc. All rights reserved.\n\nDistributed under the Mango Refer" "ence Design License:\nhttp://mangocomm.com/802.11/license" Position [692, 471] DropShadow on } Annotation { Name "TODO:\n-Use Sym_Cfg for cyclic prefix len (for short_GI mode)\n-Check scaling of HT-STF " Position [72, 398] HorizontalAlignment "left" } } } MatData { NumRecords 1 DataRecord { Tag DataTag0 Data " %)30 . \")X 8 ( @ % \" $ ! 0 % 0 !@ $ , 0 . . 8 ( ! " " % \" $ ' 0 0 !P '1A7, !V86QU97, . & $ 8 ( 0 % \" $ # 0 " " . 0 8 ( ! % \" $ + 0 0 \"P $A$3\"!.971L:7-T . 2 8 " " ( ! % \" $ 8 0 0 & $5X<&]R=\"!A7-I

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