C_BASEADDR C_BASEADDR Base Address '> C_MEMMAP_TIMER0_TIMELEFT C_MEMMAP_TIMER0_TIMELEFT From Register data type: UFix_32_0 '> C_MEMMAP_TIMER1_TIMELEFT C_MEMMAP_TIMER1_TIMELEFT From Register data type: UFix_32_0 '> C_MEMMAP_TIMER2_TIMELEFT C_MEMMAP_TIMER2_TIMELEFT From Register data type: UFix_32_0 '> C_MEMMAP_TIMER3_TIMELEFT C_MEMMAP_TIMER3_TIMELEFT From Register data type: UFix_32_0 '> C_MEMMAP_TIMER_CONTROL_R C_MEMMAP_TIMER_CONTROL_R From Register data type: UFix_32_0 '> C_MEMMAP_TIMER_STATUS C_MEMMAP_TIMER_STATUS From Register data type: UFix_32_0 '> C_MEMMAP_TIMER0_COUNTTO C_MEMMAP_TIMER0_COUNTTO To Register data type: UFix_32_0 '> C_MEMMAP_TIMER1_COUNTTO C_MEMMAP_TIMER1_COUNTTO To Register data type: UFix_32_0 '> C_MEMMAP_TIMER2_COUNTTO C_MEMMAP_TIMER2_COUNTTO To Register data type: UFix_32_0 '> C_MEMMAP_TIMER3_COUNTTO C_MEMMAP_TIMER3_COUNTTO To Register data type: UFix_32_0 '> C_MEMMAP_TIMER_CONTROL_W C_MEMMAP_TIMER_CONTROL_W To Register data type: UFix_32_0 '> ]> Memory Map Information All &C_BASEADDR; &C_MEMMAP_TIMER0_TIMELEFT; &C_MEMMAP_TIMER1_TIMELEFT; &C_MEMMAP_TIMER2_TIMELEFT; &C_MEMMAP_TIMER3_TIMELEFT; &C_MEMMAP_TIMER_CONTROL_R; &C_MEMMAP_TIMER_STATUS; &C_MEMMAP_TIMER0_COUNTTO; &C_MEMMAP_TIMER1_COUNTTO; &C_MEMMAP_TIMER2_COUNTTO; &C_MEMMAP_TIMER3_COUNTTO; &C_MEMMAP_TIMER_CONTROL_W; From/To Registers &C_BASEADDR; &C_MEMMAP_TIMER0_TIMELEFT; &C_MEMMAP_TIMER1_TIMELEFT; &C_MEMMAP_TIMER2_TIMELEFT; &C_MEMMAP_TIMER3_TIMELEFT; &C_MEMMAP_TIMER_CONTROL_R; &C_MEMMAP_TIMER_STATUS; &C_MEMMAP_TIMER0_COUNTTO; &C_MEMMAP_TIMER1_COUNTTO; &C_MEMMAP_TIMER2_COUNTTO; &C_MEMMAP_TIMER3_COUNTTO; &C_MEMMAP_TIMER_CONTROL_W; From/To FIFOs &C_BASEADDR; Shared Memories &C_BASEADDR;