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# Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
# 
# You may copy and modify these files for your own internal
# use solely with Xilinx programmable logic devices and
# Xilinx EDK system or create IP modules solely for Xilinx
# programmable logic devices and Xilinx EDK system.
# No rights are granted to distribute any files unless they
# are distributed in Xilinx programmable logic devices.
#
# Peripheral Analyze Order (PAO) file
# created by System Generator
# Jul 23, 2008 12:11:47 PM
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lib warp_timer_plbw_v1_00_a warp_timer vhdl
lib warp_timer_plbw_v1_00_a warp_timer_plbw vhdl