Model {
  Name			  "ofdm_txrx_supermimo"
  Version		  7.1
  MdlSubVersion		  0
  GraphicalInterface {
    NumRootInports	    0
    NumRootOutports	    0
    ParameterArgumentNames  ""
    ComputedModelVersion    "1.1395"
    NumModelReferences	    0
    NumTestPointedSignals   0
  }
  SavedCharacterEncoding  "windows-1252"
  PostLoadFcn		  "ofdm_rx_supermimo_init"
  SaveDefaultBlockParams  on
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  on
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ShowTestPointIcons	  on
  ShowSignalResolutionIcons on
  ShowViewerIcons	  on
  SortedOrder		  off
  ExecutionContextIcon	  off
  ShowLinearizationAnnotations on
  ScopeRefreshTime	  0.035000
  OverrideScopeRefreshTime on
  DisableAllScopes	  off
  DataTypeOverride	  "UseLocalSettings"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks on
  BrowserLookUnderMasks	  on
  InitFcn		  "ofdm_rx_supermimo_init"
  StartFcn		  "ofdm_rx_supermimo_init"
  Created		  "Sun Jun 14 16:43:05 2009"
  Creator		  "murphpo"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "Administrator"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Sun Oct 24 14:23:50 2010"
  RTWModifiedTimeStamp	  0
  ModelVersionFormat	  "1.%<AutoIncrement:1395>"
  ConfigurationManager	  "None"
  SimulationMode	  "normal"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  CovReportOnPause	  on
  CovModelRefEnable	  "Off"
  ExtModeBatchMode	  off
  ExtModeEnableFloating	  on
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigDurationFloating "auto"
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  ShowModelReferenceBlockVersion off
  ShowModelReferenceBlockIO off
  Array {
    Type		    "Handle"
    Dimension		    1
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	  ConsecutiveZCsStepRelTol "10*128*eps"
	  MaxConsecutiveZCs	  "1000"
	  ExtrapolationOrder	  4
	  NumberNewtonIterations  1
	  MaxStep		  "auto"
	  MinStep		  "auto"
	  MaxConsecutiveMinStep	  "1"
	  RelTol		  "1e-3"
	  SolverMode		  "SingleTasking"
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	  SolverName		  "VariableStepDiscrete"
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	  MaxDataPoints		  "1000"
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	  SaveFormat		  "Array"
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	  StateSaveName		  "xout"
	  TimeSaveName		  "tout"
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	  OutputOption		  "RefineOutputTimes"
	  OutputTimes		  "[]"
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	  Version		  "1.4.0"
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	  ExpressionDepthLimit	  2147483647
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	  LifeSpan		  "inf"
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	Simulink.DebuggingCC {
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	  RTPrefix		  "error"
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	  ReadBeforeWriteMsg	  "UseLocalSettings"
	  WriteAfterWriteMsg	  "UseLocalSettings"
	  WriteAfterReadMsg	  "UseLocalSettings"
	  AlgebraicLoopMsg	  "warning"
	  ArtificialAlgebraicLoopMsg "warning"
	  SaveWithDisabledLinksMsg "warning"
	  SaveWithParameterizedLinksMsg	"none"
	  CheckSSInitialOutputMsg on
	  CheckExecutionContextPreStartOutputMsg off
	  CheckExecutionContextRuntimeOutputMsg	off
	  SignalResolutionControl "UseLocalSettings"
	  BlockPriorityViolationMsg "warning"
	  MinStepSizeMsg	  "warning"
	  TimeAdjustmentMsg	  "none"
	  MaxConsecutiveZCsMsg	  "error"
	  SolverPrmCheckMsg	  "warning"
	  InheritedTsInSrcMsg	  "warning"
	  DiscreteInheritContinuousMsg "warning"
	  MultiTaskDSMMsg	  "error"
	  MultiTaskCondExecSysMsg "error"
	  MultiTaskRateTransMsg	  "error"
	  SingleTaskRateTransMsg  "none"
	  TasksWithSamePriorityMsg "warning"
	  SigSpecEnsureSampleTimeMsg "warning"
	  CheckMatrixSingularityMsg "none"
	  IntegerOverflowMsg	  "warning"
	  Int32ToFloatConvMsg	  "warning"
	  ParameterDowncastMsg	  "error"
	  ParameterOverflowMsg	  "error"
	  ParameterUnderflowMsg	  "none"
	  ParameterPrecisionLossMsg "warning"
	  ParameterTunabilityLossMsg "warning"
	  UnderSpecifiedDataTypeMsg "none"
	  UnnecessaryDatatypeConvMsg "none"
	  VectorMatrixConversionMsg "none"
	  InvalidFcnCallConnMsg	  "error"
	  FcnCallInpInsideContextMsg "Use local settings"
	  SignalLabelMismatchMsg  "none"
	  UnconnectedInputMsg	  "warning"
	  UnconnectedOutputMsg	  "warning"
	  UnconnectedLineMsg	  "warning"
	  SFcnCompatibilityMsg	  "none"
	  UniqueDataStoreMsg	  "none"
	  BusObjectLabelMismatch  "warning"
	  RootOutportRequireBusObject "warning"
	  AssertControl		  "UseLocalSettings"
	  EnableOverflowDetection off
	  ModelReferenceIOMsg	  "none"
	  ModelReferenceVersionMismatchMessage "none"
	  ModelReferenceIOMismatchMessage "none"
	  ModelReferenceCSMismatchMessage "none"
	  ModelReferenceSimTargetVerbose off
	  UnknownTsInhSupMsg	  "warning"
	  ModelReferenceDataLoggingMessage "warning"
	  ModelReferenceSymbolNameMessage "warning"
	  ModelReferenceExtraNoncontSigs "error"
	  StateNameClashWarn	  "warning"
	  StrictBusMsg		  "Warning"
	  LoggingUnavailableSignals "error"
	  BlockIODiagnostic	  "none"
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	Simulink.HardwareCC {
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	  ProdBitPerChar	  8
	  ProdBitPerShort	  16
	  ProdBitPerInt		  32
	  ProdBitPerLong	  32
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	  ProdWordSize		  32
	  ProdShiftRightIntArith  on
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	  TargetBitPerChar	  8
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	  TargetBitPerInt	  32
	  TargetBitPerLong	  32
	  TargetShiftRightIntArith on
	  TargetIntDivRoundTo	  "Undefined"
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	  TargetWordSize	  32
	  TargetTypeEmulationWarnSuppressLevel 0
	  TargetPreprocMaxBitsSint 32
	  TargetPreprocMaxBitsUint 32
	  TargetHWDeviceType	  "Specified"
	  TargetUnknown		  off
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	Simulink.ModelReferenceCC {
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	  UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
	  CheckModelReferenceTargetMessage "error"
	  ModelReferenceNumInstancesAllowed "Multi"
	  ModelReferenceSigSizeVariationType "Always allowed"
	  ModelReferencePassRootInputsByReference on
	  ModelReferenceMinAlgLoopOccurrences off
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	Simulink.RTWCC {
	  $BackupClass		  "Simulink.RTWCC"
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	    Cell		    "IncludeHyperlinkInReport"
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	  Version		  "1.4.0"
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	  ProcessScriptMode	  "Default"
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	  TargetLang		  "C"
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	  RTWCompilerOptimization "Off"
	  Array {
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	    Simulink.CodeAppCC {
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  BlockDefaults {
    Orientation		    "right"
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    FontSize		    10
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  BlockParameterDefaults {
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      Inputs		      "4"
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      BusObject		      "BusObject"
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    Block {
      BlockType		      BusSelector
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      BlockType		      ComplexToRealImag
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    Block {
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      OutDataTypeMode	      "Same as input"
      OutDataType	      "fixdt(1,16,0)"
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      BlockType		      Goto
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      BlockType		      Mux
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      OutMax		      "[]"
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    Block {
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      BlockType		      RealImagToComplex
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    Block {
      BlockType		      Reference
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    Block {
      BlockType		      Scope
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      TickLabels	      "OneTimeTick"
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    Block {
      BlockType		      "S-Function"
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      SystemSampleTime	      "-1"
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      RTWMemSecDataParameters "Inherit from model"
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    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
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    Block {
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      SaturateOnIntegerOverflow	on
      ZeroCross		      on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Terminator
    }
    Block {
      BlockType		      ZeroOrderHold
      SampleTime	      "1"
    }
    Block {
      BlockType		      Constant
      Value		      "1"
      VectorParams1D	      on
      SamplingMode	      "Sample based"
      OutMin		      "[]"
      OutMax		      "[]"
      OutDataTypeMode	      "Inherit from 'Constant value'"
      OutDataType	      "fixdt(1,16,0)"
      ConRadixGroup	      "Use specified scaling"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: Inherit from 'Constant value'"
      SampleTime	      "inf"
      FramePeriod	      "inf"
    }
    Block {
      BlockType		      DiscretePulseGenerator
      PulseType		      "Sample based"
      TimeSource	      "Use simulation time"
      Amplitude		      "1"
      Period		      "2"
      PulseWidth	      "1"
      PhaseDelay	      "0"
      SampleTime	      "1"
      VectorParams1D	      on
    }
    Block {
      BlockType		      RelationalOperator
      Operator		      ">="
      InputSameDT	      on
      LogicOutDataTypeMode    "Logical (see Configuration Parameters: Optimization)"
      LogicDataType	      "uint(8)"
      OutDataTypeStr	      "Inherit: Logical (see Configuration Parameters: Optimization)"
      ZeroCross		      on
      SampleTime	      "-1"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    UseDisplayTextAsClickCallback off
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "ofdm_txrx_supermimo"
    Location		    [202, 74, 1654, 866]
    Open		    on
    ModelBrowserVisibility  on
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
    TiledPageScale	    1
    ShowPageBoundaries	    off
    ZoomFactor		    "275"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      " System Generator"
      Tag		      "genX"
      Ports		      []
      Position		      [251, 128, 298, 173]
      ShowName		      off
      AttributesFormatString  "System\\nGenerator"
      UserDataPersistent      on
      UserData		      "DataTag0"
      SourceBlock	      "xbsIndex_r4/ System Generator"
      SourceType	      "Xilinx System Generator Block"
      ShowPortLabels	      "FromPortIcon"
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      infoedit		      " System Generator"
      xilinxfamily	      "virtex2p"
      part		      "xc2vp70"
      speed		      "-6"
      package		      "ff1517"
      synthesis_tool	      "XST"
      clock_wrapper	      "Clock Enables"
      directory		      "./OFDM_txrx_v15_v50"
      testbench		      off
      simulink_period	      "1"
      sysclk_period	      "10"
      dcm_input_clock_period  "100"
      incr_netlist	      off
      trim_vbits	      "Everywhere in SubSystem"
      dbl_ovrd		      "According to Block Masks"
      core_generation	      "According to Block Masks"
      run_coregen	      off
      deprecated_control      off
      eval_field	      "0"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "sysgen"
      block_version	      "10.1.3"
      sg_icon_stat	      "39,31,-1,-1,red,beige,0,07734,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 39 39 0 ],[0 0 31 31 ],[0.93 0.92 0.86]);\npatch([11 6 13 6 11 19 21 23 32 25 18 13 20 13 18 25 32 23 21 19 11 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.6 0.2 0.25]);\nplot([0 39 39 0 0 ],[0 0 31 31 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      SubSystem
      Name		      "\"Channel\""
      Ports		      [4, 4]
      Position		      [160, 36, 250, 99]
      NamePlacement	      "alternate"
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      MaskDescription	      "This block implements a simple static 2x2 channel. The one parameter sets the 2x2 channel matrix. h=[1 0;0 1] would be perfectly orthogonal channels. The norm of the matrix should be 1 to avoid overflow."
      MaskPromptString	      "2x2 Channel Matrix|Freq Offset A (phase inc [0,1])|Freq Offset B (phase inc [0,1])|SNR (dB)|Phase Noise (dBc @ 100Hz)"
      MaskStyleString	      "edit,edit,edit,edit,edit"
      MaskTunableValueString  "on,on,on,on,on"
      MaskCallbackString      "||||"
      MaskEnableString	      "on,on,on,on,on"
      MaskVisibilityString    "on,on,on,on,on"
      MaskToolTipString	      "on,on,on,on,on"
      MaskVarAliasString      ",,,,"
      MaskVariables	      "h=@1;freqOffsetA=@2;freqOffsetB=@3;awgnSNR=@4;phNoise=@5;"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      MaskValueString	      "[1 0; 1 0] * 0.45 %[1 0; 0 0] * 0.5 %|0|0|500|-5000"
      MaskTabNameString	      ",,,,"
      System {
	Name			"\"Channel\""
	Location		[160, 74, 1868, 1156]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"136"
	Block {
	  BlockType		  Inport
	  Name			  "AntA I"
	  Position		  [80, 183, 110, 197]
	  NamePlacement		  "alternate"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "AntA Q"
	  Position		  [80, 218, 110, 232]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "AntB I"
	  Position		  [80, 258, 110, 272]
	  NamePlacement		  "alternate"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "AntB Q"
	  Position		  [80, 293, 110, 307]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AWGN\nChannel"
	  Ports			  [1, 1]
	  Position		  [775, 189, 855, 231]
	  ShowName		  off
	  SourceBlock		  "commchan3/AWGN\nChannel"
	  SourceType		  "AWGN Channel"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData "off"
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "rand"
	  noiseMode		  "Signal to noise ratio  (SNR)"
	  EbNodB		  "10"
	  EsNodB		  "10"
	  SNRdB			  "awgnSNR"
	  bitsPerSym		  "1"
	  Ps			  "1"
	  Tsym			  "1"
	  variance		  "1"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AWGN\nChannel1"
	  Ports			  [1, 1]
	  Position		  [775, 264, 855, 306]
	  ShowName		  off
	  SourceBlock		  "commchan3/AWGN\nChannel"
	  SourceType		  "AWGN Channel"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData "off"
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  seed			  "rand"
	  noiseMode		  "Signal to noise ratio  (SNR)"
	  EbNodB		  "10"
	  EsNodB		  "10"
	  SNRdB			  "awgnSNR"
	  bitsPerSym		  "1"
	  Ps			  "1"
	  Tsym			  "1"
	  variance		  "1"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Add"
	  Ports			  [2, 1]
	  Position		  [845, 43, 875, 107]
	  ShowName		  off
	  Inputs		  "+-"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^-10"
	  OutDataTypeStr	  "Inherit: Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Sum
	  Name			  "Add1"
	  Ports			  [2, 1]
	  Position		  [845, 108, 875, 172]
	  ShowName		  off
	  Inputs		  "+-"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^-10"
	  OutDataTypeStr	  "Inherit: Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  ComplexToMagnitudeAngle
	  Name			  "Complex to\nMagnitude-Angle"
	  Ports			  [1, 2]
	  Position		  [765, 38, 795, 67]
	  ShowName		  off
	  Output		  "Magnitude and angle"
	}
	Block {
	  BlockType		  ComplexToMagnitudeAngle
	  Name			  "Complex to\nMagnitude-Angle1"
	  Ports			  [1, 2]
	  Position		  [765, 68, 795, 97]
	  ShowName		  off
	  Output		  "Magnitude and angle"
	}
	Block {
	  BlockType		  ComplexToMagnitudeAngle
	  Name			  "Complex to\nMagnitude-Angle2"
	  Ports			  [1, 2]
	  Position		  [765, 103, 795, 132]
	  ShowName		  off
	  Output		  "Magnitude and angle"
	}
	Block {
	  BlockType		  ComplexToMagnitudeAngle
	  Name			  "Complex to\nMagnitude-Angle3"
	  Ports			  [1, 2]
	  Position		  [765, 133, 795, 162]
	  ShowName		  off
	  Output		  "Magnitude and angle"
	}
	Block {
	  BlockType		  ComplexToRealImag
	  Name			  "Complex to\nReal-Imag1"
	  Ports			  [1, 2]
	  Position		  [900, 193, 930, 222]
	  ShowName		  off
	  Output		  "Real and imag"
	}
	Block {
	  BlockType		  ComplexToRealImag
	  Name			  "Complex to\nReal-Imag2"
	  Ports			  [1, 2]
	  Position		  [900, 268, 930, 297]
	  ShowName		  off
	  Output		  "Real and imag"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Delays"
	  Ports			  [2, 2]
	  Position		  [270, 172, 310, 323]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Delays"
	    Location		    [182, 138, 657, 507]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [75, 193, 105, 207]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [45, 253, 75, 267]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay1"
	      Ports		      [1, 1]
	      Position		      [190, 183, 225, 217]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "4"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay2"
	      Ports		      [1, 1]
	      Position		      [190, 243, 225, 277]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "4"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [300, 193, 330, 207]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out2"
	      Position		      [300, 253, 330, 267]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Integer Delay1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay1"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay2"
	      SrcPort		      1
	      DstBlock		      "Out2"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Integer Delay2"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Freq Offset"
	  Ports			  [2, 2]
	  Position		  [340, 173, 380, 322]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Freq Offset"
	    Location		    [527, 287, 832, 584]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [255, 168, 285, 182]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [255, 278, 285, 292]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto1"
	      Position		      [605, 242, 710, 268]
	      ShowName		      off
	      GotoTag		      "freqOffset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Product
	      Name		      "Product4"
	      Ports		      [2, 1]
	      Position		      [310, 167, 340, 198]
	      ShowName		      off
	      InputSameDT	      off
	      OutDataTypeMode	      "Inherit via internal rule"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	      OutDataTypeStr	      "Inherit: Inherit via internal rule"
	      SaturateOnIntegerOverflow	off
	    }
	    Block {
	      BlockType		      Product
	      Name		      "Product5"
	      Ports		      [2, 1]
	      Position		      [310, 277, 340, 308]
	      ShowName		      off
	      InputSameDT	      off
	      OutDataTypeMode	      "Inherit via internal rule"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	      OutDataTypeStr	      "Inherit: Inherit via internal rule"
	      SaturateOnIntegerOverflow	off
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Sine Wave"
	      Ports		      [0, 1]
	      Position		      [225, 368, 270, 412]
	      SourceBlock	      "dspsrcs4/Sine Wave"
	      SourceType	      "Sine Wave"
	      Amplitude		      "1"
	      Frequency		      "freqOffsetB/4"
	      Phase		      "0"
	      SampleMode	      "Discrete"
	      OutComplex	      "Complex"
	      CompMethod	      "Trigonometric fcn"
	      TableSize		      "Speed"
	      SampleTime	      "1"
	      SamplesPerFrame	      "1"
	      additionalParams	      "off"
	      allowOverrides	      "on"
	      dataType		      "double"
	      wordLen		      "16"
	      udDataType	      "sfix(16)"
	      fracBitsMode	      "Best precision"
	      numFracBits	      "15"
	      ResetState	      "Restart at time zero"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Sine Wave1"
	      Ports		      [0, 1]
	      Position		      [135, 198, 180, 242]
	      SourceBlock	      "dspsrcs4/Sine Wave"
	      SourceType	      "Sine Wave"
	      Amplitude		      "1"
	      Frequency		      "freqOffsetA/4"
	      Phase		      "0"
	      SampleMode	      "Discrete"
	      OutComplex	      "Complex"
	      CompMethod	      "Trigonometric fcn"
	      TableSize		      "Speed"
	      SampleTime	      "1"
	      SamplesPerFrame	      "1"
	      additionalParams	      "off"
	      allowOverrides	      "on"
	      dataType		      "double"
	      wordLen		      "16"
	      udDataType	      "sfix(16)"
	      fracBitsMode	      "Best precision"
	      numFracBits	      "15"
	      ResetState	      "Restart at time zero"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [515, 178, 545, 192]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out2"
	      Position		      [515, 288, 545, 302]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Sine Wave"
	      SrcPort		      1
	      Points		      [20, 0]
	      Branch {
		Points			[160, 0]
		Branch {
		  Points		  [60, 0]
		}
		Branch {
		  Points		  [0, -10]
		}
	      }
	      Branch {
		DstBlock		"Product5"
		DstPort			2
	      }
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Product4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Product5"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Sine Wave1"
	      SrcPort		      1
	      Points		      [110, 0]
	      Branch {
		DstBlock		"Product4"
		DstPort			2
	      }
	      Branch {
		Points			[0, 35]
		DstBlock		"Goto1"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Product4"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Product5"
	      SrcPort		      1
	      DstBlock		      "Out2"
	      DstPort		      1
	    }
	    Annotation {
	      Name		      "Optional additive carrier\nModels effects of DC-offsets at Tx/Rx\nSet gain=0.15 for realistic offset"
	      Position		      [499, 351]
	      HorizontalAlignment     "left"
	    }
	  }
	}
	Block {
	  BlockType		  Gain
	  Name			  "Gain"
	  Position		  [475, 195, 505, 225]
	  ShowName		  off
	  ParameterDataTypeMode	  "Inherit via internal rule"
	  ParameterDataType	  "sfix(16)"
	  ParameterScaling	  "2^0"
	  ParamDataTypeStr	  "Inherit: Inherit via internal rule"
	  OutDataTypeMode	  "Inherit via internal rule"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	  OutDataTypeStr	  "Inherit: Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Gain
	  Name			  "Gain1"
	  Position		  [475, 270, 505, 300]
	  ShowName		  off
	  ParameterDataTypeMode	  "Inherit via internal rule"
	  ParameterDataType	  "sfix(16)"
	  ParameterScaling	  "2^0"
	  ParamDataTypeStr	  "Inherit: Inherit via internal rule"
	  OutDataTypeMode	  "Inherit via internal rule"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	  OutDataTypeStr	  "Inherit: Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Reference
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	    Annotation {
	      Name		      "========================================\nStarting iterations for pre-spin/DF support"
	      Position		      [31, 93]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.a:\n-Started from 2.01.t (PHY for refdes14.1_fpgaV2_public)\n-Re-generated memmap (sims are faster w/out EDK Processor block)\n-Removed nearly all scopes (faster sims, less memory consumption)\n-Removed match6/7 blocks and localHeader buffer in autoResponse system (we never used this,\n  after figuring the flagA/flagB actions/conditions were enough)\n-Removed CFO PI filter\n-Moved phase normalization to immediately after pilot arctan\n-Completely redesigned pilot insertion logic and phase estimation/tracking logic. Pilots in Alamouti mode\n   are now interleaved in frequency, not time. Phase error corrections are applied to the current symbol,\n   not the next one. Overall improvement in EVM should be good, especially in Alamouti mode.\n-Fixed checksum bug in random payload mode (payloads were being flagged as all bad)\n-Added readback registers for pilot-based and coarse CFO estimates\n-Added readback register for whether A and B channels are used in pilot phase calculation (Alamouti mode only)"
	      Position		      [31, 138]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.b:\n-Added FFT overflow/AGC/pkt signals to ChipScope"
	      Position		      [31, 198]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.c:\n-Fixed pilot selection for single-path Alamouti"
	      Position		      [31, 228]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.d:\n-Added CFO pre-spin blocks\n  -Multipliers in Tx path, before filters\n  -Pilot-based CFO estimator\n  -Per-packet-buffer CFO capture buffer"
	      Position		      [31, 268]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.e:\n-Changed pre-spin mults to conj-mults"
	      Position		      [36, 303]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.f:\n-Added pktDetection event counter\n-Added logic to capture random Tx payloads to a pkt buffer\n-Shifted autoTx delay up one bit (user's 8 bits are [8:1] of 9-bit delay)\n-Fixed antB conj mult (was conjugating wrong argument)"
	      Position		      [36, 338]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.g:\n-Fixed autoTx delay comparison (to < instead of <=, so that Tx isn't always being asserted)"
	      Position		      [36, 373]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.h:\n-Fixed latency on pilotCFOest_en signals, bumped CFO capture buffer to T=1\n-Fixed autoTx delay counter (now 9 bits, matching delay param)\n-Updated LFSR polynomial"
	      Position		      [36, 398]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.i:\n-Redesigned pilot pre-CFO calculator, to use all received phases instead of trying to average just the last N."
	      Position		      [36, 433]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
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	    Name		    "Through PHY 3.00u"
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	    Annotation {
	      Name		      "Export 3.00.j:\n-Fixed bug in pilot-CFO calc (added reset to unwrapping counter)"
	      Position		      [16, 18]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
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	    Annotation {
	      Name		      "Export 3.00.k:\n-Fixed bug in random payload generation/recording (LFSR en toggled only once per pkt in 3.00j)"
	      Position		      [16, 43]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.l:\n-Fixed random payload mode (again) so capture & checksums will work."
	      Position		      [16, 68]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.m:\n-Added precision and multiplication correction factor to pilotCFO estimator, based on experimental tests."
	      Position		      [16, 98]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.n:\n-Added AutoTwoTx circuit, to optionally transmit every user-initiated packet twice with programmed delay\n-Added external PktDetReset input to hold Rx PHY in reset via GPIO"
	      Position		      [16, 128]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.o:\n-Fixed timing of AutoTwoTx\n-Added autoResponse action to force Tx antenna swap\n-Added optional circuit to calculate/store channel magnitudes (and not raw I/Q)"
	      Position		      [16, 163]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.p:\n-Added hooks to disable random payload generation for autoResponse and autoTwoTx transmissions\n   (don't want new payloads for slot2 when testing PHY stuff)\n-Fixed pktBuf mixup on autoTwoTx transissions (shouldn't use autoResponse pktBuf assignment)"
	      Position		      [16, 208]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.q:\n-Rearranged coarse CFO calc (moved 1/2pi scaling just after arctan)\n-Added coarseCFO correction adder"
	      Position		      [21, 253]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.r:\n-Added coarseCFO correction register to EDK processor block (was omitted in q)"
	      Position		      [21, 288]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.t:\n-Redesigned checksum subsystems; header now has real CRC-16, full packet has real CRC-32"
	      Position		      [21, 338]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.s:\n-Re-export of 3.00r with logic multiliers for V4 project"
	      Position		      [21, 313]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 3.00.u:\n-Added EVM buffers\n  -One summing all EVM for a given subcarrier across symbols\n  -One summing EVM across all subcarriers per symbol\n-Changed antB preamble shift to add (delay relative to antA)\n-Changed autoResponder delay to 9 bits {user8, 0}, so each user bit is a sample delay\n-Renamed coarseCFO correction register"
	      Position		      [21, 373]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
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	  }
	}
	Block {
	  BlockType		  SubSystem
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	  Ports			  []
	  Position		  [15, 15, 82, 35]
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	    Annotation {
	      Name		      "Export 2.00.x:\n-Added register to capture autoTx delay (required for actions which require a Flag)\n-Added better TxStart logic (posedge on TxStart gateway; OR'd AF_TxDone for TxRunning SR reset)\n-Screwed with precision in equalizer (more fractional bits, knowing abs(H)<1)\n-Register phase error to chipscope/debug port\n-Fixed TxPktLength%12==0 problem\n-Adjust pktDet RSSI for RF gain change\n-Added muxes to bypass Tx interp filters"
	      Position		      [16, 43]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.00.y:\n-Added option to use diff(phaseError) for fine CFO\n-Shortened coarse CFO window to 68 samles (from 72)\n-CFO delay should be > 0 (already settable in software)\n-Increased precision of input to phase error scaling/lookup (remember to update constant in software!)"
	      Position		      [16, 103]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.00.z:\n-Shortened coarse CFO window to 64 samples (from 68)"
	      Position		      [16, 138]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.00.z:\n-Shortened coarse CFO window to 64 samples (from 68)"
	      Position		      [16, 168]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.a:\n-Added sanity checking for max phase diff in coarse CFO calc\n-Added force reset of coarse CFO output when pkt not detected (coarse CFO was non-zero inter-packets before?)\n-Added preCFO at Tx\n-Added Sw reset of autoResponse flagA/B (via RxControlBits register)\n-Modified action registers to include usePreCFO bit\n-Increased accuracy/latency of coarse CFO arctan (11 cycles to 15)\n-Reworked coarse CFO control (running sum, uses both longCorr crossings)\n-Inverted training symbol; better PAPR in time domain this way (don't know why it was negated before)"
	      Position		      [16, 218]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.b:\n-Fixed action register connections (only action0 was connected in 2.01a)"
	      Position		      [16, 268]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.c:\n-Fixed potential stale state bits in the Tx control; hopefully the cause of the transmit-forever-on-reset condition we see occasionally"
	      Position		      [16, 293]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.d:\n-Added condition to capturing preCFO phaseInc- if either autoResponse flag is setup, it won't update the preCFO value"
	      Position		      [16, 318]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.e:\n-Added software control of pos/neg/reg for preCFO phaseInc\n-Disabled payload scaling for AF Tx (preamble * afScaling for AF waveform now)\n-BUG: DDS I/Q were connected at Tx for all Tx - maybe not a problem?"
	      Position		      [16, 343]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.f:\n-Fixed DDS I/Q bug\n-Fixed support for non-QPSK baseRate in Alamouti mode\n-Added TxReg bit to enable preCFO for all Tx pkts\n-Added DDS_I to chipscope\n-Disabled generation of chan est buf (to save BRAM for now)"
	      Position		      [16, 383]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.g:\n-Fixed EVM for BPSK\n-Added option to average all 8 pilot tones (instead of 2x average of 4)\n-Fixed phase tracking latency bug"
	      Position		      [16, 428]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.h:\n-Added precision to PN tracking 1/symNumber lookup table\n-Added new packet-long CFO estimator\n-Delayed TxDone by 8 samples\n-Moved Tx scaling post-interp-filters\n-Tx PreCFO mult is now pre-scaling, to avoid overflow"
	      Position		      [16, 473]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.i:\n-Removed packet-long CFO estimator\n-Removed preCFO logic\n-Added post-interp scaling for all four DAC outputs\n-Un-disabled channel estimate shared mem\n-Removed DDS from ChipScope\n-Disabled AF buffers (still a work in progress)\n-Adjusted timing of preamble/payload switch"
	      Position		      [421, 43]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.j:\n-Attempted re-design of phase tracking"
	      Position		      [421, 123]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.k:\n-Second attempt at redesigning phase tracking system. Phase\nerrors can now exceed 2*pi, to track larger residual CFO during\nlonger packets."
	      Position		      [426, 163]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.l:\n-Fixed timing of phase correction block for Alamouti Rx\n-Fixed (very) long-standing bug with 64-QAM checksums (false errors for some pkt lengths)"
	      Position		      [421, 208]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.m:\n-Fixed Tx control symbol counter (caused error for long Alamouti pkts)"
	      Position		      [421, 253]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.n:\n-Un-disabled AF buffer subsystem"
	      Position		      [421, 288]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.o:\n-Added logic to cap maximum pilot phase difference (otherwise a single noisy pilot can \n   corrupt an entire packet by screwing up the phase tracking system)"
	      Position		      [421, 328]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.p:\n-Rebuilt pilot phase difference calc (previous \"fix\" made things worse...)"
	      Position		      [421, 373]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	    Annotation {
	      Name		      "Export 2.01.q:\n-Yet another pilot phase fix"
	      Position		      [421, 408]
	      HorizontalAlignment     "left"
	      FontName		      "Arial"
	      FontSize		      6
	    }
	  }
	}
	Annotation {
	  Name			  "Export 3.00.v:\n-Fixed EVM-per-sc logic to reset at start of each Rx packet"
	  Position		  [131, 33]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.00.w:\n-Fixed autoResponder timing (new CRC blocks were 2 cycles slower declaring good/bad payload)"
	  Position		  [131, 63]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.00.x:\n-Added extra delay bits for autoTx and reTx counters\n-Increased int. bits for per-SC EVM accumulation\n-Added external pktDet port\n-Rearragned TxControlBits register bits"
	  Position		  [136, 108]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
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	Annotation {
	  Name			  "Export 3.00.y:\n-Added additional TxRunning outputs with programmable masks/delays (for faking pktDetecton)\n-Rearranged TxControlBits register and added TxDelays register"
	  Position		  [136, 148]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.00.z:\n-Added logic to allow coarse CFO to be triggered only by external pktDet (so long correlation can be bypassed entirely)\n-Added channel estimate magnitude checking to optionally ignore HAA or HBA when they're too small\n-Added logic to optionally mask part of the AF transmission (to blank the now-noisy unused training symbol)\n-Changed AF scaling so all AF samples are scaled by TxPayload scaling (only re-generated preamble gets scaled\n    by TxPreamble scaling)"
	  Position		  [136, 208]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.a:\n-Fixed timing bug that blocked autoResponder flags"
	  Position		  [136, 253]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.b:\n-Added selectable filters for TxA I/Q"
	  Position		  [136, 283]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.c:\n-Added precision to long correlator"
	  Position		  [136, 313]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.d:\n-Added registers to mask input I/Q until AGC is done"
	  Position		  [136, 343]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.e:\n-Added extra longCorr threshold check"
	  Position		  [136, 368]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.f:\n-Removed dualThreshold logic (didn't help)\n-Rebuilt preamble generator for realy cyclic shift of STS/LTS for antB (removed masking too)\n-Added regs to fix length of Rx pkt (for testing \"true\" AF)\n-Removed unused RxControlBits (reqShortCorr, dynPktLenEn)\n-Added windowing for LongCorr\n-Added optional conjugation of antB preamble\n-Added conjugate-correlation output from LongCorr"
	  Position		  [136, 413]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.g:\n-Redesigned long corr to use 1-bit inputs, 3-bit stored coefficients (avoids input amplitude dependence)"
	  Position		  [456, 43]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.h:\n-Added optional cyclic shift to Tx chain (shift happens before CP insertion, for training and data)\n-Removed conjugation for preamble B\n-Delayed preamble/payload scaling by 2 more (was switching to higher payload scaling too early)\n-This export is OFDM refdes v15.0 V2P public"
	  Position		  [456, 78]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.k:\n-Replaced downsamples-with-enables in phase tracker with DFF->downsample (workaround for Sysgen Virtex-4 export bug)\n-Made 10 multipliers non-embedded (too many mults for DSP48's in V4FX100)\n-This export is OFDM refdes v15.0 V4 public"
	  Position		  [456, 123]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
	Annotation {
	  Name			  "Export 3.01.l:\n-Reverted multiplier settings for further development on V2P\n-This version hasn't actually been integrated in an XPS project (just a milestone post-v15 release)"
	  Position		  [456, 163]
	  HorizontalAlignment	  "left"
	  FontName		  "Arial"
	  FontSize		  6
	}
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      MaskToolTipString	      "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on"
      MaskVarAliasString      ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
      MaskVariables	      "mode=&1;xmp=&2;MemVisToProc=&3;AvailableMemories=&4;portInterfaceTable=&5;bus_type_sgadvanced=&6;bus_type=@7;baseaddr=&8;baseaddr_lock_sgadvanced=&9;baseaddr_lock=@10;dual_clock_sgadvanced=&11;dual_clock=@12;reg_readback_sgadvanced=&13;reg_readback=@14;ucf_file=&15;inheritDeviceType_sgadvanced=&16;inheritDeviceType=@17;clock_name=&18;internalPortList=&19;resetPolarity=&20;memxtable=&21;procinfo=&22;memmapdirty=&23;blockname=&24;xpsintstyle=&25;has_advanced_control=@26;sggui_pos=&27;block_type=&28;block_version=&29;sg_icon_stat=&30;sg_mask_display=&31;sg_list_contents=&32;sg_blockgui_xml=&33;"
      MaskInitialization      "try\n  tmp_gcb = gcb;\n  tmp_gcbh = gcbh;\n  if (strcmp('SysGenIndex',get_param(bdroot(tmp_gcbh),'tag')) && ~isempty(regexp(bdroot(tmp_gcb), '^xbs', 'once')))\n    return;\n  end;\n  xlMungeMaskParams;\n\nblock_type='edkprocessor';\n  serialized_declarations = '{,''block_type''=>''String''}';\n  xledkprocessor_init();\n  ptable_ = xlblockprep(get_param(tmp_gcb, 'MaskWSVariables'));\ncatch\n  global dbgsysgen;\n  if(~isempty(dbgsysgen) && dbgsysgen)\n    e = regexprep(lasterr, '\\n', '\\nError: ');\n    disp(['Error: While running MaskInit code on block ' tmp_gcb ': ' e]);\n    error(e);\n  end\nend\n"
      MaskDisplay	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 ],[0 0 45 45 ],[0.77 0.82 0.91]);\npatch([11 4 15 4 11 23 26 29 42 32 22 15 26 15 22 32 42 29 26 23 11 ],[5 12 23 34 41 41 38 41 41 31 41 34 23 12 5 15 5 5 8 5 5 ],[0.98 0.96 0.92]);\nplot([0 47 47 0 0 ],[0 0 45 45 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ndisp('');\n\nfprintf('','COMMENT: end icon text');\n"
      MaskSelfModifiable      on
      MaskIconFrame	      off
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      MaskValueString	      "EDK pcore generation||<qt bgcolor=\"#FFFFFF\"><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_AF_Blanking_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_AF_TxScaling_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_BER_Errors&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_BER_TotalBits&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_ChanEst_MinMag_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_Constellation_Scaling_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_ControlBits_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_ControlBits_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_FixedPktLen_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_Gains&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_OFDM_SymbolCounts_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_OFDM_SymbolCounts_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_PilotCalcParams_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_PktDet_Delay_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_PktDet_Delay_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_PktDet_LongCorr_Params_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_PktDet_LongCorr_Params_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_PktDet_LongCorr_Thresholds_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_PreCFO_Options_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_PreCFO_PilotCalcCorrection_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_coarseCFO_correction_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_coarseCFOest&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_pilotCFOest&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_pktByteNums_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_pktByteNums_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_pktDetEventCount&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_pktDet_Tresholds_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Rx_pktDone_interruptStatus&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action0_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action0_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action1_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action1_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action2_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action2_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action3_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action3_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action4_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action4_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action5_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Action5_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match0_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match0_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match1_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match1_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match2_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match2_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match3_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match3_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match4_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match4_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match5_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match5_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match6_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match6_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match7_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_AutoReply_Match7_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_FFT_Scaling_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_Interrupt_PktBuf_Ctrl_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_Interrupt_PktBuf_Ctrl_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_Pilots_Index_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;TxRx_Pilots_Values_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_ControlBits_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_ControlBits_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_Delays_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_Delays_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_OFDM_SymCounts_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_OFDM_SymCounts_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_PktRunning&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_Scaling_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_Start_Reset_Control_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;Tx_Start_Reset_Control_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;midPacketRSSI&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;pktDet_controlBits_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;pktDet_controlBits_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;pktDet_durations_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;pktDet_durations_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;pktDet_status&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;pktDet_thresholds_r&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;pktDet_thresholds_w&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\memoryplus.gif\"> &lt;&lt;ChannelEstimates&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\memoryplus.gif\"> &lt;&lt;EVM_perSC&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\memoryplus.gif\"> &lt;&lt;EVM_perSym&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\memoryplus.gif\"> &lt;&lt;PktBufFreqOffsets&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\memoryplus.gif\"> &lt;&lt;RxModulation&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\memoryplus.gif\"> &lt;&lt;TxHeaderTranslate&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\memoryplus.gif\"> &lt;&lt;TxModulation&gt;&gt;<br></div></qt>|<empty>|{'exposed'=>[],'portdir'=>[],'portname'=>[],'shortname'=>[]}||PLB|0x80000000||off||off||off|||off|plb|{}|0|{'mlist'=>['ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register4/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register6/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read Only Register1/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read Only Register2/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register8/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register1/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read-Write Register/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read-Write Register/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register10/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read Only Register/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/TxRx Registers/Read-Write Register4/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/TxRx Registers/Read-Write Register4/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register5/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read-Write Register3/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read-Write Register3/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read-Write Register1/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read-Write Register1/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register9/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register7/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register2/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register3/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read Only Register5/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read Only Register4/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read-Write Register2/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read-Write Register2/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read Only Register6/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Write-Only Register/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Read Only Register3/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register7/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register7/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register8/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register8/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register9/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register9/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register10/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register10/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register12/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register12/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register11/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register11/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register5/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register5/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register1/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register1/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register2/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register2/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register6/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register6/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register3/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register3/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register4/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register4/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register13/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register13/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register14/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/AutoReply Registers/Read-Write Register14/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/TxRx Registers/Write-Only Register/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/TxRx Registers/Read-Write Register/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/TxRx Registers/Read-Write Register/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/TxRx Registers/Write-Only Register2/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/TxRx Registers/Write-Only Register4/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Tx Registers/Read-Write Register1/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Tx Registers/Read-Write Register1/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Tx Registers/Read-Write Register2/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Tx Registers/Read-Write Register2/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/TxRx Registers/Read-Write Register2/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/TxRx Registers/Read-Write Register2/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Tx Registers/Read Only Register/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Tx Registers/Write-Only Register1/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Tx Registers/Read-Write Register/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Tx Registers/Read-Write Register/From Register','ofdm_txrx_supermimo/OFDM Rx MIMO/Packet_Detection/RSSI-based PktDet/Mid-Packet\nRSSI Register/To Register2','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Pkt Detector Registers/Read-Write Register1/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Pkt Detector Registers/Read-Write Register1/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Pkt Detector Registers/Read-Write Register2/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Pkt Detector Registers/Read-Write Register2/From Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Pkt Detector Registers/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Pkt Detector Registers/Read-Write Register5/To Register','ofdm_txrx_supermimo/Memory-mapped\nRegisters/Rx Registers/Pkt Detector Registers/Read-Write Register5/From Register','ofdm_txrx_supermimo/OFDM Rx MIMO/FFT & Chan Est/Channel Estimation\n& Pilot Processing/Chan Est Buffer\n& Mag Calc/Shared Memory','ofdm_txrx_supermimo/OFDM Rx MIMO/Equalizer & Packetizer/Packet_Constructor/EVM Calc/EVM per Subcarrier/Shared Memory','ofdm_txrx_supermimo/OFDM Rx MIMO/Equalizer & Packetizer/Packet_Constructor/EVM Calc/EVM per Symbol/Shared Memory','ofdm_txrx_supermimo/OFDM Rx MIMO/Coarse Freq Correction/PreSpin CFO Sel/Shared Memory','ofdm_txrx_supermimo/OFDM Rx MIMO/Equalizer & Packetizer/Packet_Constructor/Modulation RAM/Modulation Masks/Shared Memory','ofdm_txrx_supermimo/OFDM Tx MIMO/Training_Data/FlexibleMod/PktBuffer_CRC1/Packet Buffer/AutoTx\nHeader Translation/Shared Memory','ofdm_txrx_supermimo/OFDM Tx MIMO/Training_Data/FlexibleMod/control/Tx Modulation/Shared Memory for\nModulation Masks/Shared Memory'],'mlname'=>['\\'Rx_AF_Blanking_w\\'','\\'Rx_AF_TxScaling_w\\'','\\'Rx_BER_Errors\\'','\\'Rx_BER_TotalBits\\'','\\'Rx_ChanEst_MinMag_w\\'','\\'Rx_Constellation_Scaling_w\\'','\\'Rx_ControlBits_r\\'','\\'Rx_ControlBits_w\\'','\\'Rx_FixedPktLen_w\\'','\\'Rx_Gains\\'','\\'Rx_OFDM_SymbolCounts_r\\'','\\'Rx_OFDM_SymbolCounts_w\\'','\\'Rx_PilotCalcParams_w\\'','\\'Rx_PktDet_Delay_r\\'','\\'Rx_PktDet_Delay_w\\'','\\'Rx_PktDet_LongCorr_Params_r\\'','\\'Rx_PktDet_LongCorr_Params_w\\'','\\'Rx_PktDet_LongCorr_Thresholds_w\\'','\\'Rx_PreCFO_Options_w\\'','\\'Rx_PreCFO_PilotCalcCorrection_w\\'','\\'Rx_coarseCFO_correction_w\\'','\\'Rx_coarseCFOest\\'','\\'Rx_pilotCFOest\\'','\\'Rx_pktByteNums_r\\'','\\'Rx_pktByteNums_w\\'','\\'Rx_pktDetEventCount\\'','\\'Rx_pktDet_Tresholds_w\\'','\\'Rx_pktDone_interruptStatus\\'','\\'TxRx_AutoReply_Action0_r\\'','\\'TxRx_AutoReply_Action0_w\\'','\\'TxRx_AutoReply_Action1_r\\'','\\'TxRx_AutoReply_Action1_w\\'','\\'TxRx_AutoReply_Action2_r\\'','\\'TxRx_AutoReply_Action2_w\\'','\\'TxRx_AutoReply_Action3_r\\'','\\'TxRx_AutoReply_Action3_w\\'','\\'TxRx_AutoReply_Action4_r\\'','\\'TxRx_AutoReply_Action4_w\\'','\\'TxRx_AutoReply_Action5_r\\'','\\'TxRx_AutoReply_Action5_w\\'','\\'TxRx_AutoReply_Match0_r\\'','\\'TxRx_AutoReply_Match0_w\\'','\\'TxRx_AutoReply_Match1_r\\'','\\'TxRx_AutoReply_Match1_w\\'','\\'TxRx_AutoReply_Match2_r\\'','\\'TxRx_AutoReply_Match2_w\\'','\\'TxRx_AutoReply_Match3_r\\'','\\'TxRx_AutoReply_Match3_w\\'','\\'TxRx_AutoReply_Match4_r\\'','\\'TxRx_AutoReply_Match4_w\\'','\\'TxRx_AutoReply_Match5_r\\'','\\'TxRx_AutoReply_Match5_w\\'','\\'TxRx_AutoReply_Match6_r\\'','\\'TxRx_AutoReply_Match6_w\\'','\\'TxRx_AutoReply_Match7_r\\'','\\'TxRx_AutoReply_Match7_w\\'','\\'TxRx_FFT_Scaling_w\\'','\\'TxRx_Interrupt_PktBuf_Ctrl_r\\'','\\'TxRx_Interrupt_PktBuf_Ctrl_w\\'','\\'TxRx_Pilots_Index_w\\'','\\'TxRx_Pilots_Values_w\\'','\\'Tx_ControlBits_r\\'','\\'Tx_ControlBits_w\\'','\\'Tx_Delays_r\\'','\\'Tx_Delays_w\\'','\\'Tx_OFDM_SymCounts_r\\'','\\'Tx_OFDM_SymCounts_w\\'','\\'Tx_PktRunning\\'','\\'Tx_Scaling_w\\'','\\'Tx_Start_Reset_Control_r\\'','\\'Tx_Start_Reset_Control_w\\'','\\'midPacketRSSI\\'','\\'pktDet_controlBits_r\\'','\\'pktDet_controlBits_w\\'','\\'pktDet_durations_r\\'','\\'pktDet_durations_w\\'','\\'pktDet_status\\'','\\'pktDet_thresholds_r\\'','\\'pktDet_thresholds_w\\'','\\'ChannelEstimates\\'','\\'EVM_perSC\\'','\\'EVM_perSym\\'','\\'PktBufFreqOffsets\\'','\\'RxModulation\\'','\\'TxHeaderTranslate\\'','\\'TxModulation\\''],'mlstate'=>[0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000]}|{'xmliface'=>'Xilinx//microblaze//iface.xml'}|off||default|0|20,20,383,441|edkprocessor|2.5|47,45,-1,-1,white,blue,0,07734,right|fprintf('','COMMENT: begin icon graphics');\npatch([0 47 47 0 ],[0 0 45 45 ],[0.77 0.82 0.91]);\npatch([11 4 15 4 11 23 26 29 42 32 22 15 26 15 22 32 42 29 26 23 11 ],[5 12 23 34 41 41 38 41 41 31 41 34 23 12 5 15 5 5 8 5 5 ],[0.98 0.96 0.92]);\nplot([0 47 47 0 0 ],[0 0 45 45 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n|{'table'=>{'AvailableMemories'=>'popup(<empty>)','userSelections'=>{'AvailableMemories'=>'<empty>'}}}|"
      MaskTabNameString	      ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
      System {
	Name			"EDK Processor"
	Location		[514, 91, 900, 269]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Constant
	  Name			  "Constant"
	  Position		  [40, 310, 60, 330]
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant1"
	  Position		  [40, 370, 60, 390]
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [40, 430, 60, 450]
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant3"
	  Position		  [40, 490, 60, 510]
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [40, 545, 60, 565]
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant5"
	  Ports			  [0, 1]
	  Position		  [20, 242, 75, 268]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  "on"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "55,26,1,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Sl_wait"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant6"
	  Position		  [40, 665, 60, 685]
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register"
	  Ports			  [0, 1]
	  Position		  [260, 1007, 320, 1063]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_BER_Errors'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_BER_Errors_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register1"
	  Ports			  [0, 1]
	  Position		  [260, 1092, 320, 1148]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_BER_TotalBits'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_BER_TotalBits_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register10"
	  Ports			  [0, 1]
	  Position		  [260, 1872, 320, 1928]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_pktDetEventCount'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_pktDetEventCount_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register11"
	  Ports			  [0, 1]
	  Position		  [260, 1962, 320, 2018]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_pktDone_interruptStatus'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_pktDone_interruptStatus_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register12"
	  Ports			  [0, 1]
	  Position		  [260, 2047, 320, 2103]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action0_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action0_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register13"
	  Ports			  [0, 1]
	  Position		  [260, 2132, 320, 2188]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action1_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action1_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register14"
	  Ports			  [0, 1]
	  Position		  [260, 2222, 320, 2278]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action2_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action2_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register15"
	  Ports			  [0, 1]
	  Position		  [260, 2307, 320, 2363]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action3_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action3_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register16"
	  Ports			  [0, 1]
	  Position		  [260, 2392, 320, 2448]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action4_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action4_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register17"
	  Ports			  [0, 1]
	  Position		  [260, 2482, 320, 2538]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action5_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action5_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register18"
	  Ports			  [0, 1]
	  Position		  [260, 2567, 320, 2623]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match0_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match0_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register19"
	  Ports			  [0, 1]
	  Position		  [260, 2652, 320, 2708]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match1_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match1_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register2"
	  Ports			  [0, 1]
	  Position		  [260, 1182, 320, 1238]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_ControlBits_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_ControlBits_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register20"
	  Ports			  [0, 1]
	  Position		  [260, 2742, 320, 2798]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match2_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match2_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register21"
	  Ports			  [0, 1]
	  Position		  [260, 2827, 320, 2883]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match3_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match3_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register22"
	  Ports			  [0, 1]
	  Position		  [260, 2912, 320, 2968]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match4_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match4_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register23"
	  Ports			  [0, 1]
	  Position		  [260, 3002, 320, 3058]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match5_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match5_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register24"
	  Ports			  [0, 1]
	  Position		  [260, 3087, 320, 3143]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match6_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match6_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register25"
	  Ports			  [0, 1]
	  Position		  [260, 3172, 320, 3228]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match7_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match7_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register26"
	  Ports			  [0, 1]
	  Position		  [260, 3262, 320, 3318]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_Interrupt_PktBuf_Ctrl_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_Interrupt_PktBuf_Ctrl_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register27"
	  Ports			  [0, 1]
	  Position		  [260, 3347, 320, 3403]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_ControlBits_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_ControlBits_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register28"
	  Ports			  [0, 1]
	  Position		  [260, 3432, 320, 3488]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_Delays_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_Delays_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register29"
	  Ports			  [0, 1]
	  Position		  [260, 3522, 320, 3578]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_OFDM_SymCounts_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_OFDM_SymCounts_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register3"
	  Ports			  [0, 1]
	  Position		  [260, 1267, 320, 1323]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_Gains'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_Gains_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register30"
	  Ports			  [0, 1]
	  Position		  [260, 3607, 320, 3663]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_PktRunning'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_PktRunning_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register31"
	  Ports			  [0, 1]
	  Position		  [260, 3692, 320, 3748]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_Start_Reset_Control_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_Start_Reset_Control_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register32"
	  Ports			  [0, 1]
	  Position		  [260, 3782, 320, 3838]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'midPacketRSSI'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "midPacketRSSI_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register33"
	  Ports			  [0, 1]
	  Position		  [260, 3867, 320, 3923]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'pktDet_controlBits_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "pktDet_controlBits_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register34"
	  Ports			  [0, 1]
	  Position		  [260, 3952, 320, 4008]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'pktDet_durations_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "pktDet_durations_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register35"
	  Ports			  [0, 1]
	  Position		  [260, 4042, 320, 4098]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'pktDet_status'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "14"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "pktDet_status_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register36"
	  Ports			  [0, 1]
	  Position		  [260, 4127, 320, 4183]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'pktDet_thresholds_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "pktDet_thresholds_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register4"
	  Ports			  [0, 1]
	  Position		  [260, 1352, 320, 1408]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_OFDM_SymbolCounts_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_OFDM_SymbolCounts_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register5"
	  Ports			  [0, 1]
	  Position		  [260, 1442, 320, 1498]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_PktDet_Delay_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_PktDet_Delay_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register6"
	  Ports			  [0, 1]
	  Position		  [260, 1527, 320, 1583]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_PktDet_LongCorr_Params_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_PktDet_LongCorr_Params_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register7"
	  Ports			  [0, 1]
	  Position		  [260, 1612, 320, 1668]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_coarseCFOest'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_coarseCFOest_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register8"
	  Ports			  [0, 1]
	  Position		  [260, 1702, 320, 1758]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_pilotCFOest'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_pilotCFOest_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register9"
	  Ports			  [0, 1]
	  Position		  [260, 1787, 320, 1843]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_pktByteNums_r'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_pktByteNums_r_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "PLB_ABus"
	  Ports			  [1, 1]
	  Position		  [110, 370, 175, 390]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_ABus'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "65,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "PLB_ABus"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "PLB_PAValid"
	  Ports			  [1, 1]
	  Position		  [110, 430, 175, 450]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "1"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_PAValid'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "65,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "PLB_PAValid"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "PLB_RNW"
	  Ports			  [1, 1]
	  Position		  [110, 490, 175, 510]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "1"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_RNW'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "65,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "PLB_RNW"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "PLB_wrDBus"
	  Ports			  [1, 1]
	  Position		  [110, 545, 175, 565]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_wrDBus'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "65,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "PLB_wrDBus"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "SPLB_Rst"
	  Ports			  [1, 1]
	  Position		  [110, 310, 175, 330]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "1"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'SPLB_Rst'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "65,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "SPLB_Rst"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Shared Memory"
	  Ports			  [3, 1]
	  Position		  [605, 3964, 685, 4056]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/Shared Memory"
	  SourceType		  "Xilinx Shared Memory Random Access Memory Block"
	  shared_memory_name	  "'ChannelEstimates'"
	  depth			  "256"
	  ownership		  "Owned and Initialized Elsewhere"
	  initVector		  "sin(pi*(0:15)/16)"
	  mutex			  "Unprotected"
	  mode			  "Read and Write"
	  write_mode		  "Read After Write"
	  time_out		  "0"
	  latency		  "1"
	  explicit_data_type	  "off"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  implementation	  "Block RAM"
	  use_rpm		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "shmem"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "80,92,1,1,white,blue,0,e2c38f9a,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "ChannelEstimates_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Shared Memory1"
	  Ports			  [3, 1]
	  Position		  [605, 4090, 685, 4180]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/Shared Memory"
	  SourceType		  "Xilinx Shared Memory Random Access Memory Block"
	  shared_memory_name	  "'EVM_perSC'"
	  depth			  "64"
	  ownership		  "Owned and Initialized Elsewhere"
	  initVector		  "sin(pi*(0:15)/16)"
	  mutex			  "Unprotected"
	  mode			  "Read and Write"
	  write_mode		  "Read After Write"
	  time_out		  "0"
	  latency		  "1"
	  explicit_data_type	  "off"
	  arith_type		  "Signed  (2's comp)"
	  n_bits		  "32"
	  bin_pt		  "22"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  implementation	  "Block RAM"
	  use_rpm		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "shmem"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "80,90,1,1,white,blue,0,e2c38f9a,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "EVM_perSC_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Shared Memory2"
	  Ports			  [3, 1]
	  Position		  [605, 4209, 685, 4301]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/Shared Memory"
	  SourceType		  "Xilinx Shared Memory Random Access Memory Block"
	  shared_memory_name	  "'EVM_perSym'"
	  depth			  "256"
	  ownership		  "Owned and Initialized Elsewhere"
	  initVector		  "sin(pi*(0:15)/16)"
	  mutex			  "Unprotected"
	  mode			  "Read and Write"
	  write_mode		  "Read After Write"
	  time_out		  "0"
	  latency		  "1"
	  explicit_data_type	  "off"
	  arith_type		  "Signed  (2's comp)"
	  n_bits		  "32"
	  bin_pt		  "14"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  implementation	  "Block RAM"
	  use_rpm		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "shmem"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "80,92,1,1,white,blue,0,e2c38f9a,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "EVM_perSym_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Shared Memory3"
	  Ports			  [3, 1]
	  Position		  [605, 4329, 685, 4421]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/Shared Memory"
	  SourceType		  "Xilinx Shared Memory Random Access Memory Block"
	  shared_memory_name	  "'PktBufFreqOffsets'"
	  depth			  "32"
	  ownership		  "Owned and Initialized Elsewhere"
	  initVector		  "sin(pi*(0:15)/16)"
	  mutex			  "Unprotected"
	  mode			  "Read and Write"
	  write_mode		  "Read After Write"
	  time_out		  "0"
	  latency		  "1"
	  explicit_data_type	  "off"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "32"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  implementation	  "Block RAM"
	  use_rpm		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "shmem"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "80,92,1,1,white,blue,0,e2c38f9a,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "PktBufFreqOffsets_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Shared Memory4"
	  Ports			  [3, 1]
	  Position		  [605, 4450, 685, 4540]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/Shared Memory"
	  SourceType		  "Xilinx Shared Memory Random Access Memory Block"
	  shared_memory_name	  "'RxModulation'"
	  depth			  "192"
	  ownership		  "Owned and Initialized Elsewhere"
	  initVector		  "sin(pi*(0:15)/16)"
	  mutex			  "Unprotected"
	  mode			  "Read and Write"
	  write_mode		  "Read After Write"
	  time_out		  "0"
	  latency		  "1"
	  explicit_data_type	  "off"
	  arith_type		  "Unsigned"
	  n_bits		  "4"
	  bin_pt		  "0"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  implementation	  "Block RAM"
	  use_rpm		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "shmem"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "80,90,1,1,white,blue,0,e2c38f9a,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "RxModulation_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Shared Memory5"
	  Ports			  [3, 1]
	  Position		  [605, 4574, 685, 4666]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/Shared Memory"
	  SourceType		  "Xilinx Shared Memory Random Access Memory Block"
	  shared_memory_name	  "'TxHeaderTranslate'"
	  depth			  "1024"
	  ownership		  "Owned and Initialized Elsewhere"
	  initVector		  "sin(pi*(0:15)/16)"
	  mutex			  "Unprotected"
	  mode			  "Read and Write"
	  write_mode		  "Read After Write"
	  time_out		  "0"
	  latency		  "1"
	  explicit_data_type	  "off"
	  arith_type		  "Unsigned"
	  n_bits		  "10"
	  bin_pt		  "0"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  implementation	  "Block RAM"
	  use_rpm		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "shmem"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "80,92,1,1,white,blue,0,e2c38f9a,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxHeaderTranslate_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Shared Memory6"
	  Ports			  [3, 1]
	  Position		  [605, 4694, 685, 4786]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/Shared Memory"
	  SourceType		  "Xilinx Shared Memory Random Access Memory Block"
	  shared_memory_name	  "'TxModulation'"
	  depth			  "192"
	  ownership		  "Owned and Initialized Elsewhere"
	  initVector		  "sin(pi*(0:15)/16)"
	  mutex			  "Unprotected"
	  mode			  "Read and Write"
	  write_mode		  "Read After Write"
	  time_out		  "0"
	  latency		  "1"
	  explicit_data_type	  "off"
	  arith_type		  "Unsigned"
	  n_bits		  "4"
	  bin_pt		  "0"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  implementation	  "Block RAM"
	  use_rpm		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "shmem"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "80,92,1,1,white,blue,0,e2c38f9a,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxModulation_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_addrAck"
	  Ports			  [1, 1]
	  Position		  [460, 40, 520, 60]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_addrAck'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_rdComp"
	  Ports			  [1, 1]
	  Position		  [460, 125, 520, 145]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdComp'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_rdDAck"
	  Ports			  [1, 1]
	  Position		  [460, 505, 520, 525]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDAck'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_rdDBus"
	  Ports			  [1, 1]
	  Position		  [460, 595, 520, 615]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDBus'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_wait"
	  Ports			  [1, 1]
	  Position		  [110, 245, 170, 265]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wait'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_wrComp"
	  Ports			  [1, 1]
	  Position		  [460, 425, 520, 445]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrComp'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_wrDAck"
	  Ports			  [1, 1]
	  Position		  [460, 240, 520, 260]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrDAck'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator"
	  Position		  [635, 30, 655, 50]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator1"
	  Position		  [635, 80, 655, 100]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator10"
	  Position		  [720, 605, 740, 625]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator11"
	  Position		  [720, 690, 740, 710]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator12"
	  Position		  [720, 780, 740, 800]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator13"
	  Position		  [720, 865, 740, 885]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator14"
	  Position		  [720, 950, 740, 970]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator15"
	  Position		  [720, 1040, 740, 1060]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator16"
	  Position		  [720, 1125, 740, 1145]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator17"
	  Position		  [720, 1210, 740, 1230]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator18"
	  Position		  [720, 1300, 740, 1320]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator19"
	  Position		  [720, 1385, 740, 1405]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator2"
	  Position		  [635, 225, 655, 245]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator20"
	  Position		  [720, 1470, 740, 1490]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator21"
	  Position		  [720, 1560, 740, 1580]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator22"
	  Position		  [720, 1645, 740, 1665]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator23"
	  Position		  [720, 1730, 740, 1750]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator24"
	  Position		  [720, 1820, 740, 1840]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator25"
	  Position		  [720, 1905, 740, 1925]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator26"
	  Position		  [720, 1990, 740, 2010]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator27"
	  Position		  [720, 2080, 740, 2100]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator28"
	  Position		  [720, 2165, 740, 2185]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator29"
	  Position		  [720, 2250, 740, 2270]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator3"
	  Position		  [635, 275, 655, 295]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator30"
	  Position		  [720, 2340, 740, 2360]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator31"
	  Position		  [720, 2425, 740, 2445]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator32"
	  Position		  [720, 2510, 740, 2530]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator33"
	  Position		  [720, 2600, 740, 2620]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator34"
	  Position		  [720, 2685, 740, 2705]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator35"
	  Position		  [720, 2770, 740, 2790]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator36"
	  Position		  [720, 2860, 740, 2880]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator37"
	  Position		  [720, 2945, 740, 2965]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator38"
	  Position		  [720, 3030, 740, 3050]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator39"
	  Position		  [720, 3120, 740, 3140]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator4"
	  Position		  [280, 245, 300, 265]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator40"
	  Position		  [720, 3205, 740, 3225]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator41"
	  Position		  [720, 3290, 740, 3310]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator42"
	  Position		  [720, 3380, 740, 3400]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator43"
	  Position		  [720, 3465, 740, 3485]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator44"
	  Position		  [720, 3550, 740, 3570]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator45"
	  Position		  [720, 3640, 740, 3660]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator46"
	  Position		  [720, 3725, 740, 3745]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator47"
	  Position		  [720, 3810, 740, 3830]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator48"
	  Position		  [720, 3900, 740, 3920]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator5"
	  Position		  [635, 130, 655, 150]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator6"
	  Position		  [635, 180, 655, 200]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator7"
	  Position		  [720, 345, 740, 365]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator8"
	  Position		  [720, 430, 740, 450]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator9"
	  Position		  [720, 520, 740, 540]
	  ShowName		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register"
	  Ports			  [2, 1]
	  Position		  [615, 327, 675, 383]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_AF_Blanking_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_AF_Blanking_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register1"
	  Ports			  [2, 1]
	  Position		  [615, 412, 675, 468]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_AF_TxScaling_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_AF_TxScaling_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register10"
	  Ports			  [2, 1]
	  Position		  [615, 1192, 675, 1248]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_PktDet_LongCorr_Thresholds_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_PktDet_LongCorr_Thresholds_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register11"
	  Ports			  [2, 1]
	  Position		  [615, 1282, 675, 1338]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_PreCFO_Options_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_PreCFO_Options_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register12"
	  Ports			  [2, 1]
	  Position		  [615, 1367, 675, 1423]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_PreCFO_PilotCalcCorrection_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_PreCFO_PilotCalcCorrection_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register13"
	  Ports			  [2, 1]
	  Position		  [615, 1452, 675, 1508]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_coarseCFO_correction_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_coarseCFO_correction_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register14"
	  Ports			  [2, 1]
	  Position		  [615, 1542, 675, 1598]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_pktByteNums_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_pktByteNums_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register15"
	  Ports			  [2, 1]
	  Position		  [615, 1627, 675, 1683]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_pktDet_Tresholds_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_pktDet_Tresholds_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register16"
	  Ports			  [2, 1]
	  Position		  [615, 1712, 675, 1768]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action0_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action0_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register17"
	  Ports			  [2, 1]
	  Position		  [615, 1802, 675, 1858]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action1_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action1_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register18"
	  Ports			  [2, 1]
	  Position		  [615, 1887, 675, 1943]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action2_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action2_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register19"
	  Ports			  [2, 1]
	  Position		  [615, 1972, 675, 2028]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action3_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action3_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register2"
	  Ports			  [2, 1]
	  Position		  [615, 502, 675, 558]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_ChanEst_MinMag_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_ChanEst_MinMag_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register20"
	  Ports			  [2, 1]
	  Position		  [615, 2062, 675, 2118]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action4_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action4_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register21"
	  Ports			  [2, 1]
	  Position		  [615, 2147, 675, 2203]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Action5_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Action5_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register22"
	  Ports			  [2, 1]
	  Position		  [615, 2232, 675, 2288]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match0_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match0_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register23"
	  Ports			  [2, 1]
	  Position		  [615, 2322, 675, 2378]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match1_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match1_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register24"
	  Ports			  [2, 1]
	  Position		  [615, 2407, 675, 2463]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match2_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match2_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register25"
	  Ports			  [2, 1]
	  Position		  [615, 2492, 675, 2548]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match3_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match3_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register26"
	  Ports			  [2, 1]
	  Position		  [615, 2582, 675, 2638]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match4_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match4_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register27"
	  Ports			  [2, 1]
	  Position		  [615, 2667, 675, 2723]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match5_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match5_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register28"
	  Ports			  [2, 1]
	  Position		  [615, 2752, 675, 2808]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match6_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match6_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register29"
	  Ports			  [2, 1]
	  Position		  [615, 2842, 675, 2898]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_AutoReply_Match7_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_AutoReply_Match7_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register3"
	  Ports			  [2, 1]
	  Position		  [615, 587, 675, 643]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_Constellation_Scaling_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_Constellation_Scaling_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register30"
	  Ports			  [2, 1]
	  Position		  [615, 2927, 675, 2983]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_FFT_Scaling_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "12"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_FFT_Scaling_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register31"
	  Ports			  [2, 1]
	  Position		  [615, 3012, 675, 3068]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_Interrupt_PktBuf_Ctrl_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_Interrupt_PktBuf_Ctrl_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register32"
	  Ports			  [2, 1]
	  Position		  [615, 3102, 675, 3158]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_Pilots_Index_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_Pilots_Index_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register33"
	  Ports			  [2, 1]
	  Position		  [615, 3187, 675, 3243]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'TxRx_Pilots_Values_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "TxRx_Pilots_Values_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register34"
	  Ports			  [2, 1]
	  Position		  [615, 3272, 675, 3328]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_ControlBits_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_ControlBits_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register35"
	  Ports			  [2, 1]
	  Position		  [615, 3362, 675, 3418]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_Delays_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_Delays_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register36"
	  Ports			  [2, 1]
	  Position		  [615, 3447, 675, 3503]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_OFDM_SymCounts_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_OFDM_SymCounts_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register37"
	  Ports			  [2, 1]
	  Position		  [615, 3532, 675, 3588]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_Scaling_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_Scaling_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register38"
	  Ports			  [2, 1]
	  Position		  [615, 3622, 675, 3678]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Tx_Start_Reset_Control_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Tx_Start_Reset_Control_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register39"
	  Ports			  [2, 1]
	  Position		  [615, 3707, 675, 3763]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'pktDet_controlBits_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "pktDet_controlBits_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register4"
	  Ports			  [2, 1]
	  Position		  [615, 672, 675, 728]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_ControlBits_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_ControlBits_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register40"
	  Ports			  [2, 1]
	  Position		  [615, 3792, 675, 3848]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'pktDet_durations_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "pktDet_durations_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register41"
	  Ports			  [2, 1]
	  Position		  [615, 3882, 675, 3938]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'pktDet_thresholds_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "pktDet_thresholds_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register5"
	  Ports			  [2, 1]
	  Position		  [615, 762, 675, 818]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_FixedPktLen_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_FixedPktLen_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register6"
	  Ports			  [2, 1]
	  Position		  [615, 847, 675, 903]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_OFDM_SymbolCounts_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_OFDM_SymbolCounts_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register7"
	  Ports			  [2, 1]
	  Position		  [615, 932, 675, 988]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_PilotCalcParams_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_PilotCalcParams_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register8"
	  Ports			  [2, 1]
	  Position		  [615, 1022, 675, 1078]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_PktDet_Delay_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_PktDet_Delay_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register9"
	  Ports			  [2, 1]
	  Position		  [615, 1107, 675, 1163]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Rx_PktDet_LongCorr_Params_w'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Rx_PktDet_LongCorr_Params_w_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "plb_decode"
	  Ports			  [7, 9]
	  Position		  [205, 294, 375, 706]
	  SourceBlock		  "xbsIndex_r4/MCode"
	  SourceType		  "Xilinx MCode Block Block"
	  infoedit		  "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of the block are input arguments of the function. The output ports of the block are output arguments of the function."
	  mfname		  "xlmax"
	  explicit_period	  "off"
	  period		  "1"
	  dbl_ovrd		  "off"
	  enable_stdout		  "off"
	  enable_debug		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  mfilecontent		  "function [wrDBusReg, addrAck, rdComp, wrDAck, bankAddr, RNWReg, rdDAck, rdDBus, linearAddr] = ...\n    plb_bus_decode(plbRst, plbABus, plbPAValid, plbRNW, plbWrDBus, rdData, addrPref)\n\n% constant variables (TODO: should pass from outside)\nADDRPREF_LEN = 16;\nBANKADDR_LEN = 2;\nLINEARADDR_LEN = 12;\nABUS_LEN = 32;\nDBUS_LEN = 32;\n\n% declare and initialize persistent variables\n% register input bus signals\npersistent plbRstReg_, plbRstReg_ = xl_state(0, {xlBoolean});\npersistent plbABusReg_, plbABusReg_ = xl_state(0, {xlUnsigned, ABUS_LEN, 0});\npersistent plbPAValidReg_, plbPAValidReg_ = xl_state(0, {xlBoolean});\npersistent plbRNWReg_, plbRNWReg_ = xl_state(0, {xlUnsigned, 1, 0});\npersistent plbWrDBusReg_, plbWrDBusReg_ = xl_state(0, {xlUnsigned, DBUS_LEN, 0});\n\n% ===== rest of the outputs =====\n\nbankAddr   = xl_slice(plbABusReg_, 2+BANKADDR_LEN+LINEARADDR_LEN-1, 2+LINEARADDR_LEN);\nlinearAddr = xl_slice(plbABusReg_, 2+LINEARADDR_LEN-1, 2);\nRNWReg = plbRNWReg_;\nwrDBusReg = plbWrDBusReg_;\n\n% ===== p_select =====\n\n% register PAValid\npersistent aValidReg, aValidReg = xl_state(0, {xlBoolean});\naValidReg = plbPAValidReg_;\n\n% extract and register the address prefix\naddrPref_in = xl_slice(plbABusReg_, xl_nbits(plbABusReg_)-1, xl_nbits(plbABusReg_)-ADDRPREF_LEN);\nif addrPref_in == addrPref\n    ps1 = true;\nelse \n    ps1 = false;\nend \n\npersistent ps1Reg, ps1Reg = xl_state(0, ps1);\nps1Reg = ps1;\n\nps = xl_and(ps1Reg, aValidReg);\n\n% ===== addrAck =====\n\n% register ps\npersistent psReg, psReg = xl_state(0, ps);\n\naddrAck = xfix({xlUnsigned, 1, 0}, xl_and(xl_not(plbRstReg_), ps, xl_not(psReg)));\n\npsReg = ps;\n\n% ===== rdComp, rd/wr DAck =====\n \nrdComp1 = xfix({xlUnsigned, 1, 0}, xl_and(addrAck, RNWReg));\n\nNUM_rdCompDelay = 3;\npersistent rdCompDelay, rdCompDelay = xl_state(zeros(1, NUM_rdCompDelay), rdComp1, NUM_rdCompDelay);\nrdComp2 = rdCompDelay.back;\nrdCompDelay.push_front_pop_back(rdComp1);\n\npersistent rdCompReg, rdCompReg = xl_state(0, rdComp1);\nrdComp = rdCompReg;\nrdCompReg = rdComp2;\n\npersistent rdDAckReg, rdDAckReg = xl_state(0, rdComp1);\nrdDAck = rdDAckReg;\nrdDAckReg = rdComp;\n\npersistent wrDAckReg, wrDAckReg = xl_state(0, addrAck);\nwrDAck = wrDAckReg;\nwrDAckReg = xl_and(addrAck, xl_not(RNWReg));\n\n% ===== rdDBus =====\n\nrdSel = xl_or(rdComp2, rdComp);\n\nif rdSel == 1\n    rdDBus1 = rdData;\nelse\n    rdDBus1 = 0;\nend % if\n\npersistent rdDBusReg, rdDBusReg = xl_state(0, rdDBus1);\nrdDBus = rdDBusReg;\nrdDBusReg = rdDBus1;\n\n% rdDBus = xl_concat(rdDBus32, rdDBus32);\n% rdDBus = rdDBus32;\n\n% ===== update the persistent variables =====\n\nplbRstReg_ = plbRst;\nplbABusReg_ = plbABus;\nplbPAValidReg_ = plbPAValid;\nplbRNWReg_ = plbRNW;\nplbWrDBusReg_ = xl_slice(plbWrDBus, DBUS_LEN-1, 0);\n"
	  suppress_output	  "1"
	  defparams		  "{}"
	  hide_port_list	  "{}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mcode"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "170,412,1,1,white,blue,0,8b15b975,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 ],[0 0 412 412 ],[0.77 0.82 0.91]);\npatch([40 12 52 12 40 85 97 109 157 119 83 57 97 57 83 119 157 109 97 85 40 ],[139 167 207 247 275 275 263 275 275 237 273 247 207 167 141 177 139 139 151 139 139 ],[0.98 0.96 0.92]);\nplot([0 170 170 0 0 ],[0 0 412 412 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'plbRst');\ncolor('black');port_label('input',2,'plbABus');\ncolor('black');port_label('input',3,'plbPAValid');\ncolor('black');port_label('input',4,'plbRNW');\ncolor('black');port_label('input',5,'plbWrDBus');\ncolor('black');port_label('input',6,'rdData');\ncolor('black');port_label('input',7,'addrPref');\ncolor('black');port_label('output',1,'wrDBusReg');\ncolor('black');port_label('output',2,'addrAck');\ncolor('black');port_label('output',3,'rdComp');\ncolor('black');port_label('output',4,'wrDAck');\ncolor('black');port_label('output',5,'bankAddr');\ncolor('black');port_label('output',6,'RNWReg');\ncolor('black');port_label('output',7,'rdDAck');\ncolor('black');port_label('output',8,'rdDBus');\ncolor('black');port_label('output',9,'linearAddr');\ncolor('black');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "wrDBusReg"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    2
	    Name		    "Sl_addrAck"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    3
	    Name		    "Sl_rdComp"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    4
	    Name		    "Sl_wrDAck"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    5
	    Name		    "bankAddr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    6
	    Name		    "RNWReg"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    7
	    Name		    "Sl_rdDAck"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    8
	    Name		    "Sl_rdDBus"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    9
	    Name		    "linearAddr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "plb_memmap"
	  Ports			  [49, 106]
	  Position		  [405, 2344, 575, 2871]
	  SourceBlock		  "xbsIndex_r4/MCode"
	  SourceType		  "Xilinx MCode Block Block"
	  infoedit		  "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of the block are input arguments of the function. The output ports of the block are output arguments of the function."
	  mfname		  "xlmax"
	  explicit_period	  "off"
	  period		  "1"
	  dbl_ovrd		  "off"
	  enable_stdout		  "off"
	  enable_debug		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  mfilecontent		  "function [read_bank_out, sm_Rx_AF_Blanking_w_din, sm_Rx_AF_Blanking_w_en, sm_Rx_AF_TxScaling_w_din, sm_Rx_AF_TxScaling_w_en, sm_Rx_ChanEst_MinMag_w_din, sm_Rx_ChanEst_MinMag_w_en, sm_Rx_Constellation_Scaling_w_din, sm_Rx_Constellation_Scaling_w_en, sm_Rx_ControlBits_w_din, sm_Rx_ControlBits_w_en, sm_Rx_FixedPktLen_w_din, sm_Rx_FixedPktLen_w_en, sm_Rx_OFDM_SymbolCounts_w_din, sm_Rx_OFDM_SymbolCounts_w_en, sm_Rx_PilotCalcParams_w_din, sm_Rx_PilotCalcParams_w_en, sm_Rx_PktDet_Delay_w_din, sm_Rx_PktDet_Delay_w_en, sm_Rx_PktDet_LongCorr_Params_w_din, sm_Rx_PktDet_LongCorr_Params_w_en, sm_Rx_PktDet_LongCorr_Thresholds_w_din, sm_Rx_PktDet_LongCorr_Thresholds_w_en, sm_Rx_PreCFO_Options_w_din, sm_Rx_PreCFO_Options_w_en, sm_Rx_PreCFO_PilotCalcCorrection_w_din, sm_Rx_PreCFO_PilotCalcCorrection_w_en, sm_Rx_coarseCFO_correction_w_din, sm_Rx_coarseCFO_correction_w_en, sm_Rx_pktByteNums_w_din, sm_Rx_pktByteNums_w_en, sm_Rx_pktDet_Tresholds_w_din, sm_Rx_pktDet_Tresholds_w_en, sm_TxRx_AutoReply_Action0_w_din, sm_TxRx_AutoReply_Action0_w_en, sm_TxRx_AutoReply_Action1_w_din, sm_TxRx_AutoReply_Action1_w_en, sm_TxRx_AutoReply_Action2_w_din, sm_TxRx_AutoReply_Action2_w_en, sm_TxRx_AutoReply_Action3_w_din, sm_TxRx_AutoReply_Action3_w_en, sm_TxRx_AutoReply_Action4_w_din, sm_TxRx_AutoReply_Action4_w_en, sm_TxRx_AutoReply_Action5_w_din, sm_TxRx_AutoReply_Action5_w_en, sm_TxRx_AutoReply_Match0_w_din, sm_TxRx_AutoReply_Match0_w_en, sm_TxRx_AutoReply_Match1_w_din, sm_TxRx_AutoReply_Match1_w_en, sm_TxRx_AutoReply_Match2_w_din, sm_TxRx_AutoReply_Match2_w_en, sm_TxRx_AutoReply_Match3_w_din, sm_TxRx_AutoReply_Match3_w_en, sm_TxRx_AutoReply_Match4_w_din, sm_TxRx_AutoReply_Match4_w_en, sm_TxRx_AutoReply_Match5_w_din, sm_TxRx_AutoReply_Match5_w_en, sm_TxRx_AutoReply_Match6_w_din, sm_TxRx_AutoReply_Match6_w_en, sm_TxRx_AutoReply_Match7_w_din, sm_TxRx_AutoReply_Match7_w_en, sm_TxRx_FFT_Scaling_w_din, sm_TxRx_FFT_Scaling_w_en, sm_TxRx_Interrupt_PktBuf_Ctrl_w_din, sm_TxRx_Interrupt_PktBuf_Ctrl_w_en, sm_TxRx_Pilots_Index_w_din, sm_TxRx_Pilots_Index_w_en, sm_TxRx_Pilots_Values_w_din, sm_TxRx_Pilots_Values_w_en, sm_Tx_ControlBits_w_din, sm_Tx_ControlBits_w_en, sm_Tx_Delays_w_din, sm_Tx_Delays_w_en, sm_Tx_OFDM_SymCounts_w_din, sm_Tx_OFDM_SymCounts_w_en, sm_Tx_Scaling_w_din, sm_Tx_Scaling_w_en, sm_Tx_Start_Reset_Control_w_din, sm_Tx_Start_Reset_Control_w_en, sm_pktDet_controlBits_w_din, sm_pktDet_controlBits_w_en, sm_pktDet_durations_w_din, sm_pktDet_durations_w_en, sm_pktDet_thresholds_w_din, sm_pktDet_thresholds_w_en, sm_ChannelEstimates_addr, sm_ChannelEstimates_din, sm_ChannelEstimates_we, sm_EVM_perSC_addr, sm_EVM_perSC_din, sm_EVM_perSC_we, sm_EVM_perSym_addr, sm_EVM_perSym_din, sm_EVM_perSym_we, sm_PktBufFreqOffsets_addr, sm_PktBufFreqOffsets_din, sm_PktBufFreqOffsets_we, sm_RxModulation_addr, sm_RxModulation_din, sm_RxModulation_we, sm_TxHeaderTranslate_addr, sm_TxHeaderTranslate_din, sm_TxHeaderTranslate_we, sm_TxModulation_addr, sm_TxModulation_din, sm_TxModulation_we] = plb_memmap(wrDBus, bankAddr, linearAddr, RNWReg, addrAck, sm_Rx_BER_Errors, sm_Rx_BER_TotalBits, sm_Rx_ControlBits_r, sm_Rx_Gains, sm_Rx_OFDM_SymbolCounts_r, sm_Rx_PktDet_Delay_r, sm_Rx_PktDet_LongCorr_Params_r, sm_Rx_coarseCFOest, sm_Rx_pilotCFOest, sm_Rx_pktByteNums_r, sm_Rx_pktDetEventCount, sm_Rx_pktDone_interruptStatus, sm_TxRx_AutoReply_Action0_r, sm_TxRx_AutoReply_Action1_r, sm_TxRx_AutoReply_Action2_r, sm_TxRx_AutoReply_Action3_r, sm_TxRx_AutoReply_Action4_r, sm_TxRx_AutoReply_Action5_r, sm_TxRx_AutoReply_Match0_r, sm_TxRx_AutoReply_Match1_r, sm_TxRx_AutoReply_Match2_r, sm_TxRx_AutoReply_Match3_r, sm_TxRx_AutoReply_Match4_r, sm_TxRx_AutoReply_Match5_r, sm_TxRx_AutoReply_Match6_r, sm_TxRx_AutoReply_Match7_r, sm_TxRx_Interrupt_PktBuf_Ctrl_r, sm_Tx_ControlBits_r, sm_Tx_Delays_r, sm_Tx_OFDM_SymCounts_r, sm_Tx_PktRunning, sm_Tx_Start_Reset_Control_r, sm_midPacketRSSI, sm_pktDet_controlBits_r, sm_pktDet_durations_r, sm_pktDet_status, sm_pktDet_thresholds_r, sm_ChannelEstimates, sm_EVM_perSC, sm_EVM_perSym, sm_PktBufFreqOffsets, sm_RxModulation, sm_TxHeaderTranslate, sm_TxModulation)\n\n\n% connvert the input data to UFix_32_0 (the bus data type)\n% 'From Register' blocks\n% sm_Rx_BER_Errors_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_BER_Errors_bus = xl_force(sm_Rx_BER_Errors, xlUnsigned, 0);\n\n% sm_Rx_BER_TotalBits_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_BER_TotalBits_bus = xl_force(sm_Rx_BER_TotalBits, xlUnsigned, 0);\n\n% sm_Rx_ControlBits_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_ControlBits_r_bus = xl_force(sm_Rx_ControlBits_r, xlUnsigned, 0);\n\n% sm_Rx_Gains_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_Gains_bus = xl_force(sm_Rx_Gains, xlUnsigned, 0);\n\n% sm_Rx_OFDM_SymbolCounts_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_OFDM_SymbolCounts_r_bus = xl_force(sm_Rx_OFDM_SymbolCounts_r, xlUnsigned, 0);\n\n% sm_Rx_PktDet_Delay_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_PktDet_Delay_r_bus = xl_force(sm_Rx_PktDet_Delay_r, xlUnsigned, 0);\n\n% sm_Rx_PktDet_LongCorr_Params_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_PktDet_LongCorr_Params_r_bus = xl_force(sm_Rx_PktDet_LongCorr_Params_r, xlUnsigned, 0);\n\n% sm_Rx_coarseCFOest_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_coarseCFOest_bus = xl_force(sm_Rx_coarseCFOest, xlUnsigned, 0);\n\n% sm_Rx_pilotCFOest_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_pilotCFOest_bus = xl_force(sm_Rx_pilotCFOest, xlUnsigned, 0);\n\n% sm_Rx_pktByteNums_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_pktByteNums_r_bus = xl_force(sm_Rx_pktByteNums_r, xlUnsigned, 0);\n\n% sm_Rx_pktDetEventCount_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_pktDetEventCount_bus = xl_force(sm_Rx_pktDetEventCount, xlUnsigned, 0);\n\n% sm_Rx_pktDone_interruptStatus_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Rx_pktDone_interruptStatus_bus = xl_force(sm_Rx_pktDone_interruptStatus, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Action0_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Action0_r_bus = xl_force(sm_TxRx_AutoReply_Action0_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Action1_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Action1_r_bus = xl_force(sm_TxRx_AutoReply_Action1_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Action2_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Action2_r_bus = xl_force(sm_TxRx_AutoReply_Action2_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Action3_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Action3_r_bus = xl_force(sm_TxRx_AutoReply_Action3_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Action4_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Action4_r_bus = xl_force(sm_TxRx_AutoReply_Action4_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Action5_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Action5_r_bus = xl_force(sm_TxRx_AutoReply_Action5_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Match0_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Match0_r_bus = xl_force(sm_TxRx_AutoReply_Match0_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Match1_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Match1_r_bus = xl_force(sm_TxRx_AutoReply_Match1_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Match2_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Match2_r_bus = xl_force(sm_TxRx_AutoReply_Match2_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Match3_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Match3_r_bus = xl_force(sm_TxRx_AutoReply_Match3_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Match4_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Match4_r_bus = xl_force(sm_TxRx_AutoReply_Match4_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Match5_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Match5_r_bus = xl_force(sm_TxRx_AutoReply_Match5_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Match6_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Match6_r_bus = xl_force(sm_TxRx_AutoReply_Match6_r, xlUnsigned, 0);\n\n% sm_TxRx_AutoReply_Match7_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_AutoReply_Match7_r_bus = xl_force(sm_TxRx_AutoReply_Match7_r, xlUnsigned, 0);\n\n% sm_TxRx_Interrupt_PktBuf_Ctrl_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxRx_Interrupt_PktBuf_Ctrl_r_bus = xl_force(sm_TxRx_Interrupt_PktBuf_Ctrl_r, xlUnsigned, 0);\n\n% sm_Tx_ControlBits_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Tx_ControlBits_r_bus = xl_force(sm_Tx_ControlBits_r, xlUnsigned, 0);\n\n% sm_Tx_Delays_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Tx_Delays_r_bus = xl_force(sm_Tx_Delays_r, xlUnsigned, 0);\n\n% sm_Tx_OFDM_SymCounts_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Tx_OFDM_SymCounts_r_bus = xl_force(sm_Tx_OFDM_SymCounts_r, xlUnsigned, 0);\n\n% sm_Tx_PktRunning_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Tx_PktRunning_bus = xl_force(sm_Tx_PktRunning, xlUnsigned, 0);\n\n% sm_Tx_Start_Reset_Control_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Tx_Start_Reset_Control_r_bus = xl_force(sm_Tx_Start_Reset_Control_r, xlUnsigned, 0);\n\n% sm_midPacketRSSI_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_midPacketRSSI_bus = xl_force(sm_midPacketRSSI, xlUnsigned, 0);\n\n% sm_pktDet_controlBits_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_pktDet_controlBits_r_bus = xl_force(sm_pktDet_controlBits_r, xlUnsigned, 0);\n\n% sm_pktDet_durations_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_pktDet_durations_r_bus = xl_force(sm_pktDet_durations_r, xlUnsigned, 0);\n\n% sm_pktDet_status_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_pktDet_status_bus = xl_force(sm_pktDet_status, xlUnsigned, 0);\n\n% sm_pktDet_thresholds_r_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_pktDet_thresholds_r_bus = xl_force(sm_pktDet_thresholds_r, xlUnsigned, 0);\n\n% 'To Register' blocks\n\n% 'From FIFO' blocks\n% 'To FIFO' blocks\n% 'Shared Memory' blocks\n% ChannelEstimates_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_ChannelEstimates_bus = xl_force(sm_ChannelEstimates, xlUnsigned, 0);\n\n% EVM_perSC_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_EVM_perSC_bus = xl_force(sm_EVM_perSC, xlUnsigned, 0);\n\n% EVM_perSym_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_EVM_perSym_bus = xl_force(sm_EVM_perSym, xlUnsigned, 0);\n\n% PktBufFreqOffsets_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_PktBufFreqOffsets_bus = xl_force(sm_PktBufFreqOffsets, xlUnsigned, 0);\n\n% RxModulation_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RxModulation_bus = xl_force(sm_RxModulation, xlUnsigned, 0);\n\n% TxHeaderTranslate_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxHeaderTranslate_bus = xl_force(sm_TxHeaderTranslate, xlUnsigned, 0);\n\n% TxModulation_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxModulation_bus = xl_force(sm_TxModulation, xlUnsigned, 0);\n\n\n% 'dout' ports of 'From Register' blocks\n\n% registered register mux output\npersistent reg_bank_out_reg; reg_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nreg_bank_out = reg_bank_out_reg;\n\nif linearAddr == 0\n    reg_bank_out_reg = sm_Rx_BER_Errors_bus;\nelseif linearAddr == 1\n    reg_bank_out_reg = sm_Rx_BER_TotalBits_bus;\nelseif linearAddr == 2\n    reg_bank_out_reg = sm_Rx_ControlBits_r_bus;\nelseif linearAddr == 3\n    reg_bank_out_reg = sm_Rx_Gains_bus;\nelseif linearAddr == 4\n    reg_bank_out_reg = sm_Rx_OFDM_SymbolCounts_r_bus;\nelseif linearAddr == 5\n    reg_bank_out_reg = sm_Rx_PktDet_Delay_r_bus;\nelseif linearAddr == 6\n    reg_bank_out_reg = sm_Rx_PktDet_LongCorr_Params_r_bus;\nelseif linearAddr == 7\n    reg_bank_out_reg = sm_Rx_coarseCFOest_bus;\nelseif linearAddr == 8\n    reg_bank_out_reg = sm_Rx_pilotCFOest_bus;\nelseif linearAddr == 9\n    reg_bank_out_reg = sm_Rx_pktByteNums_r_bus;\nelseif linearAddr == 10\n    reg_bank_out_reg = sm_Rx_pktDetEventCount_bus;\nelseif linearAddr == 11\n    reg_bank_out_reg = sm_Rx_pktDone_interruptStatus_bus;\nelseif linearAddr == 12\n    reg_bank_out_reg = sm_TxRx_AutoReply_Action0_r_bus;\nelseif linearAddr == 13\n    reg_bank_out_reg = sm_TxRx_AutoReply_Action1_r_bus;\nelseif linearAddr == 14\n    reg_bank_out_reg = sm_TxRx_AutoReply_Action2_r_bus;\nelseif linearAddr == 15\n    reg_bank_out_reg = sm_TxRx_AutoReply_Action3_r_bus;\nelseif linearAddr == 16\n    reg_bank_out_reg = sm_TxRx_AutoReply_Action4_r_bus;\nelseif linearAddr == 17\n    reg_bank_out_reg = sm_TxRx_AutoReply_Action5_r_bus;\nelseif linearAddr == 18\n    reg_bank_out_reg = sm_TxRx_AutoReply_Match0_r_bus;\nelseif linearAddr == 19\n    reg_bank_out_reg = sm_TxRx_AutoReply_Match1_r_bus;\nelseif linearAddr == 20\n    reg_bank_out_reg = sm_TxRx_AutoReply_Match2_r_bus;\nelseif linearAddr == 21\n    reg_bank_out_reg = sm_TxRx_AutoReply_Match3_r_bus;\nelseif linearAddr == 22\n    reg_bank_out_reg = sm_TxRx_AutoReply_Match4_r_bus;\nelseif linearAddr == 23\n    reg_bank_out_reg = sm_TxRx_AutoReply_Match5_r_bus;\nelseif linearAddr == 24\n    reg_bank_out_reg = sm_TxRx_AutoReply_Match6_r_bus;\nelseif linearAddr == 25\n    reg_bank_out_reg = sm_TxRx_AutoReply_Match7_r_bus;\nelseif linearAddr == 26\n    reg_bank_out_reg = sm_TxRx_Interrupt_PktBuf_Ctrl_r_bus;\nelseif linearAddr == 27\n    reg_bank_out_reg = sm_Tx_ControlBits_r_bus;\nelseif linearAddr == 28\n    reg_bank_out_reg = sm_Tx_Delays_r_bus;\nelseif linearAddr == 29\n    reg_bank_out_reg = sm_Tx_OFDM_SymCounts_r_bus;\nelseif linearAddr == 30\n    reg_bank_out_reg = sm_Tx_PktRunning_bus;\nelseif linearAddr == 31\n    reg_bank_out_reg = sm_Tx_Start_Reset_Control_r_bus;\nelseif linearAddr == 32\n    reg_bank_out_reg = sm_midPacketRSSI_bus;\nelseif linearAddr == 33\n    reg_bank_out_reg = sm_pktDet_controlBits_r_bus;\nelseif linearAddr == 34\n    reg_bank_out_reg = sm_pktDet_durations_r_bus;\nelseif linearAddr == 35\n    reg_bank_out_reg = sm_pktDet_status_bus;\nelseif linearAddr == 36\n    reg_bank_out_reg = sm_pktDet_thresholds_r_bus;\n\nend\n\n\n% 'From FIFO' and 'To FIFO' blocks\n\n\n\n\n\nopCode = xl_concat(addrAck, RNWReg, bankAddr, linearAddr);\n\n% 'Shared Memory' blocks\n\nsm_ChannelEstimates_sel_value = xl_concat(xl_slice(linearAddr, ...\n                                        xl_nbits(linearAddr) - 1, ...\n                                        8) ...\n                                    );\nif sm_ChannelEstimates_sel_value == xfix({xlUnsigned, ...\n                                        xl_nbits(linearAddr) - 8, ...\n                                        0}, ...\n                                        4);\n    sm_ChannelEstimates_sel = true;\nelse\n    sm_ChannelEstimates_sel = false;\nend\nsm_EVM_perSC_sel_value = xl_concat(xl_slice(linearAddr, ...\n                                        xl_nbits(linearAddr) - 1, ...\n                                        6) ...\n                                    );\nif sm_EVM_perSC_sel_value == xfix({xlUnsigned, ...\n                                        xl_nbits(linearAddr) - 6, ...\n                                        0}, ...\n                                        32);\n    sm_EVM_perSC_sel = true;\nelse\n    sm_EVM_perSC_sel = false;\nend\nsm_EVM_perSym_sel_value = xl_concat(xl_slice(linearAddr, ...\n                                        xl_nbits(linearAddr) - 1, ...\n                                        8) ...\n                                    );\nif sm_EVM_perSym_sel_value == xfix({xlUnsigned, ...\n                                        xl_nbits(linearAddr) - 8, ...\n                                        0}, ...\n                                        5);\n    sm_EVM_perSym_sel = true;\nelse\n    sm_EVM_perSym_sel = false;\nend\nsm_PktBufFreqOffsets_sel_value = xl_concat(xl_slice(linearAddr, ...\n                                        xl_nbits(linearAddr) - 1, ...\n                                        5) ...\n                                    );\nif sm_PktBufFreqOffsets_sel_value == xfix({xlUnsigned, ...\n                                        xl_nbits(linearAddr) - 5, ...\n                                        0}, ...\n                                        66);\n    sm_PktBufFreqOffsets_sel = true;\nelse\n    sm_PktBufFreqOffsets_sel = false;\nend\nsm_RxModulation_sel_value = xl_concat(xl_slice(linearAddr, ...\n                                        xl_nbits(linearAddr) - 1, ...\n                                        8) ...\n                                    );\nif sm_RxModulation_sel_value == xfix({xlUnsigned, ...\n                                        xl_nbits(linearAddr) - 8, ...\n                                        0}, ...\n                                        6);\n    sm_RxModulation_sel = true;\nelse\n    sm_RxModulation_sel = false;\nend\nsm_TxHeaderTranslate_sel_value = xl_concat(xl_slice(linearAddr, ...\n                                        xl_nbits(linearAddr) - 1, ...\n                                        10) ...\n                                    );\nif sm_TxHeaderTranslate_sel_value == xfix({xlUnsigned, ...\n                                        xl_nbits(linearAddr) - 10, ...\n                                        0}, ...\n                                        0);\n    sm_TxHeaderTranslate_sel = true;\nelse\n    sm_TxHeaderTranslate_sel = false;\nend\nsm_TxModulation_sel_value = xl_concat(xl_slice(linearAddr, ...\n                                        xl_nbits(linearAddr) - 1, ...\n                                        8) ...\n                                    );\nif sm_TxModulation_sel_value == xfix({xlUnsigned, ...\n                                        xl_nbits(linearAddr) - 8, ...\n                                        0}, ...\n                                        7);\n    sm_TxModulation_sel = true;\nelse\n    sm_TxModulation_sel = false;\nend\n\n\n% registered Shared Memory mux output\npersistent ram_bank_out_reg; ram_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nram_bank_out = ram_bank_out_reg;\nif sm_ChannelEstimates_sel\n    ram_bank_out_reg = sm_ChannelEstimates_bus;\nelseif sm_EVM_perSC_sel\n    ram_bank_out_reg = sm_EVM_perSC_bus;\nelseif sm_EVM_perSym_sel\n    ram_bank_out_reg = sm_EVM_perSym_bus;\nelseif sm_PktBufFreqOffsets_sel\n    ram_bank_out_reg = sm_PktBufFreqOffsets_bus;\nelseif sm_RxModulation_sel\n    ram_bank_out_reg = sm_RxModulation_bus;\nelseif sm_TxHeaderTranslate_sel\n    ram_bank_out_reg = sm_TxHeaderTranslate_bus;\nelseif sm_TxModulation_sel\n    ram_bank_out_reg = sm_TxModulation_bus;\nend\n\n% 'din' ports of 'Shared Memory' blocks\nsm_ChannelEstimates_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_EVM_perSC_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlSigned, ...\n                                 22);\nsm_EVM_perSym_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlSigned, ...\n                                 14);\nsm_PktBufFreqOffsets_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 32);\nsm_RxModulation_din = xl_force(xl_slice(wrDBus, 4 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxHeaderTranslate_din = xl_force(xl_slice(wrDBus, 10 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxModulation_din = xl_force(xl_slice(wrDBus, 4 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\n\n\n% 'we' ports of 'Shared Memory' blocks\npersistent sm_ChannelEstimates_we_reg; sm_ChannelEstimates_we_reg = xl_state(false, {xlBoolean});\nsm_ChannelEstimates_we = sm_ChannelEstimates_we_reg;\nopCode_sm_ChannelEstimates = xl_concat(addrAck, ...\n                                     RNWReg, ...\n                                     bankAddr, ...\n                                     xl_slice(linearAddr, ...\n                                              xl_nbits(linearAddr) - 1, ...\n                                              8) ...\n                                    );\nif opCode_sm_ChannelEstimates == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n                                         xfix({xlUnsigned, ...\n                                               xl_nbits(linearAddr) - 8, ...\n                                               0}, ...\n                                               4) ...\n                                        );\n    sm_ChannelEstimates_we_reg = true;\nelse\n    sm_ChannelEstimates_we_reg = false;\nend\npersistent sm_EVM_perSC_we_reg; sm_EVM_perSC_we_reg = xl_state(false, {xlBoolean});\nsm_EVM_perSC_we = sm_EVM_perSC_we_reg;\nopCode_sm_EVM_perSC = xl_concat(addrAck, ...\n                                     RNWReg, ...\n                                     bankAddr, ...\n                                     xl_slice(linearAddr, ...\n                                              xl_nbits(linearAddr) - 1, ...\n                                              6) ...\n                                    );\nif opCode_sm_EVM_perSC == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n                                         xfix({xlUnsigned, ...\n                                               xl_nbits(linearAddr) - 6, ...\n                                               0}, ...\n                                               32) ...\n                                        );\n    sm_EVM_perSC_we_reg = true;\nelse\n    sm_EVM_perSC_we_reg = false;\nend\npersistent sm_EVM_perSym_we_reg; sm_EVM_perSym_we_reg = xl_state(false, {xlBoolean});\nsm_EVM_perSym_we = sm_EVM_perSym_we_reg;\nopCode_sm_EVM_perSym = xl_concat(addrAck, ...\n                                     RNWReg, ...\n                                     bankAddr, ...\n                                     xl_slice(linearAddr, ...\n                                              xl_nbits(linearAddr) - 1, ...\n                                              8) ...\n                                    );\nif opCode_sm_EVM_perSym == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n                                         xfix({xlUnsigned, ...\n                                               xl_nbits(linearAddr) - 8, ...\n                                               0}, ...\n                                               5) ...\n                                        );\n    sm_EVM_perSym_we_reg = true;\nelse\n    sm_EVM_perSym_we_reg = false;\nend\npersistent sm_PktBufFreqOffsets_we_reg; sm_PktBufFreqOffsets_we_reg = xl_state(false, {xlBoolean});\nsm_PktBufFreqOffsets_we = sm_PktBufFreqOffsets_we_reg;\nopCode_sm_PktBufFreqOffsets = xl_concat(addrAck, ...\n                                     RNWReg, ...\n                                     bankAddr, ...\n                                     xl_slice(linearAddr, ...\n                                              xl_nbits(linearAddr) - 1, ...\n                                              5) ...\n                                    );\nif opCode_sm_PktBufFreqOffsets == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n                                         xfix({xlUnsigned, ...\n                                               xl_nbits(linearAddr) - 5, ...\n                                               0}, ...\n                                               66) ...\n                                        );\n    sm_PktBufFreqOffsets_we_reg = true;\nelse\n    sm_PktBufFreqOffsets_we_reg = false;\nend\npersistent sm_RxModulation_we_reg; sm_RxModulation_we_reg = xl_state(false, {xlBoolean});\nsm_RxModulation_we = sm_RxModulation_we_reg;\nopCode_sm_RxModulation = xl_concat(addrAck, ...\n                                     RNWReg, ...\n                                     bankAddr, ...\n                                     xl_slice(linearAddr, ...\n                                              xl_nbits(linearAddr) - 1, ...\n                                              8) ...\n                                    );\nif opCode_sm_RxModulation == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n                                         xfix({xlUnsigned, ...\n                                               xl_nbits(linearAddr) - 8, ...\n                                               0}, ...\n                                               6) ...\n                                        );\n    sm_RxModulation_we_reg = true;\nelse\n    sm_RxModulation_we_reg = false;\nend\npersistent sm_TxHeaderTranslate_we_reg; sm_TxHeaderTranslate_we_reg = xl_state(false, {xlBoolean});\nsm_TxHeaderTranslate_we = sm_TxHeaderTranslate_we_reg;\nopCode_sm_TxHeaderTranslate = xl_concat(addrAck, ...\n                                     RNWReg, ...\n                                     bankAddr, ...\n                                     xl_slice(linearAddr, ...\n                                              xl_nbits(linearAddr) - 1, ...\n                                              10) ...\n                                    );\nif opCode_sm_TxHeaderTranslate == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n                                         xfix({xlUnsigned, ...\n                                               xl_nbits(linearAddr) - 10, ...\n                                               0}, ...\n                                               0) ...\n                                        );\n    sm_TxHeaderTranslate_we_reg = true;\nelse\n    sm_TxHeaderTranslate_we_reg = false;\nend\npersistent sm_TxModulation_we_reg; sm_TxModulation_we_reg = xl_state(false, {xlBoolean});\nsm_TxModulation_we = sm_TxModulation_we_reg;\nopCode_sm_TxModulation = xl_concat(addrAck, ...\n                                     RNWReg, ...\n                                     bankAddr, ...\n                                     xl_slice(linearAddr, ...\n                                              xl_nbits(linearAddr) - 1, ...\n                                              8) ...\n                                    );\nif opCode_sm_TxModulation == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n                                         xfix({xlUnsigned, ...\n                                               xl_nbits(linearAddr) - 8, ...\n                                               0}, ...\n                                               7) ...\n                                        );\n    sm_TxModulation_we_reg = true;\nelse\n    sm_TxModulation_we_reg = false;\nend\n\n\n% 'addr' ports of 'Shared Memory' blocks\npersistent sm_ChannelEstimates_addr_reg; \nsm_ChannelEstimates_addr_reg = xl_state(0, {xlUnsigned, 8, 0});\nsm_ChannelEstimates_addr = sm_ChannelEstimates_addr_reg;\nif addrAck == 1\n    sm_ChannelEstimates_addr_reg = xl_slice(linearAddr, 8, 0);\nelse\n    sm_ChannelEstimates_addr_reg = sm_ChannelEstimates_addr_reg;\nend\npersistent sm_EVM_perSC_addr_reg; \nsm_EVM_perSC_addr_reg = xl_state(0, {xlUnsigned, 6, 0});\nsm_EVM_perSC_addr = sm_EVM_perSC_addr_reg;\nif addrAck == 1\n    sm_EVM_perSC_addr_reg = xl_slice(linearAddr, 6, 0);\nelse\n    sm_EVM_perSC_addr_reg = sm_EVM_perSC_addr_reg;\nend\npersistent sm_EVM_perSym_addr_reg; \nsm_EVM_perSym_addr_reg = xl_state(0, {xlUnsigned, 8, 0});\nsm_EVM_perSym_addr = sm_EVM_perSym_addr_reg;\nif addrAck == 1\n    sm_EVM_perSym_addr_reg = xl_slice(linearAddr, 8, 0);\nelse\n    sm_EVM_perSym_addr_reg = sm_EVM_perSym_addr_reg;\nend\npersistent sm_PktBufFreqOffsets_addr_reg; \nsm_PktBufFreqOffsets_addr_reg = xl_state(0, {xlUnsigned, 5, 0});\nsm_PktBufFreqOffsets_addr = sm_PktBufFreqOffsets_addr_reg;\nif addrAck == 1\n    sm_PktBufFreqOffsets_addr_reg = xl_slice(linearAddr, 5, 0);\nelse\n    sm_PktBufFreqOffsets_addr_reg = sm_PktBufFreqOffsets_addr_reg;\nend\npersistent sm_RxModulation_addr_reg; \nsm_RxModulation_addr_reg = xl_state(0, {xlUnsigned, 8, 0});\nsm_RxModulation_addr = sm_RxModulation_addr_reg;\nif addrAck == 1\n    sm_RxModulation_addr_reg = xl_slice(linearAddr, 8, 0);\nelse\n    sm_RxModulation_addr_reg = sm_RxModulation_addr_reg;\nend\npersistent sm_TxHeaderTranslate_addr_reg; \nsm_TxHeaderTranslate_addr_reg = xl_state(0, {xlUnsigned, 10, 0});\nsm_TxHeaderTranslate_addr = sm_TxHeaderTranslate_addr_reg;\nif addrAck == 1\n    sm_TxHeaderTranslate_addr_reg = xl_slice(linearAddr, 10, 0);\nelse\n    sm_TxHeaderTranslate_addr_reg = sm_TxHeaderTranslate_addr_reg;\nend\npersistent sm_TxModulation_addr_reg; \nsm_TxModulation_addr_reg = xl_state(0, {xlUnsigned, 8, 0});\nsm_TxModulation_addr = sm_TxModulation_addr_reg;\nif addrAck == 1\n    sm_TxModulation_addr_reg = xl_slice(linearAddr, 8, 0);\nelse\n    sm_TxModulation_addr_reg = sm_TxModulation_addr_reg;\nend\n\n\n% 're' ports of 'From FIFO' blocks\n\n\n% 'en' ports of 'To Register' blocks\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 0))\n    sm_Rx_AF_Blanking_w_en = true;\nelse\n    sm_Rx_AF_Blanking_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 1))\n    sm_Rx_AF_TxScaling_w_en = true;\nelse\n    sm_Rx_AF_TxScaling_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 2))\n    sm_Rx_ChanEst_MinMag_w_en = true;\nelse\n    sm_Rx_ChanEst_MinMag_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 3))\n    sm_Rx_Constellation_Scaling_w_en = true;\nelse\n    sm_Rx_Constellation_Scaling_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 4))\n    sm_Rx_ControlBits_w_en = true;\nelse\n    sm_Rx_ControlBits_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 5))\n    sm_Rx_FixedPktLen_w_en = true;\nelse\n    sm_Rx_FixedPktLen_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 6))\n    sm_Rx_OFDM_SymbolCounts_w_en = true;\nelse\n    sm_Rx_OFDM_SymbolCounts_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 7))\n    sm_Rx_PilotCalcParams_w_en = true;\nelse\n    sm_Rx_PilotCalcParams_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 8))\n    sm_Rx_PktDet_Delay_w_en = true;\nelse\n    sm_Rx_PktDet_Delay_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 9))\n    sm_Rx_PktDet_LongCorr_Params_w_en = true;\nelse\n    sm_Rx_PktDet_LongCorr_Params_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 10))\n    sm_Rx_PktDet_LongCorr_Thresholds_w_en = true;\nelse\n    sm_Rx_PktDet_LongCorr_Thresholds_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 11))\n    sm_Rx_PreCFO_Options_w_en = true;\nelse\n    sm_Rx_PreCFO_Options_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 12))\n    sm_Rx_PreCFO_PilotCalcCorrection_w_en = true;\nelse\n    sm_Rx_PreCFO_PilotCalcCorrection_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 13))\n    sm_Rx_coarseCFO_correction_w_en = true;\nelse\n    sm_Rx_coarseCFO_correction_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 14))\n    sm_Rx_pktByteNums_w_en = true;\nelse\n    sm_Rx_pktByteNums_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 15))\n    sm_Rx_pktDet_Tresholds_w_en = true;\nelse\n    sm_Rx_pktDet_Tresholds_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 16))\n    sm_TxRx_AutoReply_Action0_w_en = true;\nelse\n    sm_TxRx_AutoReply_Action0_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 17))\n    sm_TxRx_AutoReply_Action1_w_en = true;\nelse\n    sm_TxRx_AutoReply_Action1_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 18))\n    sm_TxRx_AutoReply_Action2_w_en = true;\nelse\n    sm_TxRx_AutoReply_Action2_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 19))\n    sm_TxRx_AutoReply_Action3_w_en = true;\nelse\n    sm_TxRx_AutoReply_Action3_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 20))\n    sm_TxRx_AutoReply_Action4_w_en = true;\nelse\n    sm_TxRx_AutoReply_Action4_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 21))\n    sm_TxRx_AutoReply_Action5_w_en = true;\nelse\n    sm_TxRx_AutoReply_Action5_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 22))\n    sm_TxRx_AutoReply_Match0_w_en = true;\nelse\n    sm_TxRx_AutoReply_Match0_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 23))\n    sm_TxRx_AutoReply_Match1_w_en = true;\nelse\n    sm_TxRx_AutoReply_Match1_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 24))\n    sm_TxRx_AutoReply_Match2_w_en = true;\nelse\n    sm_TxRx_AutoReply_Match2_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 25))\n    sm_TxRx_AutoReply_Match3_w_en = true;\nelse\n    sm_TxRx_AutoReply_Match3_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 26))\n    sm_TxRx_AutoReply_Match4_w_en = true;\nelse\n    sm_TxRx_AutoReply_Match4_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 27))\n    sm_TxRx_AutoReply_Match5_w_en = true;\nelse\n    sm_TxRx_AutoReply_Match5_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 28))\n    sm_TxRx_AutoReply_Match6_w_en = true;\nelse\n    sm_TxRx_AutoReply_Match6_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 29))\n    sm_TxRx_AutoReply_Match7_w_en = true;\nelse\n    sm_TxRx_AutoReply_Match7_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 30))\n    sm_TxRx_FFT_Scaling_w_en = true;\nelse\n    sm_TxRx_FFT_Scaling_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 31))\n    sm_TxRx_Interrupt_PktBuf_Ctrl_w_en = true;\nelse\n    sm_TxRx_Interrupt_PktBuf_Ctrl_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 32))\n    sm_TxRx_Pilots_Index_w_en = true;\nelse\n    sm_TxRx_Pilots_Index_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 33))\n    sm_TxRx_Pilots_Values_w_en = true;\nelse\n    sm_TxRx_Pilots_Values_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 34))\n    sm_Tx_ControlBits_w_en = true;\nelse\n    sm_Tx_ControlBits_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 35))\n    sm_Tx_Delays_w_en = true;\nelse\n    sm_Tx_Delays_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 36))\n    sm_Tx_OFDM_SymCounts_w_en = true;\nelse\n    sm_Tx_OFDM_SymCounts_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 37))\n    sm_Tx_Scaling_w_en = true;\nelse\n    sm_Tx_Scaling_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 38))\n    sm_Tx_Start_Reset_Control_w_en = true;\nelse\n    sm_Tx_Start_Reset_Control_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 39))\n    sm_pktDet_controlBits_w_en = true;\nelse\n    sm_pktDet_controlBits_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 40))\n    sm_pktDet_durations_w_en = true;\nelse\n    sm_pktDet_durations_w_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 41))\n    sm_pktDet_thresholds_w_en = true;\nelse\n    sm_pktDet_thresholds_w_en = false;\nend\n\n\n% 'din' ports of 'To FIFO' blocks\n\n\n% 'we' ports of 'To FIFO' blocks\n\n\n% 'din' ports of 'To Register' blocks\nsm_Rx_AF_Blanking_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_AF_TxScaling_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_ChanEst_MinMag_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_Constellation_Scaling_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_ControlBits_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_FixedPktLen_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_OFDM_SymbolCounts_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_PilotCalcParams_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_PktDet_Delay_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_PktDet_LongCorr_Params_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_PktDet_LongCorr_Thresholds_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_PreCFO_Options_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_PreCFO_PilotCalcCorrection_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_coarseCFO_correction_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_pktByteNums_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Rx_pktDet_Tresholds_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Action0_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Action1_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Action2_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Action3_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Action4_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Action5_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Match0_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Match1_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Match2_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Match3_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Match4_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Match5_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Match6_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_AutoReply_Match7_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_FFT_Scaling_w_din = xl_force(xl_slice(wrDBus, 12 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_Interrupt_PktBuf_Ctrl_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_Pilots_Index_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_TxRx_Pilots_Values_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Tx_ControlBits_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Tx_Delays_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Tx_OFDM_SymCounts_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Tx_Scaling_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_Tx_Start_Reset_Control_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_pktDet_controlBits_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_pktDet_durations_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_pktDet_thresholds_w_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\n\n\npersistent read_bank_out_reg; read_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nread_bank_out = read_bank_out_reg;\n\npersistent bankAddr_reg; bankAddr_reg = xl_state(0, bankAddr);\n\nif bankAddr_reg == 0\n    % Bank 0: Shared Memories\n    read_bank_out_reg = ram_bank_out;\nelseif bankAddr_reg == 1\n    % Bank 1: From/To FIFOs\n    read_bank_out_reg =  0;\nelseif bankAddr_reg == 2\n    % Bank 2: From/To Registers\n    read_bank_out_reg = reg_bank_out;\nelseif bankAddr_reg == 3\n    % Bank 3: Configuration Registers\n    read_bank_out_reg = 0;\nend\n\nbankAddr_reg = bankAddr;\n"
	  suppress_output	  "1"
	  defparams		  "{}"
	  hide_port_list	  "{}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mcode"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "170,527,1,1,white,blue,0,ebf7c53a,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 ],[0 0 527 527 ],[0.77 0.82 0.91]);\npatch([40 12 52 12 40 85 97 109 157 119 83 57 97 57 83 119 157 109 97 85 40 ],[197 225 265 305 333 333 321 333 333 295 331 305 265 225 199 235 197 197 209 197 197 ],[0.98 0.96 0.92]);\nplot([0 170 170 0 0 ],[0 0 527 527 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'wrDBus');\ncolor('black');port_label('input',2,'bankAddr');\ncolor('black');port_label('input',3,'linearAddr');\ncolor('black');port_label('input',4,'RNWReg');\ncolor('black');port_label('input',5,'addrAck');\ncolor('black');port_label('input',6,'sm_Rx_BER_Errors');\ncolor('black');port_label('input',7,'sm_Rx_BER_TotalBits');\ncolor('black');port_label('input',8,'sm_Rx_ControlBits_r');\ncolor('black');port_label('input',9,'sm_Rx_Gains');\ncolor('black');port_label('input',10,'sm_Rx_OFDM_SymbolCounts_r');\ncolor('black');port_label('input',11,'sm_Rx_PktDet_Delay_r');\ncolor('black');port_label('input',12,'sm_Rx_PktDet_LongCorr_Params_r');\ncolor('black');port_label('input',13,'sm_Rx_coarseCFOest');\ncolor('black');port_label('input',14,'sm_Rx_pilotCFOest');\ncolor('black');port_label('input',15,'sm_Rx_pktByteNums_r');\ncolor('black');port_label('input',16,'sm_Rx_pktDetEventCount');\ncolor('black');port_label('input',17,'sm_Rx_pktDone_interruptStatus');\ncolor('black');port_label('input',18,'sm_TxRx_AutoReply_Action0_r');\ncolor('black');port_label('input',19,'sm_TxRx_AutoReply_Action1_r');\ncolor('black');port_label('input',20,'sm_TxRx_AutoReply_Action2_r');\ncolor('black');port_label('input',21,'sm_TxRx_AutoReply_Action3_r');\ncolor('black');port_label('input',22,'sm_TxRx_AutoReply_Action4_r');\ncolor('black');port_label('input',23,'sm_TxRx_AutoReply_Action5_r');\ncolor('black');port_label('input',24,'sm_TxRx_AutoReply_Match0_r');\ncolor('black');port_label('input',25,'sm_TxRx_AutoReply_Match1_r');\ncolor('black');port_label('input',26,'sm_TxRx_AutoReply_Match2_r');\ncolor('black');port_label('input',27,'sm_TxRx_AutoReply_Match3_r');\ncolor('black');port_label('input',28,'sm_TxRx_AutoReply_Match4_r');\ncolor('black');port_label('input',29,'sm_TxRx_AutoReply_Match5_r');\ncolor('black');port_label('input',30,'sm_TxRx_AutoReply_Match6_r');\ncolor('black');port_label('input',31,'sm_TxRx_AutoReply_Match7_r');\ncolor('black');port_label('input',32,'sm_TxRx_Interrupt_PktBuf_Ctrl_r');\ncolor('black');port_label('input',33,'sm_Tx_ControlBits_r');\ncolor('black');port_label('input',34,'sm_Tx_Delays_r');\ncolor('black');port_label('input',35,'sm_Tx_OFDM_SymCounts_r');\ncolor('black');port_label('input',36,'sm_Tx_PktRunning');\ncolor('black');port_label('input',37,'sm_Tx_Start_Reset_Control_r');\ncolor('black');port_label('input',38,'sm_midPacketRSSI');\ncolor('black');port_label('input',39,'sm_pktDet_controlBits_r');\ncolor('black');port_label('input',40,'sm_pktDet_durations_r');\ncolor('black');port_label('input',41,'sm_pktDet_status');\ncolor('black');port_label('input',42,'sm_pktDet_thresholds_r');\ncolor('black');port_label('input',43,'sm_ChannelEstimates');\ncolor('black');port_label('input',44,'sm_EVM_perSC');\ncolor('black');port_label('input',45,'sm_EVM_perSym');\ncolor('black');port_label('input',46,'sm_PktBufFreqOffsets');\ncolor('black');port_label('input',47,'sm_RxModulation');\ncolor('black');port_label('input',48,'sm_TxHeaderTranslate');\ncolor('black');port_label('input',49,'sm_TxModulation');\ncolor('black');port_label('output',1,'read_bank_out');\ncolor('black');port_label('output',2,'sm_Rx_AF_Blanking_w_din');\ncolor('black');port_label('output',3,'sm_Rx_AF_Blanking_w_en');\ncolor('black');port_label('output',4,'sm_Rx_AF_TxScaling_w_din');\ncolor('black');port_label('output',5,'sm_Rx_AF_TxScaling_w_en');\ncolor('black');port_label('output',6,'sm_Rx_ChanEst_MinMag_w_din');\ncolor('black');port_label('output',7,'sm_Rx_ChanEst_MinMag_w_en');\ncolor('black');port_label('output',8,'sm_Rx_Constellation_Scaling_w_din');\ncolor('black');port_label('output',9,'sm_Rx_Constellation_Scaling_w_en');\ncolor('black');port_label('output',10,'sm_Rx_ControlBits_w_din');\ncolor('black');port_label('output',11,'sm_Rx_ControlBits_w_en');\ncolor('black');port_label('output',12,'sm_Rx_FixedPktLen_w_din');\ncolor('black');port_label('output',13,'sm_Rx_FixedPktLen_w_en');\ncolor('black');port_label('output',14,'sm_Rx_OFDM_SymbolCounts_w_din');\ncolor('black');port_label('output',15,'sm_Rx_OFDM_SymbolCounts_w_en');\ncolor('black');port_label('output',16,'sm_Rx_PilotCalcParams_w_din');\ncolor('black');port_label('output',17,'sm_Rx_PilotCalcParams_w_en');\ncolor('black');port_label('output',18,'sm_Rx_PktDet_Delay_w_din');\ncolor('black');port_label('output',19,'sm_Rx_PktDet_Delay_w_en');\ncolor('black');port_label('output',20,'sm_Rx_PktDet_LongCorr_Params_w_din');\ncolor('black');port_label('output',21,'sm_Rx_PktDet_LongCorr_Params_w_en');\ncolor('black');port_label('output',22,'sm_Rx_PktDet_LongCorr_Thresholds_w_din');\ncolor('black');port_label('output',23,'sm_Rx_PktDet_LongCorr_Thresholds_w_en');\ncolor('black');port_label('output',24,'sm_Rx_PreCFO_Options_w_din');\ncolor('black');port_label('output',25,'sm_Rx_PreCFO_Options_w_en');\ncolor('black');port_label('output',26,'sm_Rx_PreCFO_PilotCalcCorrection_w_din');\ncolor('black');port_label('output',27,'sm_Rx_PreCFO_PilotCalcCorrection_w_en');\ncolor('black');port_label('output',28,'sm_Rx_coarseCFO_correction_w_din');\ncolor('black');port_label('output',29,'sm_Rx_coarseCFO_correction_w_en');\ncolor('black');port_label('output',30,'sm_Rx_pktByteNums_w_din');\ncolor('black');port_label('output',31,'sm_Rx_pktByteNums_w_en');\ncolor('black');port_label('output',32,'sm_Rx_pktDet_Tresholds_w_din');\ncolor('black');port_label('output',33,'sm_Rx_pktDet_Tresholds_w_en');\ncolor('black');port_label('output',34,'sm_TxRx_AutoReply_Action0_w_din');\ncolor('black');port_label('output',35,'sm_TxRx_AutoReply_Action0_w_en');\ncolor('black');port_label('output',36,'sm_TxRx_AutoReply_Action1_w_din');\ncolor('black');port_label('output',37,'sm_TxRx_AutoReply_Action1_w_en');\ncolor('black');port_label('output',38,'sm_TxRx_AutoReply_Action2_w_din');\ncolor('black');port_label('output',39,'sm_TxRx_AutoReply_Action2_w_en');\ncolor('black');port_label('output',40,'sm_TxRx_AutoReply_Action3_w_din');\ncolor('black');port_label('output',41,'sm_TxRx_AutoReply_Action3_w_en');\ncolor('black');port_label('output',42,'sm_TxRx_AutoReply_Action4_w_din');\ncolor('black');port_label('output',43,'sm_TxRx_AutoReply_Action4_w_en');\ncolor('black');port_label('output',44,'sm_TxRx_AutoReply_Action5_w_din');\ncolor('black');port_label('output',45,'sm_TxRx_AutoReply_Action5_w_en');\ncolor('black');port_label('output',46,'sm_TxRx_AutoReply_Match0_w_din');\ncolor('black');port_label('output',47,'sm_TxRx_AutoReply_Match0_w_en');\ncolor('black');port_label('output',48,'sm_TxRx_AutoReply_Match1_w_din');\ncolor('black');port_label('output',49,'sm_TxRx_AutoReply_Match1_w_en');\ncolor('black');port_label('output',50,'sm_TxRx_AutoReply_Match2_w_din');\ncolor('black');port_label('output',51,'sm_TxRx_AutoReply_Match2_w_en');\ncolor('black');port_label('output',52,'sm_TxRx_AutoReply_Match3_w_din');\ncolor('black');port_label('output',53,'sm_TxRx_AutoReply_Match3_w_en');\ncolor('black');port_label('output',54,'sm_TxRx_AutoReply_Match4_w_din');\ncolor('black');port_label('output',55,'sm_TxRx_AutoReply_Match4_w_en');\ncolor('black');port_label('output',56,'sm_TxRx_AutoReply_Match5_w_din');\ncolor('black');port_label('output',57,'sm_TxRx_AutoReply_Match5_w_en');\ncolor('black');port_label('output',58,'sm_TxRx_AutoReply_Match6_w_din');\ncolor('black');port_label('output',59,'sm_TxRx_AutoReply_Match6_w_en');\ncolor('black');port_label('output',60,'sm_TxRx_AutoReply_Match7_w_din');\ncolor('black');port_label('output',61,'sm_TxRx_AutoReply_Match7_w_en');\ncolor('black');port_label('output',62,'sm_TxRx_FFT_Scaling_w_din');\ncolor('black');port_label('output',63,'sm_TxRx_FFT_Scaling_w_en');\ncolor('black');port_label('output',64,'sm_TxRx_Interrupt_PktBuf_Ctrl_w_din');\ncolor('black');port_label('output',65,'sm_TxRx_Interrupt_PktBuf_Ctrl_w_en');\ncolor('black');port_label('output',66,'sm_TxRx_Pilots_Index_w_din');\ncolor('black');port_label('output',67,'sm_TxRx_Pilots_Index_w_en');\ncolor('black');port_label('output',68,'sm_TxRx_Pilots_Values_w_din');\ncolor('black');port_label('output',69,'sm_TxRx_Pilots_Values_w_en');\ncolor('black');port_label('output',70,'sm_Tx_ControlBits_w_din');\ncolor('black');port_label('output',71,'sm_Tx_ControlBits_w_en');\ncolor('black');port_label('output',72,'sm_Tx_Delays_w_din');\ncolor('black');port_label('output',73,'sm_Tx_Delays_w_en');\ncolor('black');port_label('output',74,'sm_Tx_OFDM_SymCounts_w_din');\ncolor('black');port_label('output',75,'sm_Tx_OFDM_SymCounts_w_en');\ncolor('black');port_label('output',76,'sm_Tx_Scaling_w_din');\ncolor('black');port_label('output',77,'sm_Tx_Scaling_w_en');\ncolor('black');port_label('output',78,'sm_Tx_Start_Reset_Control_w_din');\ncolor('black');port_label('output',79,'sm_Tx_Start_Reset_Control_w_en');\ncolor('black');port_label('output',80,'sm_pktDet_controlBits_w_din');\ncolor('black');port_label('output',81,'sm_pktDet_controlBits_w_en');\ncolor('black');port_label('output',82,'sm_pktDet_durations_w_din');\ncolor('black');port_label('output',83,'sm_pktDet_durations_w_en');\ncolor('black');port_label('output',84,'sm_pktDet_thresholds_w_din');\ncolor('black');port_label('output',85,'sm_pktDet_thresholds_w_en');\ncolor('black');port_label('output',86,'sm_ChannelEstimates_addr');\ncolor('black');port_label('output',87,'sm_ChannelEstimates_din');\ncolor('black');port_label('output',88,'sm_ChannelEstimates_we');\ncolor('black');port_label('output',89,'sm_EVM_perSC_addr');\ncolor('black');port_label('output',90,'sm_EVM_perSC_din');\ncolor('black');port_label('output',91,'sm_EVM_perSC_we');\ncolor('black');port_label('output',92,'sm_EVM_perSym_addr');\ncolor('black');port_label('output',93,'sm_EVM_perSym_din');\ncolor('black');port_label('output',94,'sm_EVM_perSym_we');\ncolor('black');port_label('output',95,'sm_PktBufFreqOffsets_addr');\ncolor('black');port_label('output',96,'sm_PktBufFreqOffsets_din');\ncolor('black');port_label('output',97,'sm_PktBufFreqOffsets_we');\ncolor('black');port_label('output',98,'sm_RxModulation_addr');\ncolor('black');port_label('output',99,'sm_RxModulation_din');\ncolor('black');port_label('output',100,'sm_RxModulation_we');\ncolor('black');port_label('output',101,'sm_TxHeaderTranslate_addr');\ncolor('black');port_label('output',102,'sm_TxHeaderTranslate_din');\ncolor('black');port_label('output',103,'sm_TxHeaderTranslate_we');\ncolor('black');port_label('output',104,'sm_TxModulation_addr');\ncolor('black');port_label('output',105,'sm_TxModulation_din');\ncolor('black');port_label('output',106,'sm_TxModulation_we');\ncolor('black');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "rdData"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    2
	    Name		    "Rx_AF_Blanking_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    3
	    Name		    "Rx_AF_Blanking_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    4
	    Name		    "Rx_AF_TxScaling_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    5
	    Name		    "Rx_AF_TxScaling_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    6
	    Name		    "Rx_ChanEst_MinMag_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    7
	    Name		    "Rx_ChanEst_MinMag_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    8
	    Name		    "Rx_Constellation_Scaling_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    9
	    Name		    "Rx_Constellation_Scaling_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    10
	    Name		    "Rx_ControlBits_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    11
	    Name		    "Rx_ControlBits_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    12
	    Name		    "Rx_FixedPktLen_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    13
	    Name		    "Rx_FixedPktLen_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    14
	    Name		    "Rx_OFDM_SymbolCounts_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    15
	    Name		    "Rx_OFDM_SymbolCounts_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    16
	    Name		    "Rx_PilotCalcParams_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    17
	    Name		    "Rx_PilotCalcParams_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    18
	    Name		    "Rx_PktDet_Delay_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    19
	    Name		    "Rx_PktDet_Delay_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
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	  Port {
	    PortNumber		    20
	    Name		    "Rx_PktDet_LongCorr_Params_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
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	  Port {
	    PortNumber		    21
	    Name		    "Rx_PktDet_LongCorr_Params_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
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	  Port {
	    PortNumber		    22
	    Name		    "Rx_PktDet_LongCorr_Thresholds_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
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	  Port {
	    PortNumber		    23
	    Name		    "Rx_PktDet_LongCorr_Thresholds_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    24
	    Name		    "Rx_PreCFO_Options_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    25
	    Name		    "Rx_PreCFO_Options_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    26
	    Name		    "Rx_PreCFO_PilotCalcCorrection_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    27
	    Name		    "Rx_PreCFO_PilotCalcCorrection_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    28
	    Name		    "Rx_coarseCFO_correction_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    29
	    Name		    "Rx_coarseCFO_correction_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    30
	    Name		    "Rx_pktByteNums_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    31
	    Name		    "Rx_pktByteNums_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    32
	    Name		    "Rx_pktDet_Tresholds_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    33
	    Name		    "Rx_pktDet_Tresholds_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    34
	    Name		    "TxRx_AutoReply_Action0_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
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	  Port {
	    PortNumber		    35
	    Name		    "TxRx_AutoReply_Action0_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
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	  Port {
	    PortNumber		    36
	    Name		    "TxRx_AutoReply_Action1_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
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	  Port {
	    PortNumber		    37
	    Name		    "TxRx_AutoReply_Action1_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    38
	    Name		    "TxRx_AutoReply_Action2_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    39
	    Name		    "TxRx_AutoReply_Action2_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    40
	    Name		    "TxRx_AutoReply_Action3_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
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	  Port {
	    PortNumber		    41
	    Name		    "TxRx_AutoReply_Action3_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    42
	    Name		    "TxRx_AutoReply_Action4_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    43
	    Name		    "TxRx_AutoReply_Action4_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    44
	    Name		    "TxRx_AutoReply_Action5_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    45
	    Name		    "TxRx_AutoReply_Action5_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    46
	    Name		    "TxRx_AutoReply_Match0_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    47
	    Name		    "TxRx_AutoReply_Match0_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    48
	    Name		    "TxRx_AutoReply_Match1_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    49
	    Name		    "TxRx_AutoReply_Match1_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    50
	    Name		    "TxRx_AutoReply_Match2_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    51
	    Name		    "TxRx_AutoReply_Match2_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    52
	    Name		    "TxRx_AutoReply_Match3_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    53
	    Name		    "TxRx_AutoReply_Match3_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    54
	    Name		    "TxRx_AutoReply_Match4_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    55
	    Name		    "TxRx_AutoReply_Match4_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    56
	    Name		    "TxRx_AutoReply_Match5_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    57
	    Name		    "TxRx_AutoReply_Match5_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    58
	    Name		    "TxRx_AutoReply_Match6_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    59
	    Name		    "TxRx_AutoReply_Match6_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    60
	    Name		    "TxRx_AutoReply_Match7_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    61
	    Name		    "TxRx_AutoReply_Match7_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    62
	    Name		    "TxRx_FFT_Scaling_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    63
	    Name		    "TxRx_FFT_Scaling_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    64
	    Name		    "TxRx_Interrupt_PktBuf_Ctrl_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    65
	    Name		    "TxRx_Interrupt_PktBuf_Ctrl_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    66
	    Name		    "TxRx_Pilots_Index_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    67
	    Name		    "TxRx_Pilots_Index_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    68
	    Name		    "TxRx_Pilots_Values_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    69
	    Name		    "TxRx_Pilots_Values_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    70
	    Name		    "Tx_ControlBits_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    71
	    Name		    "Tx_ControlBits_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    72
	    Name		    "Tx_Delays_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    73
	    Name		    "Tx_Delays_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    74
	    Name		    "Tx_OFDM_SymCounts_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    75
	    Name		    "Tx_OFDM_SymCounts_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    76
	    Name		    "Tx_Scaling_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    77
	    Name		    "Tx_Scaling_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    78
	    Name		    "Tx_Start_Reset_Control_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    79
	    Name		    "Tx_Start_Reset_Control_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    80
	    Name		    "pktDet_controlBits_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    81
	    Name		    "pktDet_controlBits_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    82
	    Name		    "pktDet_durations_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    83
	    Name		    "pktDet_durations_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    84
	    Name		    "pktDet_thresholds_w_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    85
	    Name		    "pktDet_thresholds_w_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    86
	    Name		    "ChannelEstimates_addr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    87
	    Name		    "ChannelEstimates_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    88
	    Name		    "ChannelEstimates_we"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    89
	    Name		    "EVM_perSC_addr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    90
	    Name		    "EVM_perSC_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    91
	    Name		    "EVM_perSC_we"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    92
	    Name		    "EVM_perSym_addr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    93
	    Name		    "EVM_perSym_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    94
	    Name		    "EVM_perSym_we"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    95
	    Name		    "PktBufFreqOffsets_addr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    96
	    Name		    "PktBufFreqOffsets_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    97
	    Name		    "PktBufFreqOffsets_we"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    98
	    Name		    "RxModulation_addr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    99
	    Name		    "RxModulation_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    100
	    Name		    "RxModulation_we"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    101
	    Name		    "TxHeaderTranslate_addr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    102
	    Name		    "TxHeaderTranslate_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    103
	    Name		    "TxHeaderTranslate_we"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    104
	    Name		    "TxModulation_addr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    105
	    Name		    "TxModulation_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    106
	    Name		    "TxModulation_we"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "sg_plb_addrpref"
	  Ports			  [1, 1]
	  Position		  [110, 665, 175, 685]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'sg_plb_addrpref'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "65,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "addrPref"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Line {
	  Name			  "Sl_addrAck"
	  SrcBlock		  "plb_decode"
	  SrcPort		  2
	  Points		  [0, 0]
	  Branch {
	    Labels		    [1, 0]
	    Points		    [5, 0; 0, 2045]
	    DstBlock		    "plb_memmap"
	    DstPort		    5
	  }
	  Branch {
	    Labels		    [0, 0]
	    Points		    [30, 0; 0, -315]
	    DstBlock		    "Sl_addrAck"
	    DstPort		    1
	  }
	}
	Line {
	  Name			  "Sl_wrDAck"
	  SrcBlock		  "plb_decode"
	  SrcPort		  4
	  Points		  [0, 0]
	  Branch {
	    Labels		    [1, 0]
	    Points		    [30, 0; 0, -205]
	    DstBlock		    "Sl_wrDAck"
	    DstPort		    1
	  }
	  Branch {
	    Labels		    [0, 0]
	    Points		    [30, 0; 0, -20]
	    DstBlock		    "Sl_wrComp"
	    DstPort		    1
	  }
	}
	Line {
	  Name			  "TxModulation_we"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  106
	  Points		  [5, 0; 0, 1900]
	  DstBlock		  "Shared Memory6"
	  DstPort		  3
	}
	Line {
	  Name			  "TxModulation_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  105
	  Points		  [5, 0; 0, 1875]
	  DstBlock		  "Shared Memory6"
	  DstPort		  2
	}
	Line {
	  Name			  "TxModulation_addr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  104
	  Points		  [5, 0; 0, 1850]
	  DstBlock		  "Shared Memory6"
	  DstPort		  1
	}
	Line {
	  Name			  "TxHeaderTranslate_we"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  103
	  Points		  [5, 0; 0, 1795]
	  DstBlock		  "Shared Memory5"
	  DstPort		  3
	}
	Line {
	  Name			  "TxHeaderTranslate_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  102
	  Points		  [5, 0; 0, 1770]
	  DstBlock		  "Shared Memory5"
	  DstPort		  2
	}
	Line {
	  Name			  "TxHeaderTranslate_addr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  101
	  Points		  [5, 0; 0, 1745]
	  DstBlock		  "Shared Memory5"
	  DstPort		  1
	}
	Line {
	  Name			  "RxModulation_we"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  100
	  Points		  [5, 0; 0, 1685]
	  DstBlock		  "Shared Memory4"
	  DstPort		  3
	}
	Line {
	  Name			  "RxModulation_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  99
	  Points		  [5, 0; 0, 1660]
	  DstBlock		  "Shared Memory4"
	  DstPort		  2
	}
	Line {
	  Name			  "RxModulation_addr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  98
	  Points		  [5, 0; 0, 1635]
	  DstBlock		  "Shared Memory4"
	  DstPort		  1
	}
	Line {
	  Name			  "PktBufFreqOffsets_we"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  97
	  Points		  [5, 0; 0, 1580]
	  DstBlock		  "Shared Memory3"
	  DstPort		  3
	}
	Line {
	  Name			  "PktBufFreqOffsets_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  96
	  Points		  [5, 0; 0, 1555]
	  DstBlock		  "Shared Memory3"
	  DstPort		  2
	}
	Line {
	  Name			  "PktBufFreqOffsets_addr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  95
	  Points		  [5, 0; 0, 1530]
	  DstBlock		  "Shared Memory3"
	  DstPort		  1
	}
	Line {
	  Name			  "EVM_perSym_we"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  94
	  Points		  [5, 0; 0, 1475]
	  DstBlock		  "Shared Memory2"
	  DstPort		  3
	}
	Line {
	  Name			  "EVM_perSym_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  93
	  Points		  [5, 0; 0, 1450]
	  DstBlock		  "Shared Memory2"
	  DstPort		  2
	}
	Line {
	  Name			  "EVM_perSym_addr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  92
	  Points		  [5, 0; 0, 1425]
	  DstBlock		  "Shared Memory2"
	  DstPort		  1
	}
	Line {
	  Name			  "EVM_perSC_we"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  91
	  Points		  [5, 0; 0, 1370]
	  DstBlock		  "Shared Memory1"
	  DstPort		  3
	}
	Line {
	  Name			  "EVM_perSC_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  90
	  Points		  [5, 0; 0, 1345]
	  DstBlock		  "Shared Memory1"
	  DstPort		  2
	}
	Line {
	  Name			  "EVM_perSC_addr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  89
	  Points		  [5, 0; 0, 1320]
	  DstBlock		  "Shared Memory1"
	  DstPort		  1
	}
	Line {
	  Name			  "ChannelEstimates_we"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  88
	  Points		  [5, 0; 0, 1260]
	  DstBlock		  "Shared Memory"
	  DstPort		  3
	}
	Line {
	  Name			  "ChannelEstimates_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  87
	  Points		  [5, 0; 0, 1235]
	  DstBlock		  "Shared Memory"
	  DstPort		  2
	}
	Line {
	  Name			  "ChannelEstimates_addr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  86
	  Points		  [10, 0]
	  DstBlock		  "Shared Memory"
	  DstPort		  1
	}
	Line {
	  Name			  "pktDet_thresholds_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  85
	  Points		  [15, 0; 0, 1160]
	  DstBlock		  "To Register41"
	  DstPort		  2
	}
	Line {
	  Name			  "pktDet_thresholds_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  84
	  Points		  [15, 0; 0, 1135]
	  DstBlock		  "To Register41"
	  DstPort		  1
	}
	Line {
	  Name			  "pktDet_durations_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  83
	  Points		  [15, 0; 0, 1080]
	  DstBlock		  "To Register40"
	  DstPort		  2
	}
	Line {
	  Name			  "pktDet_durations_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  82
	  Points		  [15, 0; 0, 1055]
	  DstBlock		  "To Register40"
	  DstPort		  1
	}
	Line {
	  Name			  "pktDet_controlBits_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  81
	  Points		  [15, 0; 0, 1005]
	  DstBlock		  "To Register39"
	  DstPort		  2
	}
	Line {
	  Name			  "pktDet_controlBits_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  80
	  Points		  [15, 0; 0, 980]
	  DstBlock		  "To Register39"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_Start_Reset_Control_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  79
	  Points		  [15, 0; 0, 930]
	  DstBlock		  "To Register38"
	  DstPort		  2
	}
	Line {
	  Name			  "Tx_Start_Reset_Control_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  78
	  Points		  [15, 0; 0, 905]
	  DstBlock		  "To Register38"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_Scaling_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  77
	  Points		  [15, 0; 0, 850]
	  DstBlock		  "To Register37"
	  DstPort		  2
	}
	Line {
	  Name			  "Tx_Scaling_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  76
	  Points		  [15, 0; 0, 825]
	  DstBlock		  "To Register37"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_OFDM_SymCounts_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  75
	  Points		  [15, 0; 0, 775]
	  DstBlock		  "To Register36"
	  DstPort		  2
	}
	Line {
	  Name			  "Tx_OFDM_SymCounts_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  74
	  Points		  [15, 0; 0, 750]
	  DstBlock		  "To Register36"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_Delays_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  73
	  Points		  [15, 0; 0, 700]
	  DstBlock		  "To Register35"
	  DstPort		  2
	}
	Line {
	  Name			  "Tx_Delays_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  72
	  Points		  [15, 0; 0, 675]
	  DstBlock		  "To Register35"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_ControlBits_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  71
	  Points		  [15, 0; 0, 620]
	  DstBlock		  "To Register34"
	  DstPort		  2
	}
	Line {
	  Name			  "Tx_ControlBits_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  70
	  Points		  [15, 0; 0, 595]
	  DstBlock		  "To Register34"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_Pilots_Values_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  69
	  Points		  [15, 0; 0, 545]
	  DstBlock		  "To Register33"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_Pilots_Values_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  68
	  Points		  [15, 0; 0, 520]
	  DstBlock		  "To Register33"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_Pilots_Index_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  67
	  Points		  [15, 0; 0, 470]
	  DstBlock		  "To Register32"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_Pilots_Index_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  66
	  Points		  [15, 0; 0, 445]
	  DstBlock		  "To Register32"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_Interrupt_PktBuf_Ctrl_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  65
	  Points		  [15, 0; 0, 390]
	  DstBlock		  "To Register31"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_Interrupt_PktBuf_Ctrl_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  64
	  Points		  [15, 0; 0, 365]
	  DstBlock		  "To Register31"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_FFT_Scaling_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  63
	  Points		  [15, 0; 0, 315]
	  DstBlock		  "To Register30"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_FFT_Scaling_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  62
	  Points		  [15, 0; 0, 290]
	  DstBlock		  "To Register30"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match7_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  61
	  Points		  [15, 0; 0, 240]
	  DstBlock		  "To Register29"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Match7_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  60
	  Points		  [15, 0; 0, 215]
	  DstBlock		  "To Register29"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match6_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  59
	  Points		  [15, 0; 0, 160]
	  DstBlock		  "To Register28"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Match6_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  58
	  Points		  [15, 0; 0, 135]
	  DstBlock		  "To Register28"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match5_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  57
	  Points		  [15, 0; 0, 85]
	  DstBlock		  "To Register27"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Match5_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  56
	  Points		  [15, 0; 0, 60]
	  DstBlock		  "To Register27"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match4_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  55
	  Points		  [20, 0]
	  DstBlock		  "To Register26"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Match4_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  54
	  Points		  [20, 0]
	  DstBlock		  "To Register26"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match3_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  53
	  Points		  [15, 0; 0, -70]
	  DstBlock		  "To Register25"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Match3_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  52
	  Points		  [15, 0; 0, -95]
	  DstBlock		  "To Register25"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match2_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  51
	  Points		  [15, 0; 0, -145]
	  DstBlock		  "To Register24"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Match2_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  50
	  Points		  [15, 0; 0, -170]
	  DstBlock		  "To Register24"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match1_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  49
	  Points		  [15, 0; 0, -220]
	  DstBlock		  "To Register23"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Match1_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  48
	  Points		  [15, 0; 0, -245]
	  DstBlock		  "To Register23"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match0_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  47
	  Points		  [15, 0; 0, -300]
	  DstBlock		  "To Register22"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Match0_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  46
	  Points		  [15, 0; 0, -325]
	  DstBlock		  "To Register22"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action5_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  45
	  Points		  [15, 0; 0, -375]
	  DstBlock		  "To Register21"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Action5_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  44
	  Points		  [15, 0; 0, -400]
	  DstBlock		  "To Register21"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action4_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  43
	  Points		  [15, 0; 0, -450]
	  DstBlock		  "To Register20"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Action4_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  42
	  Points		  [15, 0; 0, -475]
	  DstBlock		  "To Register20"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action3_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  41
	  Points		  [15, 0; 0, -530]
	  DstBlock		  "To Register19"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Action3_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  40
	  Points		  [15, 0; 0, -555]
	  DstBlock		  "To Register19"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action2_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  39
	  Points		  [15, 0; 0, -605]
	  DstBlock		  "To Register18"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Action2_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  38
	  Points		  [15, 0; 0, -630]
	  DstBlock		  "To Register18"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action1_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  37
	  Points		  [15, 0; 0, -680]
	  DstBlock		  "To Register17"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Action1_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  36
	  Points		  [15, 0; 0, -705]
	  DstBlock		  "To Register17"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action0_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  35
	  Points		  [15, 0; 0, -760]
	  DstBlock		  "To Register16"
	  DstPort		  2
	}
	Line {
	  Name			  "TxRx_AutoReply_Action0_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  34
	  Points		  [15, 0; 0, -785]
	  DstBlock		  "To Register16"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_pktDet_Tresholds_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  33
	  Points		  [15, 0; 0, -835]
	  DstBlock		  "To Register15"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_pktDet_Tresholds_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  32
	  Points		  [15, 0; 0, -860]
	  DstBlock		  "To Register15"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_pktByteNums_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  31
	  Points		  [15, 0; 0, -910]
	  DstBlock		  "To Register14"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_pktByteNums_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  30
	  Points		  [15, 0; 0, -935]
	  DstBlock		  "To Register14"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_coarseCFO_correction_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  29
	  Points		  [15, 0; 0, -990]
	  DstBlock		  "To Register13"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_coarseCFO_correction_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  28
	  Points		  [15, 0; 0, -1015]
	  DstBlock		  "To Register13"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PreCFO_PilotCalcCorrection_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  27
	  Points		  [15, 0; 0, -1065]
	  DstBlock		  "To Register12"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_PreCFO_PilotCalcCorrection_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  26
	  Points		  [15, 0; 0, -1090]
	  DstBlock		  "To Register12"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PreCFO_Options_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  25
	  Points		  [15, 0; 0, -1140]
	  DstBlock		  "To Register11"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_PreCFO_Options_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  24
	  Points		  [15, 0; 0, -1165]
	  DstBlock		  "To Register11"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PktDet_LongCorr_Thresholds_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  23
	  Points		  [15, 0; 0, -1220]
	  DstBlock		  "To Register10"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_PktDet_LongCorr_Thresholds_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  22
	  Points		  [15, 0; 0, -1245]
	  DstBlock		  "To Register10"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PktDet_LongCorr_Params_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  21
	  Points		  [15, 0; 0, -1295]
	  DstBlock		  "To Register9"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_PktDet_LongCorr_Params_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  20
	  Points		  [15, 0; 0, -1320]
	  DstBlock		  "To Register9"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PktDet_Delay_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  19
	  Points		  [15, 0; 0, -1370]
	  DstBlock		  "To Register8"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_PktDet_Delay_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  18
	  Points		  [15, 0; 0, -1395]
	  DstBlock		  "To Register8"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PilotCalcParams_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  17
	  Points		  [15, 0; 0, -1450]
	  DstBlock		  "To Register7"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_PilotCalcParams_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  16
	  Points		  [15, 0; 0, -1475]
	  DstBlock		  "To Register7"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_OFDM_SymbolCounts_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  15
	  Points		  [15, 0; 0, -1525]
	  DstBlock		  "To Register6"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_OFDM_SymbolCounts_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  14
	  Points		  [15, 0; 0, -1550]
	  DstBlock		  "To Register6"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_FixedPktLen_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  13
	  Points		  [15, 0; 0, -1600]
	  DstBlock		  "To Register5"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_FixedPktLen_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  12
	  Points		  [15, 0; 0, -1625]
	  DstBlock		  "To Register5"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_ControlBits_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  11
	  Points		  [15, 0; 0, -1680]
	  DstBlock		  "To Register4"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_ControlBits_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  10
	  Points		  [15, 0; 0, -1705]
	  DstBlock		  "To Register4"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_Constellation_Scaling_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  9
	  Points		  [15, 0; 0, -1755]
	  DstBlock		  "To Register3"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_Constellation_Scaling_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  8
	  Points		  [15, 0; 0, -1780]
	  DstBlock		  "To Register3"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_ChanEst_MinMag_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  7
	  Points		  [15, 0; 0, -1830]
	  DstBlock		  "To Register2"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_ChanEst_MinMag_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  6
	  Points		  [15, 0; 0, -1855]
	  DstBlock		  "To Register2"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_AF_TxScaling_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  5
	  Points		  [15, 0; 0, -1910]
	  DstBlock		  "To Register1"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_AF_TxScaling_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  4
	  Points		  [15, 0; 0, -1935]
	  DstBlock		  "To Register1"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_AF_Blanking_w_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  3
	  Points		  [15, 0; 0, -1985]
	  DstBlock		  "To Register"
	  DstPort		  2
	}
	Line {
	  Name			  "Rx_AF_Blanking_w_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  2
	  Points		  [15, 0; 0, -2010]
	  DstBlock		  "To Register"
	  DstPort		  1
	}
	Line {
	  Name			  "rdData"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  1
	  Points		  [0, -1630; -395, 0; 0, -95]
	  DstBlock		  "plb_decode"
	  DstPort		  6
	}
	Line {
	  Name			  "TxModulation_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "Shared Memory6"
	  SrcPort		  1
	  Points		  [0, -65; -300, 0]
	  DstBlock		  "plb_memmap"
	  DstPort		  49
	}
	Line {
	  Name			  "TxHeaderTranslate_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "Shared Memory5"
	  SrcPort		  1
	  Points		  [0, -75; -305, 0; 0, -1705]
	  DstBlock		  "plb_memmap"
	  DstPort		  48
	}
	Line {
	  Name			  "RxModulation_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "Shared Memory4"
	  SrcPort		  1
	  Points		  [0, -65; -305, 0; 0, -1600]
	  DstBlock		  "plb_memmap"
	  DstPort		  47
	}
	Line {
	  Name			  "PktBufFreqOffsets_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "Shared Memory3"
	  SrcPort		  1
	  Points		  [0, -65; -305, 0; 0, -1490]
	  DstBlock		  "plb_memmap"
	  DstPort		  46
	}
	Line {
	  Name			  "EVM_perSym_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "Shared Memory2"
	  SrcPort		  1
	  Points		  [0, -70; -305, 0; 0, -1375]
	  DstBlock		  "plb_memmap"
	  DstPort		  45
	}
	Line {
	  Name			  "EVM_perSC_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "Shared Memory1"
	  SrcPort		  1
	  Points		  [0, -70; -305, 0; 0, -1265]
	  DstBlock		  "plb_memmap"
	  DstPort		  44
	}
	Line {
	  Name			  "ChannelEstimates_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "Shared Memory"
	  SrcPort		  1
	  Points		  [0, -1105; -305, 0; 0, -115]
	  DstBlock		  "plb_memmap"
	  DstPort		  43
	}
	Line {
	  Name			  "pktDet_thresholds_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register36"
	  SrcPort		  1
	  Points		  [60, 0; 0, -1375]
	  DstBlock		  "plb_memmap"
	  DstPort		  42
	}
	Line {
	  Name			  "pktDet_status_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register35"
	  SrcPort		  1
	  Points		  [60, 0; 0, -1300]
	  DstBlock		  "plb_memmap"
	  DstPort		  41
	}
	Line {
	  Name			  "pktDet_durations_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register34"
	  SrcPort		  1
	  Points		  [60, 0; 0, -1220]
	  DstBlock		  "plb_memmap"
	  DstPort		  40
	}
	Line {
	  Name			  "pktDet_controlBits_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register33"
	  SrcPort		  1
	  Points		  [60, 0; 0, -1145]
	  DstBlock		  "plb_memmap"
	  DstPort		  39
	}
	Line {
	  Name			  "midPacketRSSI_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register32"
	  SrcPort		  1
	  Points		  [60, 0; 0, -1070]
	  DstBlock		  "plb_memmap"
	  DstPort		  38
	}
	Line {
	  Name			  "Tx_Start_Reset_Control_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register31"
	  SrcPort		  1
	  Points		  [60, 0; 0, -990]
	  DstBlock		  "plb_memmap"
	  DstPort		  37
	}
	Line {
	  Name			  "Tx_PktRunning_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register30"
	  SrcPort		  1
	  Points		  [60, 0; 0, -915]
	  DstBlock		  "plb_memmap"
	  DstPort		  36
	}
	Line {
	  Name			  "Tx_OFDM_SymCounts_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register29"
	  SrcPort		  1
	  Points		  [60, 0; 0, -840]
	  DstBlock		  "plb_memmap"
	  DstPort		  35
	}
	Line {
	  Name			  "Tx_Delays_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register28"
	  SrcPort		  1
	  Points		  [60, 0; 0, -760]
	  DstBlock		  "plb_memmap"
	  DstPort		  34
	}
	Line {
	  Name			  "Tx_ControlBits_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register27"
	  SrcPort		  1
	  Points		  [60, 0; 0, -685]
	  DstBlock		  "plb_memmap"
	  DstPort		  33
	}
	Line {
	  Name			  "TxRx_Interrupt_PktBuf_Ctrl_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register26"
	  SrcPort		  1
	  Points		  [60, 0; 0, -610]
	  DstBlock		  "plb_memmap"
	  DstPort		  32
	}
	Line {
	  Name			  "TxRx_AutoReply_Match7_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register25"
	  SrcPort		  1
	  Points		  [60, 0; 0, -530]
	  DstBlock		  "plb_memmap"
	  DstPort		  31
	}
	Line {
	  Name			  "TxRx_AutoReply_Match6_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register24"
	  SrcPort		  1
	  Points		  [60, 0; 0, -455]
	  DstBlock		  "plb_memmap"
	  DstPort		  30
	}
	Line {
	  Name			  "TxRx_AutoReply_Match5_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register23"
	  SrcPort		  1
	  Points		  [60, 0; 0, -380]
	  DstBlock		  "plb_memmap"
	  DstPort		  29
	}
	Line {
	  Name			  "TxRx_AutoReply_Match4_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register22"
	  SrcPort		  1
	  Points		  [60, 0; 0, -300]
	  DstBlock		  "plb_memmap"
	  DstPort		  28
	}
	Line {
	  Name			  "TxRx_AutoReply_Match3_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register21"
	  SrcPort		  1
	  Points		  [60, 0; 0, -225]
	  DstBlock		  "plb_memmap"
	  DstPort		  27
	}
	Line {
	  Name			  "TxRx_AutoReply_Match2_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register20"
	  SrcPort		  1
	  Points		  [60, 0; 0, -150]
	  DstBlock		  "plb_memmap"
	  DstPort		  26
	}
	Line {
	  Name			  "TxRx_AutoReply_Match1_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register19"
	  SrcPort		  1
	  Points		  [30, 0; 0, -70]
	  DstBlock		  "plb_memmap"
	  DstPort		  25
	}
	Line {
	  Name			  "TxRx_AutoReply_Match0_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register18"
	  SrcPort		  1
	  Points		  [0, 5]
	  DstBlock		  "plb_memmap"
	  DstPort		  24
	}
	Line {
	  Name			  "TxRx_AutoReply_Action5_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register17"
	  SrcPort		  1
	  Points		  [60, 0; 0, 80]
	  DstBlock		  "plb_memmap"
	  DstPort		  23
	}
	Line {
	  Name			  "TxRx_AutoReply_Action4_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register16"
	  SrcPort		  1
	  Points		  [60, 0; 0, 160]
	  DstBlock		  "plb_memmap"
	  DstPort		  22
	}
	Line {
	  Name			  "TxRx_AutoReply_Action3_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register15"
	  SrcPort		  1
	  Points		  [60, 0; 0, 235]
	  DstBlock		  "plb_memmap"
	  DstPort		  21
	}
	Line {
	  Name			  "TxRx_AutoReply_Action2_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register14"
	  SrcPort		  1
	  Points		  [60, 0; 0, 310]
	  DstBlock		  "plb_memmap"
	  DstPort		  20
	}
	Line {
	  Name			  "TxRx_AutoReply_Action1_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register13"
	  SrcPort		  1
	  Points		  [60, 0; 0, 390]
	  DstBlock		  "plb_memmap"
	  DstPort		  19
	}
	Line {
	  Name			  "TxRx_AutoReply_Action0_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register12"
	  SrcPort		  1
	  Points		  [60, 0; 0, 465]
	  DstBlock		  "plb_memmap"
	  DstPort		  18
	}
	Line {
	  Name			  "Rx_pktDone_interruptStatus_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register11"
	  SrcPort		  1
	  Points		  [60, 0; 0, 540]
	  DstBlock		  "plb_memmap"
	  DstPort		  17
	}
	Line {
	  Name			  "Rx_pktDetEventCount_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register10"
	  SrcPort		  1
	  Points		  [60, 0; 0, 620]
	  DstBlock		  "plb_memmap"
	  DstPort		  16
	}
	Line {
	  Name			  "Rx_pktByteNums_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register9"
	  SrcPort		  1
	  Points		  [60, 0; 0, 695]
	  DstBlock		  "plb_memmap"
	  DstPort		  15
	}
	Line {
	  Name			  "Rx_pilotCFOest_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register8"
	  SrcPort		  1
	  Points		  [60, 0; 0, 770]
	  DstBlock		  "plb_memmap"
	  DstPort		  14
	}
	Line {
	  Name			  "Rx_coarseCFOest_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register7"
	  SrcPort		  1
	  Points		  [60, 0; 0, 850]
	  DstBlock		  "plb_memmap"
	  DstPort		  13
	}
	Line {
	  Name			  "Rx_PktDet_LongCorr_Params_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register6"
	  SrcPort		  1
	  Points		  [60, 0; 0, 925]
	  DstBlock		  "plb_memmap"
	  DstPort		  12
	}
	Line {
	  Name			  "Rx_PktDet_Delay_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register5"
	  SrcPort		  1
	  Points		  [60, 0; 0, 1000]
	  DstBlock		  "plb_memmap"
	  DstPort		  11
	}
	Line {
	  Name			  "Rx_OFDM_SymbolCounts_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register4"
	  SrcPort		  1
	  Points		  [60, 0; 0, 1080]
	  DstBlock		  "plb_memmap"
	  DstPort		  10
	}
	Line {
	  Name			  "Rx_Gains_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register3"
	  SrcPort		  1
	  Points		  [60, 0; 0, 1155]
	  DstBlock		  "plb_memmap"
	  DstPort		  9
	}
	Line {
	  Name			  "Rx_ControlBits_r_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register2"
	  SrcPort		  1
	  Points		  [60, 0; 0, 1230]
	  DstBlock		  "plb_memmap"
	  DstPort		  8
	}
	Line {
	  Name			  "Rx_BER_TotalBits_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register1"
	  SrcPort		  1
	  Points		  [60, 0; 0, 1310]
	  DstBlock		  "plb_memmap"
	  DstPort		  7
	}
	Line {
	  Name			  "Rx_BER_Errors_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register"
	  SrcPort		  1
	  Points		  [60, 0; 0, 1385]
	  DstBlock		  "plb_memmap"
	  DstPort		  6
	}
	Line {
	  Name			  "RNWReg"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  6
	  Points		  [5, 0; 0, 1855]
	  DstBlock		  "plb_memmap"
	  DstPort		  4
	}
	Line {
	  Name			  "linearAddr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  9
	  Points		  [5, 0; 0, 1710]
	  DstBlock		  "plb_memmap"
	  DstPort		  3
	}
	Line {
	  Name			  "bankAddr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  5
	  Points		  [5, 0; 0, 1880]
	  DstBlock		  "plb_memmap"
	  DstPort		  2
	}
	Line {
	  Name			  "wrDBusReg"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  1
	  Points		  [10, 0]
	  DstBlock		  "plb_memmap"
	  DstPort		  1
	}
	Line {
	  Name			  "pktDet_thresholds_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register41"
	  SrcPort		  1
	  DstBlock		  "Terminator48"
	  DstPort		  1
	}
	Line {
	  Name			  "pktDet_durations_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register40"
	  SrcPort		  1
	  DstBlock		  "Terminator47"
	  DstPort		  1
	}
	Line {
	  Name			  "pktDet_controlBits_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register39"
	  SrcPort		  1
	  DstBlock		  "Terminator46"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_Start_Reset_Control_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register38"
	  SrcPort		  1
	  DstBlock		  "Terminator45"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_Scaling_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register37"
	  SrcPort		  1
	  DstBlock		  "Terminator44"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_OFDM_SymCounts_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register36"
	  SrcPort		  1
	  DstBlock		  "Terminator43"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_Delays_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register35"
	  SrcPort		  1
	  DstBlock		  "Terminator42"
	  DstPort		  1
	}
	Line {
	  Name			  "Tx_ControlBits_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register34"
	  SrcPort		  1
	  DstBlock		  "Terminator41"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_Pilots_Values_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register33"
	  SrcPort		  1
	  DstBlock		  "Terminator40"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_Pilots_Index_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register32"
	  SrcPort		  1
	  DstBlock		  "Terminator39"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_Interrupt_PktBuf_Ctrl_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register31"
	  SrcPort		  1
	  DstBlock		  "Terminator38"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_FFT_Scaling_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register30"
	  SrcPort		  1
	  DstBlock		  "Terminator37"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match7_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register29"
	  SrcPort		  1
	  DstBlock		  "Terminator36"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match6_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register28"
	  SrcPort		  1
	  DstBlock		  "Terminator35"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match5_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register27"
	  SrcPort		  1
	  DstBlock		  "Terminator34"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match4_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register26"
	  SrcPort		  1
	  DstBlock		  "Terminator33"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match3_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register25"
	  SrcPort		  1
	  DstBlock		  "Terminator32"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match2_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register24"
	  SrcPort		  1
	  DstBlock		  "Terminator31"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match1_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register23"
	  SrcPort		  1
	  DstBlock		  "Terminator30"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Match0_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register22"
	  SrcPort		  1
	  DstBlock		  "Terminator29"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action5_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register21"
	  SrcPort		  1
	  DstBlock		  "Terminator28"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action4_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register20"
	  SrcPort		  1
	  DstBlock		  "Terminator27"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action3_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register19"
	  SrcPort		  1
	  DstBlock		  "Terminator26"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action2_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register18"
	  SrcPort		  1
	  DstBlock		  "Terminator25"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action1_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register17"
	  SrcPort		  1
	  DstBlock		  "Terminator24"
	  DstPort		  1
	}
	Line {
	  Name			  "TxRx_AutoReply_Action0_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register16"
	  SrcPort		  1
	  DstBlock		  "Terminator23"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_pktDet_Tresholds_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register15"
	  SrcPort		  1
	  DstBlock		  "Terminator22"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_pktByteNums_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register14"
	  SrcPort		  1
	  DstBlock		  "Terminator21"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_coarseCFO_correction_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register13"
	  SrcPort		  1
	  DstBlock		  "Terminator20"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PreCFO_PilotCalcCorrection_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register12"
	  SrcPort		  1
	  DstBlock		  "Terminator19"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PreCFO_Options_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register11"
	  SrcPort		  1
	  DstBlock		  "Terminator18"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PktDet_LongCorr_Thresholds_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register10"
	  SrcPort		  1
	  DstBlock		  "Terminator17"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PktDet_LongCorr_Params_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register9"
	  SrcPort		  1
	  DstBlock		  "Terminator16"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PktDet_Delay_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register8"
	  SrcPort		  1
	  DstBlock		  "Terminator15"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_PilotCalcParams_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register7"
	  SrcPort		  1
	  DstBlock		  "Terminator14"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_OFDM_SymbolCounts_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register6"
	  SrcPort		  1
	  DstBlock		  "Terminator13"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_FixedPktLen_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register5"
	  SrcPort		  1
	  DstBlock		  "Terminator12"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_ControlBits_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register4"
	  SrcPort		  1
	  DstBlock		  "Terminator11"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_Constellation_Scaling_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register3"
	  SrcPort		  1
	  DstBlock		  "Terminator10"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_ChanEst_MinMag_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register2"
	  SrcPort		  1
	  DstBlock		  "Terminator9"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_AF_TxScaling_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register1"
	  SrcPort		  1
	  DstBlock		  "Terminator8"
	  DstPort		  1
	}
	Line {
	  Name			  "Rx_AF_Blanking_w_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register"
	  SrcPort		  1
	  DstBlock		  "Terminator7"
	  DstPort		  1
	}
	Line {
	  Name			  "Sl_rdDBus"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  8
	  Points		  [65, 0]
	  DstBlock		  "Sl_rdDBus"
	  DstPort		  1
	}
	Line {
	  Name			  "Sl_rdDAck"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  7
	  Points		  [65, 0]
	  DstBlock		  "Sl_rdDAck"
	  DstPort		  1
	}
	Line {
	  Name			  "Sl_rdComp"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  3
	  Points		  [60, 0; 0, -275]
	  DstBlock		  "Sl_rdComp"
	  DstPort		  1
	}
	Line {
	  Name			  "addrPref"
	  Labels		  [0, 0]
	  SrcBlock		  "sg_plb_addrpref"
	  SrcPort		  1
	  Points		  [10, 0]
	  DstBlock		  "plb_decode"
	  DstPort		  7
	}
	Line {
	  Name			  "PLB_wrDBus"
	  Labels		  [0, 0]
	  SrcBlock		  "PLB_wrDBus"
	  SrcPort		  1
	  Points		  [5, 0; 0, 5]
	  DstBlock		  "plb_decode"
	  DstPort		  5
	}
	Line {
	  Name			  "PLB_RNW"
	  Labels		  [0, 0]
	  SrcBlock		  "PLB_RNW"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  4
	}
	Line {
	  Name			  "PLB_PAValid"
	  Labels		  [0, 0]
	  SrcBlock		  "PLB_PAValid"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  3
	}
	Line {
	  Name			  "PLB_ABus"
	  Labels		  [0, 0]
	  SrcBlock		  "PLB_ABus"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  2
	}
	Line {
	  Name			  "SPLB_Rst"
	  Labels		  [0, 0]
	  SrcBlock		  "SPLB_Rst"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant6"
	  SrcPort		  1
	  DstBlock		  "sg_plb_addrpref"
	  DstPort		  1
	}
	Line {
	  Name			  "Sl_wait"
	  Labels		  [0, 0]
	  SrcBlock		  "Constant5"
	  SrcPort		  1
	  DstBlock		  "Sl_wait"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "PLB_wrDBus"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant3"
	  SrcPort		  1
	  DstBlock		  "PLB_RNW"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "PLB_PAValid"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "PLB_ABus"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "SPLB_Rst"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_wrComp"
	  SrcPort		  1
	  Points		  [70, 0; 0, -245]
	  DstBlock		  "Terminator6"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_wrDAck"
	  SrcPort		  1
	  Points		  [90, 0; 0, -110]
	  DstBlock		  "Terminator5"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_wait"
	  SrcPort		  1
	  DstBlock		  "Terminator4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_rdDBus"
	  SrcPort		  1
	  Points		  [70, 0; 0, -320]
	  DstBlock		  "Terminator3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_rdDAck"
	  SrcPort		  1
	  Points		  [70, 0; 0, -280]
	  DstBlock		  "Terminator2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_rdComp"
	  SrcPort		  1
	  Points		  [45, 0; 0, -45]
	  DstBlock		  "Terminator1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_addrAck"
	  SrcPort		  1
	  Points		  [45, 0; 0, -10]
	  DstBlock		  "Terminator"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Memory-mapped\nRegisters"
      Ports		      []
      Position		      [95, 128, 142, 173]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Memory-mapped\nRegisters"
	Location		[160, 70, 1782, 1131]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"343"
	Block {
	  BlockType		  SubSystem
	  Name			  "AutoReply Registers"
	  Ports			  []
	  Position		  [95, 160, 166, 197]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "AutoReply Registers"
	    Location		    [158, 69, 1365, 1151]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "121"
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample1"
	      Ports		      [1, 1]
	      Position		      [195, 40, 225, 70]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample10"
	      Ports		      [1, 1]
	      Position		      [660, 170, 690, 200]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample11"
	      Ports		      [1, 1]
	      Position		      [660, 105, 690, 135]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample12"
	      Ports		      [1, 1]
	      Position		      [660, 40, 690, 70]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample13"
	      Ports		      [1, 1]
	      Position		      [195, 435, 225, 465]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample14"
	      Ports		      [1, 1]
	      Position		      [195, 510, 225, 540]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample2"
	      Ports		      [1, 1]
	      Position		      [195, 105, 225, 135]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample3"
	      Ports		      [1, 1]
	      Position		      [195, 170, 225, 200]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample4"
	      Ports		      [1, 1]
	      Position		      [195, 235, 225, 265]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample5"
	      Ports		      [1, 1]
	      Position		      [195, 300, 225, 330]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample6"
	      Ports		      [1, 1]
	      Position		      [195, 365, 225, 395]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample7"
	      Ports		      [1, 1]
	      Position		      [660, 370, 690, 400]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample8"
	      Ports		      [1, 1]
	      Position		      [660, 305, 690, 335]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample9"
	      Ports		      [1, 1]
	      Position		      [660, 235, 690, 265]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "30,30,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto1"
	      Position		      [265, 113, 425, 127]
	      ShowName		      off
	      GotoTag		      "regAutoReply_match1"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto10"
	      Position		      [730, 313, 890, 327]
	      ShowName		      off
	      GotoTag		      "regAutoReply_action4"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto11"
	      Position		      [730, 378, 890, 392]
	      ShowName		      off
	      GotoTag		      "regAutoReply_action5"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto12"
	      Position		      [265, 443, 425, 457]
	      ShowName		      off
	      GotoTag		      "regAutoReply_match6"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto13"
	      Position		      [265, 518, 425, 532]
	      ShowName		      off
	      GotoTag		      "regAutoReply_match7"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto2"
	      Position		      [265, 178, 425, 192]
	      ShowName		      off
	      GotoTag		      "regAutoReply_match2"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto3"
	      Position		      [265, 308, 425, 322]
	      ShowName		      off
	      GotoTag		      "regAutoReply_match4"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto31"
	      Position		      [265, 48, 425, 62]
	      ShowName		      off
	      GotoTag		      "regAutoReply_match0"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto4"
	      Position		      [265, 373, 425, 387]
	      ShowName		      off
	      GotoTag		      "regAutoReply_match5"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto5"
	      Position		      [265, 243, 425, 257]
	      ShowName		      off
	      GotoTag		      "regAutoReply_match3"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto6"
	      Position		      [730, 48, 890, 62]
	      ShowName		      off
	      GotoTag		      "regAutoReply_action0"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto7"
	      Position		      [730, 113, 890, 127]
	      ShowName		      off
	      GotoTag		      "regAutoReply_action1"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto8"
	      Position		      [730, 178, 890, 192]
	      ShowName		      off
	      GotoTag		      "regAutoReply_action2"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto9"
	      Position		      [730, 243, 890, 257]
	      ShowName		      off
	      GotoTag		      "regAutoReply_action3"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register1"
	      Ports		      [0, 1]
	      Position		      [50, 104, 105, 136]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Match1'|Unsigned|32|0|Match1_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register1"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match1_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match1_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register10"
	      Ports		      [0, 1]
	      Position		      [515, 234, 570, 266]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Action3'|Unsigned|32|0|Action3_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register10"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action3_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action3_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register11"
	      Ports		      [0, 1]
	      Position		      [515, 369, 570, 401]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Action5'|Unsigned|32|0|Action5_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register11"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action5_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action5_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register12"
	      Ports		      [0, 1]
	      Position		      [515, 304, 570, 336]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Action4'|Unsigned|32|0|Action4_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register12"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action4_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action4_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register13"
	      Ports		      [0, 1]
	      Position		      [50, 434, 105, 466]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Match6'|Unsigned|32|0|Match6_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register13"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match6_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match6_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register14"
	      Ports		      [0, 1]
	      Position		      [50, 509, 105, 541]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Match7'|Unsigned|32|0|Match7_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register14"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match7_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match7_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register2"
	      Ports		      [0, 1]
	      Position		      [50, 169, 105, 201]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Match2'|Unsigned|32|0|Match2_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register2"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match2_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match2_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register3"
	      Ports		      [0, 1]
	      Position		      [50, 299, 105, 331]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Match4'|Unsigned|32|0|Match4_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register3"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match4_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match4_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register4"
	      Ports		      [0, 1]
	      Position		      [50, 364, 105, 396]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Match5'|Unsigned|32|0|Match5_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register4"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match5_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match5_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register5"
	      Ports		      [0, 1]
	      Position		      [50, 39, 105, 71]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Match0'|Unsigned|32|0|Match0_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register5"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match0_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match0_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register6"
	      Ports		      [0, 1]
	      Position		      [50, 234, 105, 266]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Match3'|Unsigned|32|0|Match3_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register6"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match3_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Match3_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register7"
	      Ports		      [0, 1]
	      Position		      [515, 39, 570, 71]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Action0'|Unsigned|32|0|Action0_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register7"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action0_w'"
		  init			  "26624"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action0_r'"
		  init			  "26624"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register8"
	      Ports		      [0, 1]
	      Position		      [515, 104, 570, 136]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Action1'|Unsigned|32|0|Action1_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register8"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action1_w'"
		  init			  "10240"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action1_r'"
		  init			  "10240"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register9"
	      Ports		      [0, 1]
	      Position		      [515, 169, 570, 201]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'TxRx_AutoReply_Action2'|Unsigned|32|0|Action2_Config|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register9"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action2_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'TxRx_AutoReply_Action2_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Line {
	      SrcBlock		      "Read-Write Register5"
	      SrcPort		      1
	      DstBlock		      "Down Sample1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register1"
	      SrcPort		      1
	      DstBlock		      "Down Sample2"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register2"
	      SrcPort		      1
	      DstBlock		      "Down Sample3"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register6"
	      SrcPort		      1
	      DstBlock		      "Down Sample4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register3"
	      SrcPort		      1
	      DstBlock		      "Down Sample5"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register4"
	      SrcPort		      1
	      DstBlock		      "Down Sample6"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register7"
	      SrcPort		      1
	      DstBlock		      "Down Sample12"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register8"
	      SrcPort		      1
	      DstBlock		      "Down Sample11"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register9"
	      SrcPort		      1
	      DstBlock		      "Down Sample10"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register10"
	      SrcPort		      1
	      DstBlock		      "Down Sample9"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register12"
	      SrcPort		      1
	      DstBlock		      "Down Sample8"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register11"
	      SrcPort		      1
	      DstBlock		      "Down Sample7"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample1"
	      SrcPort		      1
	      DstBlock		      "Goto31"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample2"
	      SrcPort		      1
	      DstBlock		      "Goto1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample3"
	      SrcPort		      1
	      DstBlock		      "Goto2"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample4"
	      SrcPort		      1
	      DstBlock		      "Goto5"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample5"
	      SrcPort		      1
	      DstBlock		      "Goto3"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample6"
	      SrcPort		      1
	      DstBlock		      "Goto4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample7"
	      SrcPort		      1
	      DstBlock		      "Goto11"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample8"
	      SrcPort		      1
	      DstBlock		      "Goto10"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample9"
	      SrcPort		      1
	      DstBlock		      "Goto9"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample10"
	      SrcPort		      1
	      DstBlock		      "Goto8"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample11"
	      SrcPort		      1
	      DstBlock		      "Goto7"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample12"
	      SrcPort		      1
	      DstBlock		      "Goto6"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register13"
	      SrcPort		      1
	      DstBlock		      "Down Sample13"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample13"
	      SrcPort		      1
	      DstBlock		      "Goto12"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register14"
	      SrcPort		      1
	      DstBlock		      "Down Sample14"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample14"
	      SrcPort		      1
	      DstBlock		      "Goto13"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Rx Registers"
	  Ports			  []
	  Position		  [175, 95, 246, 132]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Rx Registers"
	    Location		    [124, -217, 775, 1155]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Reference
	      Name		      "12LSB"
	      Ports		      [1, 1]
	      Position		      [185, 601, 220, 619]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "12"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "35,18,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "12LSB "
	      Ports		      [1, 1]
	      Position		      [285, 718, 325, 732]
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "12"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "12LSB  "
	      Ports		      [1, 1]
	      Position		      [995, 759, 1030, 771]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "12"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "35,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "12LSB+16"
	      Ports		      [1, 1]
	      Position		      [285, 698, 325, 712]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "12"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "16"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "16LSB"
	      Ports		      [1, 1]
	      Position		      [235, 933, 275, 947]
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "16"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "16LSB "
	      Ports		      [1, 1]
	      Position		      [955, 613, 995, 627]
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "16"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "16MSB  "
	      Ports		      [1, 1]
	      Position		      [235, 913, 275, 927]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "16"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "16"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "18LSB"
	      Ports		      [1, 1]
	      Position		      [180, 801, 215, 819]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "18"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "35,18,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "1LSB "
	      Ports		      [1, 1]
	      Position		      [870, 144, 905, 156]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "35,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "1LSB+1 "
	      Ports		      [1, 1]
	      Position		      [870, 184, 905, 196]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "35,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "1MSB"
	      Ports		      [1, 1]
	      Position		      [995, 709, 1030, 721]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "off"
	      mode		      "Upper Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "35,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "24MSB"
	      Ports		      [1, 1]
	      Position		      [300, 241, 335, 259]
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "24"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "8"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,442,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "35,18,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "3LSB+16"
	      Ports		      [1, 1]
	      Position		      [185, 641, 220, 659]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "3"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "16"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "35,18,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "5b+16"
	      Ports		      [1, 1]
	      Position		      [195, 383, 235, 397]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "5"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "16"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "6LSB+7"
	      Ports		      [1, 1]
	      Position		      [205, 338, 245, 352]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "6"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "7"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "7LSB"
	      Ports		      [1, 1]
	      Position		      [205, 293, 245, 307]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "7"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,442,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "8LSB "
	      Ports		      [1, 1]
	      Position		      [300, 211, 335, 229]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "8"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,442,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "35,18,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "8LSB+0"
	      Ports		      [1, 1]
	      Position		      [955, 433, 995, 447]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "8"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "8LSB+16"
	      Ports		      [1, 1]
	      Position		      [955, 503, 995, 517]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "8"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "16"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "8LSB+24"
	      Ports		      [1, 1]
	      Position		      [955, 533, 995, 547]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "8"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "24"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "8LSB+8"
	      Ports		      [1, 1]
	      Position		      [955, 463, 995, 477]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "8"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "8"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "8MSB"
	      Ports		      [1, 1]
	      Position		      [195, 418, 235, 432]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "8"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "24"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "ControlBits Slices"
	      Ports		      [1]
	      Position		      [285, 29, 360, 61]
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      System {
		Name			"ControlBits Slices"
		Location		[160, 70, 1782, 1131]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Inport
		  Name			  "32b"
		  Position		  [25, 38, 55, 52]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample"
		  Ports			  [1, 1]
		  Position		  [190, 51, 220, 79]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "-1,-1,-1,-1"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample1"
		  Ports			  [1, 1]
		  Position		  [190, 131, 220, 159]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "-1,-1,-1,-1"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample10"
		  Ports			  [1, 1]
		  Position		  [190, 231, 220, 259]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample11"
		  Ports			  [1, 1]
		  Position		  [190, 721, 220, 749]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample12"
		  Ports			  [1, 1]
		  Position		  [190, 766, 220, 794]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample13"
		  Ports			  [1, 1]
		  Position		  [190, 251, 220, 279]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,360,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample14"
		  Ports			  [1, 1]
		  Position		  [190, 271, 220, 299]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample19"
		  Ports			  [1, 1]
		  Position		  [190, 346, 220, 374]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample2"
		  Ports			  [1, 1]
		  Position		  [190, 151, 220, 179]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "-1,-1,-1,-1"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample3"
		  Ports			  [1, 1]
		  Position		  [190, 171, 220, 199]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "-1,-1,-1,-1"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample4"
		  Ports			  [1, 1]
		  Position		  [190, 301, 220, 329]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample5"
		  Ports			  [1, 1]
		  Position		  [190, 211, 220, 239]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample6"
		  Ports			  [1, 1]
		  Position		  [190, 401, 220, 429]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample7"
		  Ports			  [1, 1]
		  Position		  [190, 436, 220, 464]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample8"
		  Ports			  [1, 1]
		  Position		  [190, 481, 220, 509]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample9"
		  Ports			  [1, 1]
		  Position		  [190, 591, 220, 619]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto1"
		  Position		  [280, 55, 465, 75]
		  ShowName		  off
		  GotoTag		  "regRx_reqLongCorr"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto10"
		  Position		  [280, 509, 465, 531]
		  ShowName		  off
		  GotoTag		  "regRx_AlamoutiMode"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto11"
		  Position		  [280, 534, 465, 556]
		  ShowName		  off
		  GotoTag		  "regRx_FlexBERMode"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto12"
		  Position		  [280, 564, 465, 586]
		  ShowName		  off
		  GotoTag		  "regRx_BERignoreHeader"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto13"
		  Position		  [280, 114, 465, 136]
		  ShowName		  off
		  GotoTag		  "regRx_SISOmode"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto16"
		  Position		  [280, 594, 465, 616]
		  ShowName		  off
		  GotoTag		  "regRx_BER_perPktReset"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto17"
		  Position		  [280, 174, 465, 196]
		  ShowName		  off
		  GotoTag		  "regRx_chanEst_RecordEn"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto18"
		  Position		  [280, 624, 465, 646]
		  ShowName		  off
		  GotoTag		  "RxReg_radioRxEnable"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto19"
		  Position		  [280, 214, 465, 236]
		  ShowName		  off
		  GotoTag		  "regRx_freqCorrBypass"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto20"
		  Position		  [280, 654, 465, 676]
		  ShowName		  off
		  GotoTag		  "regRx_AF_SavePkt"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto21"
		  Position		  [280, 274, 465, 296]
		  ShowName		  off
		  GotoTag		  "regRx_CompensateRSSI_En"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto22"
		  Position		  [280, 379, 465, 401]
		  ShowName		  off
		  GotoTag		  "regRx_simpleDynRxModulationEn"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto23"
		  Position		  [280, 254, 465, 276]
		  ShowName		  off
		  GotoTag		  "regRx_ExtPktDetReset_En"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto24"
		  Position		  [280, 679, 465, 701]
		  ShowName		  off
		  GotoTag		  "RxReg_ResetFlagA"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto25"
		  Position		  [280, 194, 465, 216]
		  ShowName		  off
		  GotoTag		  "RxReg_CaptureChanMags"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto26"
		  Position		  [280, 704, 465, 726]
		  ShowName		  off
		  GotoTag		  "RxReg_ResetFlagB"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto27"
		  Position		  [280, 304, 465, 326]
		  ShowName		  off
		  GotoTag		  "RxReg_PreCFO_Negate"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto28"
		  Position		  [280, 724, 465, 746]
		  ShowName		  off
		  GotoTag		  "RxReg_PktDetCoarseCFOEn"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto29"
		  Position		  [280, 744, 465, 766]
		  ShowName		  off
		  GotoTag		  "regRx_UseChanMag_Masking"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto3"
		  Position		  [280, 234, 465, 256]
		  ShowName		  off
		  GotoTag		  "regRx_coarseCFO_en"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto31"
		  Position		  [280, 329, 465, 351]
		  ShowName		  off
		  GotoTag		  "regRx_DivisionBypass"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto33"
		  Position		  [285, 805, 470, 825]
		  ShowName		  off
		  GotoTag		  "regRx_GlobalReset"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto4"
		  Position		  [280, 404, 465, 426]
		  ShowName		  off
		  GotoTag		  "regRx_switchingDivEn"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto5"
		  Position		  [280, 35, 465, 55]
		  ShowName		  off
		  GotoTag		  "regRx_BER_reset"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto6"
		  Position		  [280, 439, 465, 461]
		  ShowName		  off
		  GotoTag		  "regRx_noSwitch_forceAntB"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto7"
		  Position		  [280, 94, 465, 116]
		  ShowName		  off
		  GotoTag		  "regTxRx_BigPktBufMode"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto8"
		  Position		  [280, 484, 465, 506]
		  ShowName		  off
		  GotoTag		  "regRx_resetOnBadHeader"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto9"
		  Position		  [280, 349, 465, 371]
		  ShowName		  off
		  GotoTag		  "regRx_forceDisableOnTx"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice"
		  Ports			  [1, 1]
		  Position		  [110, 36, 145, 54]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "0"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice1"
		  Ports			  [1, 1]
		  Position		  [110, 56, 145, 74]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "1"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice10"
		  Ports			  [1, 1]
		  Position		  [110, 236, 145, 254]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "10"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice11"
		  Ports			  [1, 1]
		  Position		  [110, 256, 145, 274]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "11"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice12"
		  Ports			  [1, 1]
		  Position		  [110, 276, 145, 294]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "12"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice13"
		  Ports			  [1, 1]
		  Position		  [110, 306, 145, 324]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "13"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice14"
		  Ports			  [1, 1]
		  Position		  [110, 331, 145, 349]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "14"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice15"
		  Ports			  [1, 1]
		  Position		  [110, 351, 145, 369]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "15"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice16"
		  Ports			  [1, 1]
		  Position		  [110, 381, 145, 399]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "16"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice17"
		  Ports			  [1, 1]
		  Position		  [110, 406, 145, 424]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "17"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice18"
		  Ports			  [1, 1]
		  Position		  [110, 441, 145, 459]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "18"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice19"
		  Ports			  [1, 1]
		  Position		  [110, 486, 145, 504]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "19"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice2"
		  Ports			  [1, 1]
		  Position		  [110, 76, 145, 94]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "2"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice20"
		  Ports			  [1, 1]
		  Position		  [110, 511, 145, 529]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "20"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice21"
		  Ports			  [1, 1]
		  Position		  [110, 536, 145, 554]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "21"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice22"
		  Ports			  [1, 1]
		  Position		  [110, 566, 145, 584]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "22"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice23"
		  Ports			  [1, 1]
		  Position		  [110, 596, 145, 614]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "23"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice24"
		  Ports			  [1, 1]
		  Position		  [110, 626, 145, 644]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "24"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice25"
		  Ports			  [1, 1]
		  Position		  [110, 806, 145, 824]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Upper Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "31"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice26"
		  Ports			  [1, 1]
		  Position		  [110, 656, 145, 674]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "25"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice27"
		  Ports			  [1, 1]
		  Position		  [110, 681, 145, 699]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "26"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice28"
		  Ports			  [1, 1]
		  Position		  [110, 706, 145, 724]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "27"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice29"
		  Ports			  [1, 1]
		  Position		  [110, 726, 145, 744]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "28"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice3"
		  Ports			  [1, 1]
		  Position		  [110, 96, 145, 114]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "3"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice30"
		  Ports			  [1, 1]
		  Position		  [110, 746, 145, 764]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "29"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice31"
		  Ports			  [1, 1]
		  Position		  [110, 771, 145, 789]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "30"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice4"
		  Ports			  [1, 1]
		  Position		  [110, 116, 145, 134]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "4"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice5"
		  Ports			  [1, 1]
		  Position		  [110, 156, 145, 174]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "6"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice6"
		  Ports			  [1, 1]
		  Position		  [110, 136, 145, 154]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "5"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice7"
		  Ports			  [1, 1]
		  Position		  [110, 176, 145, 194]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "7"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice8"
		  Ports			  [1, 1]
		  Position		  [110, 196, 145, 214]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "8"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice9"
		  Ports			  [1, 1]
		  Position		  [110, 216, 145, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "9"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "Slice"
		  SrcPort		  1
		  DstBlock		  "Goto5"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice1"
		  SrcPort		  1
		  DstBlock		  "Down Sample"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice2"
		  SrcPort		  1
		  Points		  [125, 0]
		}
		Line {
		  SrcBlock		  "Down Sample"
		  SrcPort		  1
		  DstBlock		  "Goto1"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice4"
		  SrcPort		  1
		  DstBlock		  "Goto13"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice6"
		  SrcPort		  1
		  DstBlock		  "Down Sample1"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice5"
		  SrcPort		  1
		  DstBlock		  "Down Sample2"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample1"
		  SrcPort		  1
		  Points		  [50, 0]
		}
		Line {
		  SrcBlock		  "Down Sample2"
		  SrcPort		  1
		  Points		  [50, 0]
		}
		Line {
		  SrcBlock		  "Slice7"
		  SrcPort		  1
		  DstBlock		  "Down Sample3"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice8"
		  SrcPort		  1
		  DstBlock		  "Goto25"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample3"
		  SrcPort		  1
		  DstBlock		  "Goto17"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice9"
		  SrcPort		  1
		  DstBlock		  "Down Sample5"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample5"
		  SrcPort		  1
		  DstBlock		  "Goto19"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "32b"
		  SrcPort		  1
		  Points		  [0, 0; 15, 0]
		  Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice16"
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		    }
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    DstBlock		    "Slice17"
		    DstPort		    1
		    }
		    Branch {
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		    Branch {
		    DstBlock		    "Slice18"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 45]
		    Branch {
		    DstBlock		    "Slice19"
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		    }
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    DstBlock		    "Slice20"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    DstBlock		    "Slice21"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice22"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice23"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice24"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice26"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    DstBlock		    "Slice27"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    DstBlock		    "Slice28"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    DstBlock		    "Slice29"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    DstBlock		    "Slice30"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    Points		    [0, 35]
		    DstBlock		    "Slice25"
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		    Branch {
		    DstBlock		    "Slice31"
		    DstPort		    1
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		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    Branch {
		    DstBlock		    "Slice15"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice14"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice13"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice12"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice11"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice10"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice9"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice8"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice7"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice5"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice6"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice4"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice3"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice2"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice1"
		    DstPort		    1
		    }
		  }
		  Branch {
		    DstBlock		    "Slice"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "Slice10"
		  SrcPort		  1
		  DstBlock		  "Down Sample10"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample10"
		  SrcPort		  1
		  DstBlock		  "Goto3"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice11"
		  SrcPort		  1
		  DstBlock		  "Down Sample13"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample13"
		  SrcPort		  1
		  DstBlock		  "Goto23"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample14"
		  SrcPort		  1
		  DstBlock		  "Goto21"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice12"
		  SrcPort		  1
		  DstBlock		  "Down Sample14"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice3"
		  SrcPort		  1
		  DstBlock		  "Goto7"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice13"
		  SrcPort		  1
		  DstBlock		  "Down Sample4"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice14"
		  SrcPort		  1
		  DstBlock		  "Goto31"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice15"
		  SrcPort		  1
		  DstBlock		  "Down Sample19"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample19"
		  SrcPort		  1
		  DstBlock		  "Goto9"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice25"
		  SrcPort		  1
		  DstBlock		  "Goto33"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice16"
		  SrcPort		  1
		  DstBlock		  "Goto22"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice17"
		  SrcPort		  1
		  DstBlock		  "Down Sample6"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample6"
		  SrcPort		  1
		  DstBlock		  "Goto4"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice18"
		  SrcPort		  1
		  DstBlock		  "Down Sample7"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample7"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "Goto6"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample8"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "Goto8"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice19"
		  SrcPort		  1
		  DstBlock		  "Down Sample8"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice20"
		  SrcPort		  1
		  DstBlock		  "Goto10"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice21"
		  SrcPort		  1
		  DstBlock		  "Goto11"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice22"
		  SrcPort		  1
		  DstBlock		  "Goto12"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice23"
		  SrcPort		  1
		  DstBlock		  "Down Sample9"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample9"
		  SrcPort		  1
		  DstBlock		  "Goto16"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice24"
		  SrcPort		  1
		  DstBlock		  "Goto18"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice26"
		  SrcPort		  1
		  DstBlock		  "Goto20"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice27"
		  SrcPort		  1
		  DstBlock		  "Goto24"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice28"
		  SrcPort		  1
		  DstBlock		  "Goto26"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample4"
		  SrcPort		  1
		  DstBlock		  "Goto27"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice29"
		  SrcPort		  1
		  DstBlock		  "Down Sample11"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample11"
		  SrcPort		  1
		  DstBlock		  "Goto28"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice30"
		  SrcPort		  1
		  DstBlock		  "Goto29"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice31"
		  SrcPort		  1
		  DstBlock		  "Down Sample12"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample12"
		  SrcPort		  1
		  Points		  [50, 0]
		}
		Annotation {
		  Name			  "LSB"
		  Position		  [125, 24]
		}
		Annotation {
		  Name			  "0x1"
		  Position		  [492, 49]
		}
		Annotation {
		  Name			  "0x2"
		  Position		  [492, 69]
		}
		Annotation {
		  Name			  "0x4"
		  Position		  [492, 89]
		}
		Annotation {
		  Name			  "0x8"
		  Position		  [492, 109]
		}
		Annotation {
		  Name			  "0x10"
		  Position		  [492, 129]
		}
		Annotation {
		  Name			  "0x20"
		  Position		  [492, 149]
		}
		Annotation {
		  Name			  "0x40"
		  Position		  [492, 169]
		}
		Annotation {
		  Name			  "0x100"
		  Position		  [492, 209]
		}
		Annotation {
		  Name			  "0x200"
		  Position		  [492, 229]
		}
		Annotation {
		  Name			  "0x400"
		  Position		  [492, 244]
		}
		Annotation {
		  Name			  "0x800"
		  Position		  [492, 264]
		}
		Annotation {
		  Name			  "0x1000"
		  Position		  [492, 284]
		}
		Annotation {
		  Name			  "0x2000"
		  Position		  [492, 319]
		}
		Annotation {
		  Name			  "0x4000"
		  Position		  [492, 344]
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		Annotation {
		  Name			  "0x1_0000"
		  Position		  [497, 389]
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		Annotation {
		  Name			  "0x2_0000"
		  Position		  [497, 414]
		}
		Annotation {
		  Name			  "0x4_0000"
		  Position		  [497, 449]
		}
		Annotation {
		  Name			  "0x8_0000"
		  Position		  [502, 494]
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		Annotation {
		  Name			  "0x8000"
		  Position		  [492, 364]
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		Annotation {
		  Name			  "0x10_0000"
		  Position		  [507, 519]
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		Annotation {
		  Name			  "0x20_0000"
		  Position		  [507, 544]
		}
		Annotation {
		  Name			  "0x40_0000"
		  Position		  [507, 574]
		}
		Annotation {
		  Name			  "0x80"
		  Position		  [492, 189]
		}
		Annotation {
		  Name			  "0x80_0000"
		  Position		  [507, 609]
		}
		Annotation {
		  Name			  "0x100_0000"
		  Position		  [512, 639]
		}
		Annotation {
		  Name			  "0x200_0000"
		  Position		  [512, 664]
		}
		Annotation {
		  Name			  "0x400_0000"
		  Position		  [512, 689]
		}
		Annotation {
		  Name			  "0x800_0000"
		  Position		  [512, 714]
		}
		Annotation {
		  Name			  "0x8000_0000"
		  Position		  [517, 814]
		}
		Annotation {
		  Name			  "0x1000_0000"
		  Position		  [512, 734]
		}
		Annotation {
		  Name			  "0x2000_0000"
		  Position		  [512, 754]
		}
		Annotation {
		  Name			  "0x4000_0000"
		  Position		  [512, 779]
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	      }
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample1"
	      Ports		      [1, 1]
	      Position		      [355, 411, 385, 439]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,303"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample12"
	      Ports		      [1, 1]
	      Position		      [865, 456, 895, 484]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample15"
	      Ports		      [1, 1]
	      Position		      [210, 206, 240, 234]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample17"
	      Ports		      [1, 1]
	      Position		      [355, 331, 385, 359]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample18"
	      Ports		      [1, 1]
	      Position		      [210, 31, 240, 59]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample2"
	      Ports		      [1, 1]
	      Position		      [990, 136, 1020, 164]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,303"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample20"
	      Ports		      [1, 1]
	      Position		      [195, 461, 225, 489]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,303"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample23"
	      Ports		      [1, 1]
	      Position		      [355, 376, 385, 404]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,303"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample3"
	      Ports		      [1, 1]
	      Position		      [990, 176, 1020, 204]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,303"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample4"
	      Ports		      [1, 1]
	      Position		      [180, 696, 205, 714]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,303"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "25,18,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample5"
	      Ports		      [1, 1]
	      Position		      [160, 911, 185, 929]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,303"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "25,18,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample6"
	      Ports		      [1, 1]
	      Position		      [860, 606, 890, 634]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample7"
	      Ports		      [1, 1]
	      Position		      [875, 701, 905, 729]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample9"
	      Ports		      [1, 1]
	      Position		      [355, 286, 385, 314]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From1"
	      Position		      [1400, 51, 1515, 69]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "RxReg_RxGainsEn"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From10"
	      Position		      [1345, 585, 1500, 605]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_pktDetEventCount_en"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From12"
	      Position		      [1365, 125, 1480, 145]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_BER_Errors"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From13"
	      Position		      [1365, 140, 1480, 160]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_BER_ErrorsEn"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From14"
	      Position		      [1365, 225, 1480, 245]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_BER_TotalBitsEn"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From2"
	      Position		      [1345, 310, 1500, 330]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_PktDone_InterruptStatus"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From25"
	      Position		      [1365, 210, 1480, 230]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_BER_TotalBits"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From3"
	      Position		      [1400, 36, 1515, 54]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "RxReg_RxGains"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From4"
	      Position		      [1345, 325, 1500, 345]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_PktDone_InterruptStatusEn"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From5"
	      Position		      [1345, 415, 1500, 435]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_pilotCFOest"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From6"
	      Position		      [1345, 430, 1500, 450]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_pilotCFOest_en"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From7"
	      Position		      [1345, 500, 1500, 520]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_coarseCFOest"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From8"
	      Position		      [1345, 515, 1500, 535]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_coarseCFOest_en"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From9"
	      Position		      [1345, 570, 1500, 590]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regRx_pktDetEventCount"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto1"
	      Position		      [395, 802, 550, 818]
	      ShowName		      off
	      GotoTag		      "regRx_AF_TxScaling"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto10"
	      Position		      [1040, 430, 1240, 450]
	      ShowName		      off
	      GotoTag		      "regRx_PktDet_LongCorr_CountLoad"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto11"
	      Position		      [355, 642, 510, 658]
	      ShowName		      off
	      GotoTag		      "regRx_PilotCFOCalc_AvgLen"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto12"
	      Position		      [395, 717, 550, 733]
	      ShowName		      off
	      GotoTag		      "regRx_AF_BlankStart"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto13"
	      Position		      [395, 697, 550, 713]
	      ShowName		      off
	      GotoTag		      "regRx_AF_BlankEnd"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto14"
	      Position		      [430, 932, 600, 948]
	      ShowName		      off
	      GotoTag		      "regRx_chanEst_minMagA"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto15"
	      Position		      [430, 912, 600, 928]
	      ShowName		      off
	      GotoTag		      "regRx_chanEst_minMagB"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto16"
	      Position		      [1040, 610, 1240, 630]
	      ShowName		      off
	      GotoTag		      "regRx_PktDet_LongCorr_Thresh"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto17"
	      Position		      [1050, 499, 1235, 521]
	      ShowName		      off
	      GotoTag		      "regRx_PktDet_LongCorr_WindStart"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto18"
	      Position		      [1050, 529, 1235, 551]
	      ShowName		      off
	      GotoTag		      "regRx_PktDet_LongCorr_WindEnd"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto19"
	      Position		      [1105, 705, 1305, 725]
	      ShowName		      off
	      GotoTag		      "regRx_fixedLenMode"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto2"
	      Position		      [465, 413, 635, 437]
	      ShowName		      off
	      GotoTag		      "regRx_CFOCalc_maxPhaseDiff"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto20"
	      Position		      [430, 290, 630, 310]
	      ShowName		      off
	      GotoTag		      "regRx_PktDet_Delay"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto21"
	      Position		      [1110, 755, 1310, 775]
	      ShowName		      off
	      GotoTag		      "regRx_fixedLen_maxNumBytes"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto26"
	      Position		      [355, 602, 510, 618]
	      ShowName		      off
	      GotoTag		      "regRx_MinimumPilotChanMag"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto27"
	      Position		      [410, 239, 595, 261]
	      ShowName		      off
	      GotoTag		      "regRx_headerByteNums"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto29"
	      Position		      [1045, 459, 1230, 481]
	      ShowName		      off
	      GotoTag		      "RxReg_PktDetCoarseCFO_CaptInd"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto3"
	      Position		      [1080, 142, 1260, 158]
	      ShowName		      off
	      GotoTag		      "RxReg_PreCFO_UseCoarse"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto4"
	      Position		      [255, 532, 400, 548]
	      ShowName		      off
	      GotoTag		      "RxReg_PostEQScaling"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto41"
	      Position		      [465, 378, 635, 402]
	      ShowName		      off
	      GotoTag		      "regRx_CFOCalc_Dly"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto45"
	      Position		      [315, 466, 410, 484]
	      ShowName		      off
	      GotoTag		      "Rx_IntPktDet_Thresholds"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto5"
	      Position		      [410, 209, 595, 231]
	      ShowName		      off
	      GotoTag		      "regTxRx_numHeaderBytes"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto6"
	      Position		      [1080, 182, 1260, 198]
	      ShowName		      off
	      GotoTag		      "RxReg_PreCFO_UsePilots"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto7"
	      Position		      [455, 333, 625, 357]
	      ShowName		      off
	      GotoTag		      "regRx_symbolTimingOffset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto8"
	      Position		      [1040, 227, 1220, 243]
	      ShowName		      off
	      GotoTag		      "regRx_PilotCFOCalc_Correction"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto9"
	      Position		      [1040, 297, 1220, 313]
	      ShowName		      off
	      GotoTag		      "regRx_coarseCFO_correction"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Pkt Detector Registers"
	      Ports		      []
	      Position		      [650, 43, 699, 96]
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      System {
		Name			"Pkt Detector Registers"
		Location		[160, 70, 1918, 1152]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "10LSB + 11"
		  Ports			  [1, 1]
		  Position		  [240, 346, 275, 364]
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "10"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "11"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "11LSB"
		  Ports			  [1, 1]
		  Position		  [240, 306, 275, 324]
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "11"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "0"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "16LSB"
		  Ports			  [1, 1]
		  Position		  [240, 466, 275, 484]
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "16"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "0"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "16MSB"
		  Ports			  [1, 1]
		  Position		  [240, 506, 275, 524]
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "16"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "16"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "5LSB + 21"
		  Ports			  [1, 1]
		  Position		  [240, 386, 275, 404]
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "5"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "21"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Concat"
		  Ports			  [5, 1]
		  Position		  [435, 577, 505, 673]
		  SourceBlock		  "xbsIndex_r4/Concat"
		  SourceType		  "Xilinx Bus Concatenator Block"
		  infoedit		  "Concatenates two or more inputs.  Output will be cast to an unsigned value with the binary point at zero."
		  num_inputs		  "5"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,165"
		  block_type		  "concat"
		  block_version		  "10.1.3"
		  sg_icon_stat		  "70,96,1,1,white,blue,0,b68db4a4,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',5,'lo');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [550, 643, 575, 667]
		  NamePlacement		  "alternate"
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  "off"
		  period		  "1"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "10.1.3"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Constant1"
		  Ports			  [0, 1]
		  Position		  [150, 593, 175, 617]
		  NamePlacement		  "alternate"
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Unsigned"
		  const			  "0"
		  n_bits		  "1"
		  bin_pt		  "0"
		  explicit_period	  "off"
		  period		  "1"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "10.1.3"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,72d575a1,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert1"
		  Ports			  [1, 1]
		  Position		  [330, 597, 355, 613]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "1"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  "off"
		  pipeline		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1.3"
		  sg_icon_stat		  "25,16,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert2"
		  Ports			  [1, 1]
		  Position		  [330, 617, 355, 633]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "1"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  "off"
		  pipeline		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1.3"
		  sg_icon_stat		  "25,16,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert3"
		  Ports			  [1, 1]
		  Position		  [330, 637, 355, 653]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "1"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  "off"
		  pipeline		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1.3"
		  sg_icon_stat		  "25,16,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert4"
		  Ports			  [1, 1]
		  Position		  [330, 657, 355, 673]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "1"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  "off"
		  pipeline		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1.3"
		  sg_icon_stat		  "25,16,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample1"
		  Ports			  [1, 1]
		  Position		  [395, 343, 420, 367]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample10"
		  Ports			  [1, 1]
		  Position		  [395, 58, 420, 82]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample11"
		  Ports			  [1, 1]
		  Position		  [395, 38, 420, 62]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample12"
		  Ports			  [1, 1]
		  Position		  [395, 158, 420, 182]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample13"
		  Ports			  [1, 1]
		  Position		  [395, 178, 420, 202]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample2"
		  Ports			  [1, 1]
		  Position		  [395, 383, 420, 407]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample3"
		  Ports			  [1, 1]
		  Position		  [400, 463, 425, 487]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample4"
		  Ports			  [1, 1]
		  Position		  [400, 503, 425, 527]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample5"
		  Ports			  [1, 1]
		  Position		  [395, 138, 420, 162]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample6"
		  Ports			  [1, 1]
		  Position		  [395, 303, 420, 327]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample7"
		  Ports			  [1, 1]
		  Position		  [395, 118, 420, 142]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample8"
		  Ports			  [1, 1]
		  Position		  [395, 98, 420, 122]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample9"
		  Ports			  [1, 1]
		  Position		  [395, 78, 420, 102]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "4"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "25,24,1,1,white,blue,0,f354a31c,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  From
		  Name			  "From1"
		  Position		  [45, 636, 200, 654]
		  ShowName		  off
		  CloseFcn		  "tagdialog Close"
		  GotoTag		  "regPktDet_pktDetected_AntA"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  From
		  Name			  "From2"
		  Position		  [45, 616, 200, 634]
		  ShowName		  off
		  CloseFcn		  "tagdialog Close"
		  GotoTag		  "regPktDet_pktDetected_AntB"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  From
		  Name			  "From3"
		  Position		  [45, 576, 200, 594]
		  ShowName		  off
		  CloseFcn		  "tagdialog Close"
		  GotoTag		  "regPktDet_idleCounter"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  From
		  Name			  "From4"
		  Position		  [45, 656, 200, 674]
		  ShowName		  off
		  CloseFcn		  "tagdialog Close"
		  GotoTag		  "regPktDet_idleForDIFS"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto1"
		  Position		  [495, 385, 680, 405]
		  ShowName		  off
		  GotoTag		  "regPktDet_RSSIavgLength"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto12"
		  Position		  [495, 60, 680, 80]
		  ShowName		  off
		  GotoTag		  "regPktDet_IgnoreDetection"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto13"
		  Position		  [495, 40, 680, 60]
		  ShowName		  off
		  GotoTag		  "regPktDet_MasterReset"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto14"
		  Position		  [495, 80, 680, 100]
		  ShowName		  off
		  GotoTag		  "regPktDet_RSSIclkRatioSel"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto15"
		  Position		  [495, 100, 680, 120]
		  ShowName		  off
		  GotoTag		  "regPktDet_CSMAenableIdle"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto16"
		  Position		  [495, 120, 680, 140]
		  ShowName		  off
		  GotoTag		  "regPktDet_pktDetMode"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto17"
		  Position		  [495, 140, 680, 160]
		  ShowName		  off
		  GotoTag		  "regPktDet_pktDetMask_A"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto18"
		  Position		  [495, 305, 680, 325]
		  ShowName		  off
		  GotoTag		  "regPktDet_pktDetMinDuration"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto2"
		  Position		  [495, 160, 680, 180]
		  ShowName		  off
		  GotoTag		  "regPktDet_pktDetMask_B"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto20"
		  Position		  [495, 345, 680, 365]
		  ShowName		  off
		  GotoTag		  "regPktDet_DIFSperiod"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto21"
		  Position		  [505, 465, 690, 485]
		  ShowName		  off
		  GotoTag		  "regPktDet_pktDetThresh"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto22"
		  Position		  [505, 505, 690, 525]
		  ShowName		  off
		  GotoTag		  "regPktDet_carrierSenseThresh"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto3"
		  Position		  [495, 180, 680, 200]
		  ShowName		  off
		  GotoTag		  "regPktDet_EnableExtDet"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  SubSystem
		  Name			  "Read-Write Register1"
		  Ports			  [0, 1]
		  Position		  [80, 34, 135, 66]
		  AttributesFormatString  "RW Reg: %<regName>"
		  AncestorBlock		  "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
		  MinAlgLoopOccurrences	  off
		  PropExecContextOutsideSubsystem off
		  RTWSystemCode		  "Auto"
		  FunctionWithSeparateData off
		  Opaque		  off
		  RequestExecContextInheritance	off
		  MaskHideContents	  off
		  MaskDescription	  "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
		  MaskPromptString	  "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
		  MaskStyleString	  "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
		  MaskTunableValueString  "off,off,off,off,off,off"
		  MaskCallbackString	  "|||||"
		  MaskEnableString	  "on,on,on,on,on,on"
		  MaskVisibilityString	  "on,on,on,on,on,on"
		  MaskToolTipString	  "on,on,on,on,on,on"
		  MaskVarAliasString	  ",,,,,"
		  MaskVariables		  "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
		  MaskInitialization	  "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
		  MaskSelfModifiable	  on
		  MaskIconFrame		  on
		  MaskIconOpaque	  on
		  MaskIconRotate	  "none"
		  MaskIconUnits		  "autoscale"
		  MaskValueString	  "'pktDet_controlBits'|Unsigned|32|0|hex2dec('78')|1"
		  MaskTabNameString	  ",,,,,"
		  System {
		    Name		    "Read-Write Register1"
		    Location		    [2, 74, 582, 375]
		    Open		    off
		    ModelBrowserVisibility  on
		    ModelBrowserWidth	    200
		    ScreenColor		    "white"
		    PaperOrientation	    "landscape"
		    PaperPositionMode	    "auto"
		    PaperType		    "usletter"
		    PaperUnits		    "inches"
		    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
		    TiledPageScale	    1
		    ShowPageBoundaries	    off
		    ZoomFactor		    "100"
		    Block {
		    BlockType		    Reference
		    Name		    "Constant"
		    Ports		    [0, 1]
		    Position		    [175, 216, 200, 234]
		    ShowName		    off
		    SourceBlock		    "xbsIndex_r4/Constant"
		    SourceType		    "Xilinx Constant Block Block"
		    arith_type		    "Boolean"
		    const		    "1"
		    n_bits		    "16"
		    bin_pt		    "14"
		    explicit_period	    on
		    period		    "sampPeriod"
		    dsp48_infoedit	    "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		    equ			    "P=C"
		    opselect		    "C"
		    inp2		    "PCIN>>17"
		    opr			    "+"
		    inp1		    "P"
		    carry		    "CIN"
		    dbl_ovrd		    off
		    has_advanced_control    "0"
		    sggui_pos		    "20,20,400,346"
		    block_type		    "constant"
		    block_version	    "8.2.02"
		    sg_icon_stat	    "25,18,0,1,white,blue,0,06094819,right"
		    sg_mask_display	    "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		    }
		    Block {
		    BlockType		    Reference
		    Name		    "From Register"
		    Ports		    [0, 1]
		    Position		    [150, 35, 195, 85]
		    ShowName		    off
		    AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		    SourceBlock		    "xbsIndex_r4/From Register"
		    SourceType		    "Xilinx Shared Memory Based From Register Block"
		    infoedit		    "Register block that reads data to a shared memory register.  Delay of one sample period."
		    shared_memory_name	    "'pktDet_controlBits_w'"
		    init		    "120"
		    period		    "sampPeriod"
		    ownership		    "Locally owned and initialized"
		    arith_type		    "Unsigned"
		    n_bits		    "32"
		    bin_pt		    "0"
		    dbl_ovrd		    off
		    xl_use_area		    off
		    xl_area		    "[0,0,0,0,0,0,0]"
		    has_advanced_control    "0"
		    sggui_pos		    "20,20,381,246"
		    block_type		    "fromreg"
		    block_version	    "8.2.02"
		    sg_icon_stat	    "45,50,0,1,white,blue,0,4b212927,right"
		    sg_mask_display	    "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		    }
		    Block {
		    BlockType		    Terminator
		    Name		    "Terminator"
		    Position		    [370, 205, 390, 225]
		    ShowName		    off
		    }
		    Block {
		    BlockType		    Reference
		    Name		    "To Register"
		    Ports		    [2, 1]
		    Position		    [270, 186, 325, 239]
		    ShowName		    off
		    AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		    SourceBlock		    "xbsIndex_r4/To Register"
		    SourceType		    "Xilinx Shared Memory Based To Register Block"
		    infoedit		    "Register block that writes data to a shared memory register.  Delay of one sample period."
		    shared_memory_name	    "'pktDet_controlBits_r'"
		    init		    "120"
		    ownership		    "Locally owned and initialized"
		    explicit_data_type	    on
		    arith_type		    "Unsigned"
		    n_bits		    "32"
		    bin_pt		    "0"
		    dbl_ovrd		    off
		    xl_use_area		    off
		    xl_area		    "[0,0,0,0,0,0,0]"
		    has_advanced_control    "0"
		    sggui_pos		    "20,20,381,270"
		    block_type		    "toreg"
		    block_version	    "8.2.02"
		    sg_icon_stat	    "55,53,1,1,white,blue,0,77cabcdf,right"
		    sg_mask_display	    "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		    }
		    Block {
		    BlockType		    Outport
		    Name		    "D"
		    Position		    [285, 53, 315, 67]
		    IconDisplay		    "Port number"
		    OutDataType		    "sfix(16)"
		    OutScaling		    "2^0"
		    }
		    Line {
		    SrcBlock		    "From Register"
		    SrcPort		    1
		    Points		    [0, 0; 35, 0]
		    Branch {
		    DstBlock		    "D"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		    }
		    }
		    Line {
		    SrcBlock		    "Constant"
		    SrcPort		    1
		    DstBlock		    "To Register"
		    DstPort		    2
		    }
		    Line {
		    SrcBlock		    "To Register"
		    SrcPort		    1
		    DstBlock		    "Terminator"
		    DstPort		    1
		    }
		  }
		}
		Block {
		  BlockType		  SubSystem
		  Name			  "Read-Write Register2"
		  Ports			  [0, 1]
		  Position		  [85, 299, 140, 331]
		  AttributesFormatString  "RW Reg: %<regName>"
		  AncestorBlock		  "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
		  MinAlgLoopOccurrences	  off
		  PropExecContextOutsideSubsystem off
		  RTWSystemCode		  "Auto"
		  FunctionWithSeparateData off
		  Opaque		  off
		  RequestExecContextInheritance	off
		  MaskHideContents	  off
		  MaskDescription	  "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
		  MaskPromptString	  "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
		  MaskStyleString	  "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
		  MaskTunableValueString  "off,off,off,off,off,off"
		  MaskCallbackString	  "|||||"
		  MaskEnableString	  "on,on,on,on,on,on"
		  MaskVisibilityString	  "on,on,on,on,on,on"
		  MaskToolTipString	  "on,on,on,on,on,on"
		  MaskVarAliasString	  ",,,,,"
		  MaskVariables		  "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
		  MaskInitialization	  "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
		  MaskSelfModifiable	  on
		  MaskIconFrame		  on
		  MaskIconOpaque	  on
		  MaskIconRotate	  "none"
		  MaskIconUnits		  "autoscale"
		  MaskValueString	  "'pktDet_durations'|Unsigned|32|0|(48 * 2^0) + (1000 * 2^11) + (16 * 2^21)|1"
		  MaskTabNameString	  ",,,,,"
		  System {
		    Name		    "Read-Write Register2"
		    Location		    [2, 74, 582, 375]
		    Open		    off
		    ModelBrowserVisibility  on
		    ModelBrowserWidth	    200
		    ScreenColor		    "white"
		    PaperOrientation	    "landscape"
		    PaperPositionMode	    "auto"
		    PaperType		    "usletter"
		    PaperUnits		    "inches"
		    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
		    TiledPageScale	    1
		    ShowPageBoundaries	    off
		    ZoomFactor		    "100"
		    Block {
		    BlockType		    Reference
		    Name		    "Constant"
		    Ports		    [0, 1]
		    Position		    [175, 216, 200, 234]
		    ShowName		    off
		    SourceBlock		    "xbsIndex_r4/Constant"
		    SourceType		    "Xilinx Constant Block Block"
		    arith_type		    "Boolean"
		    const		    "1"
		    n_bits		    "16"
		    bin_pt		    "14"
		    explicit_period	    on
		    period		    "sampPeriod"
		    dsp48_infoedit	    "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		    equ			    "P=C"
		    opselect		    "C"
		    inp2		    "PCIN>>17"
		    opr			    "+"
		    inp1		    "P"
		    carry		    "CIN"
		    dbl_ovrd		    off
		    has_advanced_control    "0"
		    sggui_pos		    "20,20,400,346"
		    block_type		    "constant"
		    block_version	    "8.2.02"
		    sg_icon_stat	    "25,18,0,1,white,blue,0,06094819,right"
		    sg_mask_display	    "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		    }
		    Block {
		    BlockType		    Reference
		    Name		    "From Register"
		    Ports		    [0, 1]
		    Position		    [150, 35, 195, 85]
		    ShowName		    off
		    AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		    SourceBlock		    "xbsIndex_r4/From Register"
		    SourceType		    "Xilinx Shared Memory Based From Register Block"
		    infoedit		    "Register block that reads data to a shared memory register.  Delay of one sample period."
		    shared_memory_name	    "'pktDet_durations_w'"
		    init		    "35602480"
		    period		    "sampPeriod"
		    ownership		    "Locally owned and initialized"
		    arith_type		    "Unsigned"
		    n_bits		    "32"
		    bin_pt		    "0"
		    dbl_ovrd		    off
		    xl_use_area		    off
		    xl_area		    "[0,0,0,0,0,0,0]"
		    has_advanced_control    "0"
		    sggui_pos		    "20,20,381,246"
		    block_type		    "fromreg"
		    block_version	    "8.2.02"
		    sg_icon_stat	    "45,50,0,1,white,blue,0,4b212927,right"
		    sg_mask_display	    "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		    }
		    Block {
		    BlockType		    Terminator
		    Name		    "Terminator"
		    Position		    [370, 205, 390, 225]
		    ShowName		    off
		    }
		    Block {
		    BlockType		    Reference
		    Name		    "To Register"
		    Ports		    [2, 1]
		    Position		    [270, 186, 325, 239]
		    ShowName		    off
		    AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		    SourceBlock		    "xbsIndex_r4/To Register"
		    SourceType		    "Xilinx Shared Memory Based To Register Block"
		    infoedit		    "Register block that writes data to a shared memory register.  Delay of one sample period."
		    shared_memory_name	    "'pktDet_durations_r'"
		    init		    "35602480"
		    ownership		    "Locally owned and initialized"
		    explicit_data_type	    on
		    arith_type		    "Unsigned"
		    n_bits		    "32"
		    bin_pt		    "0"
		    dbl_ovrd		    off
		    xl_use_area		    off
		    xl_area		    "[0,0,0,0,0,0,0]"
		    has_advanced_control    "0"
		    sggui_pos		    "20,20,381,270"
		    block_type		    "toreg"
		    block_version	    "8.2.02"
		    sg_icon_stat	    "55,53,1,1,white,blue,0,77cabcdf,right"
		    sg_mask_display	    "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		    }
		    Block {
		    BlockType		    Outport
		    Name		    "D"
		    Position		    [285, 53, 315, 67]
		    IconDisplay		    "Port number"
		    OutDataType		    "sfix(16)"
		    OutScaling		    "2^0"
		    }
		    Line {
		    SrcBlock		    "To Register"
		    SrcPort		    1
		    DstBlock		    "Terminator"
		    DstPort		    1
		    }
		    Line {
		    SrcBlock		    "Constant"
		    SrcPort		    1
		    DstBlock		    "To Register"
		    DstPort		    2
		    }
		    Line {
		    SrcBlock		    "From Register"
		    SrcPort		    1
		    Points		    [0, 0; 35, 0]
		    Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		    }
		    Branch {
		    DstBlock		    "D"
		    DstPort		    1
		    }
		    }
		  }
		}
		Block {
		  BlockType		  SubSystem
		  Name			  "Read-Write Register5"
		  Ports			  [0, 1]
		  Position		  [100, 459, 155, 491]
		  AttributesFormatString  "RW Reg: %<regName>"
		  AncestorBlock		  "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
		  MinAlgLoopOccurrences	  off
		  PropExecContextOutsideSubsystem off
		  RTWSystemCode		  "Auto"
		  FunctionWithSeparateData off
		  Opaque		  off
		  RequestExecContextInheritance	off
		  MaskHideContents	  off
		  MaskDescription	  "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
		  MaskPromptString	  "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
		  MaskStyleString	  "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
		  MaskTunableValueString  "off,off,off,off,off,off"
		  MaskCallbackString	  "|||||"
		  MaskEnableString	  "on,on,on,on,on,on"
		  MaskVisibilityString	  "on,on,on,on,on,on"
		  MaskToolTipString	  "on,on,on,on,on,on"
		  MaskVarAliasString	  ",,,,,"
		  MaskVariables		  "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
		  MaskInitialization	  "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
		  MaskSelfModifiable	  on
		  MaskIconFrame		  on
		  MaskIconOpaque	  on
		  MaskIconRotate	  "none"
		  MaskIconUnits		  "autoscale"
		  MaskValueString	  "'pktDet_thresholds'|Unsigned|32|0|(3000 * 2^0) + (3000 * 2^16)|1"
		  MaskTabNameString	  ",,,,,"
		  System {
		    Name		    "Read-Write Register5"
		    Location		    [2, 74, 582, 375]
		    Open		    off
		    ModelBrowserVisibility  on
		    ModelBrowserWidth	    200
		    ScreenColor		    "white"
		    PaperOrientation	    "landscape"
		    PaperPositionMode	    "auto"
		    PaperType		    "usletter"
		    PaperUnits		    "inches"
		    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
		    TiledPageScale	    1
		    ShowPageBoundaries	    off
		    ZoomFactor		    "100"
		    Block {
		    BlockType		    Reference
		    Name		    "Constant"
		    Ports		    [0, 1]
		    Position		    [175, 216, 200, 234]
		    ShowName		    off
		    SourceBlock		    "xbsIndex_r4/Constant"
		    SourceType		    "Xilinx Constant Block Block"
		    arith_type		    "Boolean"
		    const		    "1"
		    n_bits		    "16"
		    bin_pt		    "14"
		    explicit_period	    on
		    period		    "sampPeriod"
		    dsp48_infoedit	    "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		    equ			    "P=C"
		    opselect		    "C"
		    inp2		    "PCIN>>17"
		    opr			    "+"
		    inp1		    "P"
		    carry		    "CIN"
		    dbl_ovrd		    off
		    has_advanced_control    "0"
		    sggui_pos		    "20,20,400,346"
		    block_type		    "constant"
		    block_version	    "8.2.02"
		    sg_icon_stat	    "25,18,0,1,white,blue,0,06094819,right"
		    sg_mask_display	    "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		    }
		    Block {
		    BlockType		    Reference
		    Name		    "From Register"
		    Ports		    [0, 1]
		    Position		    [150, 35, 195, 85]
		    ShowName		    off
		    AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		    SourceBlock		    "xbsIndex_r4/From Register"
		    SourceType		    "Xilinx Shared Memory Based From Register Block"
		    infoedit		    "Register block that reads data to a shared memory register.  Delay of one sample period."
		    shared_memory_name	    "'pktDet_thresholds_w'"
		    init		    "196611000"
		    period		    "sampPeriod"
		    ownership		    "Locally owned and initialized"
		    arith_type		    "Unsigned"
		    n_bits		    "32"
		    bin_pt		    "0"
		    dbl_ovrd		    off
		    xl_use_area		    off
		    xl_area		    "[0,0,0,0,0,0,0]"
		    has_advanced_control    "0"
		    sggui_pos		    "20,20,381,246"
		    block_type		    "fromreg"
		    block_version	    "8.2.02"
		    sg_icon_stat	    "45,50,0,1,white,blue,0,4b212927,right"
		    sg_mask_display	    "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		    }
		    Block {
		    BlockType		    Terminator
		    Name		    "Terminator"
		    Position		    [370, 205, 390, 225]
		    ShowName		    off
		    }
		    Block {
		    BlockType		    Reference
		    Name		    "To Register"
		    Ports		    [2, 1]
		    Position		    [270, 186, 325, 239]
		    ShowName		    off
		    AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		    SourceBlock		    "xbsIndex_r4/To Register"
		    SourceType		    "Xilinx Shared Memory Based To Register Block"
		    infoedit		    "Register block that writes data to a shared memory register.  Delay of one sample period."
		    shared_memory_name	    "'pktDet_thresholds_r'"
		    init		    "196611000"
		    ownership		    "Locally owned and initialized"
		    explicit_data_type	    on
		    arith_type		    "Unsigned"
		    n_bits		    "32"
		    bin_pt		    "0"
		    dbl_ovrd		    off
		    xl_use_area		    off
		    xl_area		    "[0,0,0,0,0,0,0]"
		    has_advanced_control    "0"
		    sggui_pos		    "20,20,381,270"
		    block_type		    "toreg"
		    block_version	    "8.2.02"
		    sg_icon_stat	    "55,53,1,1,white,blue,0,77cabcdf,right"
		    sg_mask_display	    "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		    }
		    Block {
		    BlockType		    Outport
		    Name		    "D"
		    Position		    [285, 53, 315, 67]
		    IconDisplay		    "Port number"
		    OutDataType		    "sfix(16)"
		    OutScaling		    "2^0"
		    }
		    Line {
		    SrcBlock		    "From Register"
		    SrcPort		    1
		    Points		    [0, 0; 35, 0]
		    Branch {
		    DstBlock		    "D"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		    }
		    }
		    Line {
		    SrcBlock		    "Constant"
		    SrcPort		    1
		    DstBlock		    "To Register"
		    DstPort		    2
		    }
		    Line {
		    SrcBlock		    "To Register"
		    SrcPort		    1
		    DstBlock		    "Terminator"
		    DstPort		    1
		    }
		  }
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice1"
		  Ports			  [1, 1]
		  Position		  [235, 181, 270, 199]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "7"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice10"
		  Ports			  [1, 1]
		  Position		  [235, 41, 270, 59]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "0"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice11"
		  Ports			  [1, 1]
		  Position		  [235, 61, 270, 79]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "1"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice12"
		  Ports			  [1, 1]
		  Position		  [235, 81, 270, 99]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "2"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice13"
		  Ports			  [1, 1]
		  Position		  [235, 101, 270, 119]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "3"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice14"
		  Ports			  [1, 1]
		  Position		  [235, 121, 270, 139]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "4"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice15"
		  Ports			  [1, 1]
		  Position		  [235, 161, 270, 179]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "6"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice16"
		  Ports			  [1, 1]
		  Position		  [235, 141, 270, 159]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "5"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [725, 545, 745, 565]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [625, 612, 685, 668]
		  AttributesFormatString  "<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'pktDet_status'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "14"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,266"
		  block_type		  "toreg"
		  block_version		  "10.1.3"
		  sg_icon_stat		  "60,56,2,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Up Sample1"
		  Ports			  [1, 1]
		  Position		  [245, 636, 270, 654]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Up Sample"
		  SourceType		  "Xilinx Up Sampler Block"
		  infoedit		  "Up samples input data.  Inserted values  can be zeros or copies of the most recent input sample.<P><P>Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a mux and single bit flip-flop are used."
		  sample_ratio		  "4"
		  copy_samples		  "on"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,263"
		  block_type		  "usamp"
		  block_version		  "8.2"
		  sg_icon_stat		  "25,18,1,1,white,blue,0,b6c489dd,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 54 54 ],[0.77 0.82 0.91]);\npatch([16 7 20 7 16 30 34 38 53 41 29 21 35 21 29 41 53 38 34 30 16 ],[6 15 28 41 50 50 46 50 50 38 50 42 28 14 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 54 54 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('{\\fontsize{14pt}\\bf\\uparrow}4','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Up Sample2"
		  Ports			  [1, 1]
		  Position		  [245, 616, 270, 634]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Up Sample"
		  SourceType		  "Xilinx Up Sampler Block"
		  infoedit		  "Up samples input data.  Inserted values  can be zeros or copies of the most recent input sample.<P><P>Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a mux and single bit flip-flop are used."
		  sample_ratio		  "4"
		  copy_samples		  "on"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,263"
		  block_type		  "usamp"
		  block_version		  "8.2"
		  sg_icon_stat		  "25,18,1,1,white,blue,0,b6c489dd,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 54 54 ],[0.77 0.82 0.91]);\npatch([16 7 20 7 16 30 34 38 53 41 29 21 35 21 29 41 53 38 34 30 16 ],[6 15 28 41 50 50 46 50 50 38 50 42 28 14 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 54 54 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('{\\fontsize{14pt}\\bf\\uparrow}4','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Up Sample4"
		  Ports			  [1, 1]
		  Position		  [245, 576, 270, 594]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Up Sample"
		  SourceType		  "Xilinx Up Sampler Block"
		  infoedit		  "Up samples input data.  Inserted values  can be zeros or copies of the most recent input sample.<P><P>Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a mux and single bit flip-flop are used."
		  sample_ratio		  "4"
		  copy_samples		  "on"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,263"
		  block_type		  "usamp"
		  block_version		  "8.2"
		  sg_icon_stat		  "25,18,1,1,white,blue,0,b6c489dd,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 54 54 ],[0.77 0.82 0.91]);\npatch([16 7 20 7 16 30 34 38 53 41 29 21 35 21 29 41 53 38 34 30 16 ],[6 15 28 41 50 50 46 50 50 38 50 42 28 14 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 54 54 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('{\\fontsize{14pt}\\bf\\uparrow}4','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "Read-Write Register1"
		  SrcPort		  1
		  Points		  [65, 0]
		  Branch {
		    DstBlock		    "Slice10"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 20]
		    Branch {
		    DstBlock		    "Slice11"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    DstBlock		    "Slice12"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    DstBlock		    "Slice13"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    DstBlock		    "Slice14"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    DstBlock		    "Slice16"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    DstBlock		    "Slice15"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 20]
		    DstBlock		    "Slice1"
		    DstPort		    1
		    }
		    }
		    }
		    }
		    }
		    }
		  }
		}
		Line {
		  SrcBlock		  "Slice10"
		  SrcPort		  1
		  DstBlock		  "Down Sample11"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice11"
		  SrcPort		  1
		  DstBlock		  "Down Sample10"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice12"
		  SrcPort		  1
		  DstBlock		  "Down Sample9"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice13"
		  SrcPort		  1
		  DstBlock		  "Down Sample8"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice14"
		  SrcPort		  1
		  DstBlock		  "Down Sample7"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Read-Write Register2"
		  SrcPort		  1
		  Points		  [60, 0]
		  Branch {
		    DstBlock		    "11LSB"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 40]
		    Branch {
		    DstBlock		    "10LSB + 11"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 40]
		    DstBlock		    "5LSB + 21"
		    DstPort		    1
		    }
		  }
		}
		Line {
		  SrcBlock		  "11LSB"
		  SrcPort		  1
		  DstBlock		  "Down Sample6"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "10LSB + 11"
		  SrcPort		  1
		  DstBlock		  "Down Sample1"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample6"
		  SrcPort		  1
		  DstBlock		  "Goto18"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample1"
		  SrcPort		  1
		  DstBlock		  "Goto20"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "5LSB + 21"
		  SrcPort		  1
		  DstBlock		  "Down Sample2"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample2"
		  SrcPort		  1
		  DstBlock		  "Goto1"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Read-Write Register5"
		  SrcPort		  1
		  Points		  [45, 0]
		  Branch {
		    DstBlock		    "16LSB"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 40]
		    DstBlock		    "16MSB"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "16LSB"
		  SrcPort		  1
		  DstBlock		  "Down Sample3"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample3"
		  SrcPort		  1
		  DstBlock		  "Goto21"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "16MSB"
		  SrcPort		  1
		  DstBlock		  "Down Sample4"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample4"
		  SrcPort		  1
		  DstBlock		  "Goto22"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample5"
		  SrcPort		  1
		  DstBlock		  "Goto17"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample7"
		  SrcPort		  1
		  DstBlock		  "Goto16"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample8"
		  SrcPort		  1
		  DstBlock		  "Goto15"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample9"
		  SrcPort		  1
		  DstBlock		  "Goto14"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample10"
		  SrcPort		  1
		  DstBlock		  "Goto12"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample11"
		  SrcPort		  1
		  DstBlock		  "Goto13"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice16"
		  SrcPort		  1
		  DstBlock		  "Down Sample5"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice15"
		  SrcPort		  1
		  DstBlock		  "Down Sample12"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample12"
		  SrcPort		  1
		  DstBlock		  "Goto2"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "Concat"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "From4"
		  SrcPort		  1
		  DstBlock		  "Convert4"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "From1"
		  SrcPort		  1
		  DstBlock		  "Up Sample1"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "From2"
		  SrcPort		  1
		  DstBlock		  "Up Sample2"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant1"
		  SrcPort		  1
		  DstBlock		  "Convert1"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "From3"
		  SrcPort		  1
		  DstBlock		  "Up Sample4"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Up Sample4"
		  SrcPort		  1
		  DstBlock		  "Concat"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Up Sample2"
		  SrcPort		  1
		  DstBlock		  "Convert2"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Up Sample1"
		  SrcPort		  1
		  DstBlock		  "Convert3"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Convert1"
		  SrcPort		  1
		  DstBlock		  "Concat"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "Convert2"
		  SrcPort		  1
		  DstBlock		  "Concat"
		  DstPort		  3
		}
		Line {
		  SrcBlock		  "Convert3"
		  SrcPort		  1
		  DstBlock		  "Concat"
		  DstPort		  4
		}
		Line {
		  SrcBlock		  "Convert4"
		  SrcPort		  1
		  DstBlock		  "Concat"
		  DstPort		  5
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  Points		  [0, -85]
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice1"
		  SrcPort		  1
		  DstBlock		  "Down Sample13"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample13"
		  SrcPort		  1
		  DstBlock		  "Goto3"
		  DstPort		  1
		}
		Annotation {
		  Name			  "0x1"
		  Position		  [707, 49]
		}
		Annotation {
		  Name			  "0x2"
		  Position		  [707, 69]
		}
		Annotation {
		  Name			  "0x4"
		  Position		  [707, 89]
		}
		Annotation {
		  Name			  "0x8"
		  Position		  [707, 109]
		}
		Annotation {
		  Name			  "0x10"
		  Position		  [712, 129]
		}
		Annotation {
		  Name			  "LSB"
		  Position		  [250, 29]
		}
		Annotation {
		  Name			  "0x20"
		  Position		  [712, 149]
		}
		Annotation {
		  Name			  "0x40"
		  Position		  [712, 169]
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read Only Register"
	      Ports		      [2]
	      Position		      [1570, 36, 1620, 69]
	      AttributesFormatString  "RO Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's To Register shared memory block. This register is designed for use with WARP's sysgen2opb tool.\n\nNote: The Regisger Name paramter below must be unique for every instance of Read-Write and Read-Only registers in your system."
	      MaskPromptString	      "Register Name"
	      MaskStyleString	      "edit"
	      MaskTunableValueString  "off"
	      MaskEnableString	      "on"
	      MaskVisibilityString    "on"
	      MaskToolTipString	      "on"
	      MaskVariables	      "regName=&1;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on',   'block_type', 'toreg');\n\nif(length(regBlock) > 0)\n\n    %Set the shared memory name\n    set_param(regBlock{1}, 'shared_memory_name', regName);\n\n	set_param(regBlock{1}, 'explicit_data_type', 'on')\n    set_param(regBlock{1}, 'arith_type', 'unsigned');\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', '32');\n	set_param(regBlock{1}, 'bin_pt', '0');\n	set_param(regBlock{1}, 'init', '0');\nend\n\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_Gains'"
	      System {
		Name			"Read Only Register"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Inport
		  Name			  "D"
		  Position		  [15, 183, 45, 197]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Inport
		  Name			  "En"
		  Position		  [15, 223, 45, 237]
		  Port			  "2"
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert"
		  Ports			  [1, 1]
		  Position		  [180, 175, 225, 205]
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  off
		  pipeline		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1"
		  sg_icon_stat		  "45,30,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Reinterpret"
		  Ports			  [1, 1]
		  Position		  [90, 174, 140, 206]
		  SourceBlock		  "xbsIndex_r4/Reinterpret"
		  SourceType		  "Xilinx Type Reinterpreter Block"
		  infoedit		  "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
		  force_arith_type	  on
		  arith_type		  "Unsigned"
		  force_bin_pt		  on
		  bin_pt		  "0"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,312"
		  block_type		  "reinterpret"
		  block_version		  "10.1"
		  sg_icon_stat		  "50,32,1,1,white,blue,0,8982c1db,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [410, 195, 430, 215]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [310, 176, 365, 229]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_Gains'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,2,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "En"
		  SrcPort		  1
		  Points		  [215, 0; 0, -15]
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "D"
		  SrcPort		  1
		  DstBlock		  "Reinterpret"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Reinterpret"
		  SrcPort		  1
		  DstBlock		  "Convert"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Convert"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read Only Register1"
	      Ports		      [2]
	      Position		      [1565, 126, 1615, 159]
	      AttributesFormatString  "RO Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's To Register shared memory block. This register is designed for use with WARP's sysgen2opb tool.\n\nNote: The Regisger Name paramter below must be unique for every instance of Read-Write and Read-Only registers in your system."
	      MaskPromptString	      "Register Name"
	      MaskStyleString	      "edit"
	      MaskTunableValueString  "off"
	      MaskEnableString	      "on"
	      MaskVisibilityString    "on"
	      MaskToolTipString	      "on"
	      MaskVariables	      "regName=&1;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on',   'block_type', 'toreg');\n\nif(length(regBlock) > 0)\n\n    %Set the shared memory name\n    set_param(regBlock{1}, 'shared_memory_name', regName);\n\n	set_param(regBlock{1}, 'explicit_data_type', 'on')\n    set_param(regBlock{1}, 'arith_type', 'unsigned');\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', '32');\n	set_param(regBlock{1}, 'bin_pt', '0');\n	set_param(regBlock{1}, 'init', '0');\nend\n\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_BER_Errors'"
	      System {
		Name			"Read Only Register1"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Inport
		  Name			  "D"
		  Position		  [15, 183, 45, 197]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Inport
		  Name			  "En"
		  Position		  [15, 223, 45, 237]
		  Port			  "2"
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert"
		  Ports			  [1, 1]
		  Position		  [180, 175, 225, 205]
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  off
		  pipeline		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1"
		  sg_icon_stat		  "45,30,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Reinterpret"
		  Ports			  [1, 1]
		  Position		  [90, 174, 140, 206]
		  SourceBlock		  "xbsIndex_r4/Reinterpret"
		  SourceType		  "Xilinx Type Reinterpreter Block"
		  infoedit		  "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
		  force_arith_type	  on
		  arith_type		  "Unsigned"
		  force_bin_pt		  on
		  bin_pt		  "0"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,312"
		  block_type		  "reinterpret"
		  block_version		  "10.1"
		  sg_icon_stat		  "50,32,1,1,white,blue,0,8982c1db,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [410, 195, 430, 215]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [310, 176, 365, 229]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_BER_Errors'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,2,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "En"
		  SrcPort		  1
		  Points		  [215, 0; 0, -15]
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "D"
		  SrcPort		  1
		  DstBlock		  "Reinterpret"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Reinterpret"
		  SrcPort		  1
		  DstBlock		  "Convert"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Convert"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read Only Register2"
	      Ports		      [2]
	      Position		      [1565, 211, 1615, 244]
	      AttributesFormatString  "RO Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's To Register shared memory block. This register is designed for use with WARP's sysgen2opb tool.\n\nNote: The Regisger Name paramter below must be unique for every instance of Read-Write and Read-Only registers in your system."
	      MaskPromptString	      "Register Name"
	      MaskStyleString	      "edit"
	      MaskTunableValueString  "off"
	      MaskEnableString	      "on"
	      MaskVisibilityString    "on"
	      MaskToolTipString	      "on"
	      MaskVariables	      "regName=&1;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on',   'block_type', 'toreg');\n\nif(length(regBlock) > 0)\n\n    %Set the shared memory name\n    set_param(regBlock{1}, 'shared_memory_name', regName);\n\n	set_param(regBlock{1}, 'explicit_data_type', 'on')\n    set_param(regBlock{1}, 'arith_type', 'unsigned');\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', '32');\n	set_param(regBlock{1}, 'bin_pt', '0');\n	set_param(regBlock{1}, 'init', '0');\nend\n\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_BER_TotalBits'"
	      System {
		Name			"Read Only Register2"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Inport
		  Name			  "D"
		  Position		  [15, 183, 45, 197]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Inport
		  Name			  "En"
		  Position		  [15, 223, 45, 237]
		  Port			  "2"
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert"
		  Ports			  [1, 1]
		  Position		  [180, 175, 225, 205]
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  off
		  pipeline		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1"
		  sg_icon_stat		  "45,30,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Reinterpret"
		  Ports			  [1, 1]
		  Position		  [90, 174, 140, 206]
		  SourceBlock		  "xbsIndex_r4/Reinterpret"
		  SourceType		  "Xilinx Type Reinterpreter Block"
		  infoedit		  "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
		  force_arith_type	  on
		  arith_type		  "Unsigned"
		  force_bin_pt		  on
		  bin_pt		  "0"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,312"
		  block_type		  "reinterpret"
		  block_version		  "10.1"
		  sg_icon_stat		  "50,32,1,1,white,blue,0,8982c1db,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [410, 195, 430, 215]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [310, 176, 365, 229]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_BER_TotalBits'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,2,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "En"
		  SrcPort		  1
		  Points		  [215, 0; 0, -15]
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "D"
		  SrcPort		  1
		  DstBlock		  "Reinterpret"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Reinterpret"
		  SrcPort		  1
		  DstBlock		  "Convert"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Convert"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read Only Register3"
	      Ports		      [2]
	      Position		      [1565, 311, 1615, 344]
	      AttributesFormatString  "RO Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's To Register shared memory block. This register is designed for use with WARP's sysgen2opb tool.\n\nNote: The Regisger Name paramter below must be unique for every instance of Read-Write and Read-Only registers in your system."
	      MaskPromptString	      "Register Name"
	      MaskStyleString	      "edit"
	      MaskTunableValueString  "off"
	      MaskEnableString	      "on"
	      MaskVisibilityString    "on"
	      MaskToolTipString	      "on"
	      MaskVariables	      "regName=&1;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on',   'block_type', 'toreg');\n\nif(length(regBlock) > 0)\n\n    %Set the shared memory name\n    set_param(regBlock{1}, 'shared_memory_name', regName);\n\n	set_param(regBlock{1}, 'explicit_data_type', 'on')\n    set_param(regBlock{1}, 'arith_type', 'unsigned');\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', '32');\n	set_param(regBlock{1}, 'bin_pt', '0');\n	set_param(regBlock{1}, 'init', '0');\nend\n\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_pktDone_interruptStatus'"
	      System {
		Name			"Read Only Register3"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Inport
		  Name			  "D"
		  Position		  [15, 183, 45, 197]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Inport
		  Name			  "En"
		  Position		  [15, 223, 45, 237]
		  Port			  "2"
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert"
		  Ports			  [1, 1]
		  Position		  [180, 175, 225, 205]
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  off
		  pipeline		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1"
		  sg_icon_stat		  "45,30,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Reinterpret"
		  Ports			  [1, 1]
		  Position		  [90, 174, 140, 206]
		  SourceBlock		  "xbsIndex_r4/Reinterpret"
		  SourceType		  "Xilinx Type Reinterpreter Block"
		  infoedit		  "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
		  force_arith_type	  on
		  arith_type		  "Unsigned"
		  force_bin_pt		  on
		  bin_pt		  "0"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,312"
		  block_type		  "reinterpret"
		  block_version		  "10.1"
		  sg_icon_stat		  "50,32,1,1,white,blue,0,8982c1db,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [410, 195, 430, 215]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [310, 176, 365, 229]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_pktDone_interruptStatus'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,2,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "En"
		  SrcPort		  1
		  Points		  [215, 0; 0, -15]
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "D"
		  SrcPort		  1
		  DstBlock		  "Reinterpret"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Reinterpret"
		  SrcPort		  1
		  DstBlock		  "Convert"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Convert"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read Only Register4"
	      Ports		      [2]
	      Position		      [1565, 416, 1615, 449]
	      AttributesFormatString  "RO Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's To Register shared memory block. This register is designed for use with WARP's sysgen2opb tool.\n\nNote: The Regisger Name paramter below must be unique for every instance of Read-Write and Read-Only registers in your system."
	      MaskPromptString	      "Register Name"
	      MaskStyleString	      "edit"
	      MaskTunableValueString  "off"
	      MaskEnableString	      "on"
	      MaskVisibilityString    "on"
	      MaskToolTipString	      "on"
	      MaskVariables	      "regName=&1;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on',   'block_type', 'toreg');\n\nif(length(regBlock) > 0)\n\n    %Set the shared memory name\n    set_param(regBlock{1}, 'shared_memory_name', regName);\n\n	set_param(regBlock{1}, 'explicit_data_type', 'on')\n    set_param(regBlock{1}, 'arith_type', 'unsigned');\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', '32');\n	set_param(regBlock{1}, 'bin_pt', '0');\n	set_param(regBlock{1}, 'init', '0');\nend\n\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_pilotCFOest'"
	      System {
		Name			"Read Only Register4"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Inport
		  Name			  "D"
		  Position		  [15, 183, 45, 197]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Inport
		  Name			  "En"
		  Position		  [15, 223, 45, 237]
		  Port			  "2"
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert"
		  Ports			  [1, 1]
		  Position		  [180, 175, 225, 205]
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  off
		  pipeline		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1"
		  sg_icon_stat		  "45,30,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Reinterpret"
		  Ports			  [1, 1]
		  Position		  [90, 174, 140, 206]
		  SourceBlock		  "xbsIndex_r4/Reinterpret"
		  SourceType		  "Xilinx Type Reinterpreter Block"
		  infoedit		  "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
		  force_arith_type	  on
		  arith_type		  "Unsigned"
		  force_bin_pt		  on
		  bin_pt		  "0"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,312"
		  block_type		  "reinterpret"
		  block_version		  "10.1"
		  sg_icon_stat		  "50,32,1,1,white,blue,0,8982c1db,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [410, 195, 430, 215]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [310, 176, 365, 229]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_pilotCFOest'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,2,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "Convert"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Reinterpret"
		  SrcPort		  1
		  DstBlock		  "Convert"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "D"
		  SrcPort		  1
		  DstBlock		  "Reinterpret"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "En"
		  SrcPort		  1
		  Points		  [215, 0; 0, -15]
		  DstBlock		  "To Register"
		  DstPort		  2
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read Only Register5"
	      Ports		      [2]
	      Position		      [1565, 501, 1615, 534]
	      AttributesFormatString  "RO Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's To Register shared memory block. This register is designed for use with WARP's sysgen2opb tool.\n\nNote: The Regisger Name paramter below must be unique for every instance of Read-Write and Read-Only registers in your system."
	      MaskPromptString	      "Register Name"
	      MaskStyleString	      "edit"
	      MaskTunableValueString  "off"
	      MaskEnableString	      "on"
	      MaskVisibilityString    "on"
	      MaskToolTipString	      "on"
	      MaskVariables	      "regName=&1;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on',   'block_type', 'toreg');\n\nif(length(regBlock) > 0)\n\n    %Set the shared memory name\n    set_param(regBlock{1}, 'shared_memory_name', regName);\n\n	set_param(regBlock{1}, 'explicit_data_type', 'on')\n    set_param(regBlock{1}, 'arith_type', 'unsigned');\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', '32');\n	set_param(regBlock{1}, 'bin_pt', '0');\n	set_param(regBlock{1}, 'init', '0');\nend\n\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_coarseCFOest'"
	      System {
		Name			"Read Only Register5"
		Location		[202, 74, 1670, 1006]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Inport
		  Name			  "D"
		  Position		  [15, 183, 45, 197]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Inport
		  Name			  "En"
		  Position		  [15, 223, 45, 237]
		  Port			  "2"
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert"
		  Ports			  [1, 1]
		  Position		  [180, 175, 225, 205]
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  off
		  pipeline		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1"
		  sg_icon_stat		  "45,30,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Reinterpret"
		  Ports			  [1, 1]
		  Position		  [90, 174, 140, 206]
		  SourceBlock		  "xbsIndex_r4/Reinterpret"
		  SourceType		  "Xilinx Type Reinterpreter Block"
		  infoedit		  "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
		  force_arith_type	  on
		  arith_type		  "Unsigned"
		  force_bin_pt		  on
		  bin_pt		  "0"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,312"
		  block_type		  "reinterpret"
		  block_version		  "10.1"
		  sg_icon_stat		  "50,32,1,1,white,blue,0,8982c1db,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [410, 195, 430, 215]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [310, 176, 365, 229]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_coarseCFOest'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,2,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "En"
		  SrcPort		  1
		  Points		  [215, 0; 0, -15]
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "D"
		  SrcPort		  1
		  DstBlock		  "Reinterpret"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Reinterpret"
		  SrcPort		  1
		  DstBlock		  "Convert"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Convert"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read Only Register6"
	      Ports		      [2]
	      Position		      [1565, 571, 1615, 604]
	      AttributesFormatString  "RO Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's To Register shared memory block. This register is designed for use with WARP's sysgen2opb tool.\n\nNote: The Regisger Name paramter below must be unique for every instance of Read-Write and Read-Only registers in your system."
	      MaskPromptString	      "Register Name"
	      MaskStyleString	      "edit"
	      MaskTunableValueString  "off"
	      MaskEnableString	      "on"
	      MaskVisibilityString    "on"
	      MaskToolTipString	      "on"
	      MaskVariables	      "regName=&1;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on',   'block_type', 'toreg');\n\nif(length(regBlock) > 0)\n\n    %Set the shared memory name\n    set_param(regBlock{1}, 'shared_memory_name', regName);\n\n	set_param(regBlock{1}, 'explicit_data_type', 'on')\n    set_param(regBlock{1}, 'arith_type', 'unsigned');\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', '32');\n	set_param(regBlock{1}, 'bin_pt', '0');\n	set_param(regBlock{1}, 'init', '0');\nend\n\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_pktDetEventCount'"
	      System {
		Name			"Read Only Register6"
		Location		[202, 74, 1670, 1006]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Inport
		  Name			  "D"
		  Position		  [15, 183, 45, 197]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Inport
		  Name			  "En"
		  Position		  [15, 223, 45, 237]
		  Port			  "2"
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert"
		  Ports			  [1, 1]
		  Position		  [180, 175, 225, 205]
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  off
		  pipeline		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1"
		  sg_icon_stat		  "45,30,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Reinterpret"
		  Ports			  [1, 1]
		  Position		  [90, 174, 140, 206]
		  SourceBlock		  "xbsIndex_r4/Reinterpret"
		  SourceType		  "Xilinx Type Reinterpreter Block"
		  infoedit		  "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
		  force_arith_type	  on
		  arith_type		  "Unsigned"
		  force_bin_pt		  on
		  bin_pt		  "0"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,312"
		  block_type		  "reinterpret"
		  block_version		  "10.1"
		  sg_icon_stat		  "50,32,1,1,white,blue,0,8982c1db,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [410, 195, 430, 215]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [310, 176, 365, 229]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_pktDetEventCount'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,2,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "Convert"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Reinterpret"
		  SrcPort		  1
		  DstBlock		  "Convert"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "D"
		  SrcPort		  1
		  DstBlock		  "Reinterpret"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "En"
		  SrcPort		  1
		  Points		  [215, 0; 0, -15]
		  DstBlock		  "To Register"
		  DstPort		  2
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register"
	      Ports		      [0, 1]
	      Position		      [60, 29, 115, 61]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_ControlBits'|Unsigned|32|0|rx_controlBits|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register"
		Location		[2, 74, 582, 375]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_ControlBits_w'"
		  init			  "572069862"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_ControlBits_r'"
		  init			  "572069862"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register1"
	      Ports		      [0, 1]
	      Position		      [720, 454, 775, 486]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_PktDet_LongCorr_Params'|Unsigned|32|0|Rx_PktDet_LongCorr_Params|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register1"
		Location		[2, 74, 582, 375]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_PktDet_LongCorr_Params_w'"
		  init			  "4278190325"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_PktDet_LongCorr_Params_r'"
		  init			  "4278190325"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register2"
	      Ports		      [0, 1]
	      Position		      [60, 204, 115, 236]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_pktByteNums'|Unsigned|32|0|pktByteNums|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register2"
		Location		[2, 74, 582, 375]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_pktByteNums_w'"
		  init			  "131864"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_pktByteNums_r'"
		  init			  "131864"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register3"
	      Ports		      [0, 1]
	      Position		      [55, 284, 110, 316]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_PktDet_Delay'|Unsigned|32|0|PktDet_Delay|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register3"
		Location		[2, 74, 582, 375]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_PktDet_Delay_w'"
		  init			  "1962935642"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_PktDet_Delay_r'"
		  init			  "1962935642"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Reinterpret1"
	      Ports		      [1, 1]
	      Position		      [870, 225, 915, 245]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Reinterpret"
	      SourceType	      "Xilinx Type Reinterpreter Block"
	      infoedit		      "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
	      force_arith_type	      "on"
	      arith_type	      "Unsigned"
	      force_bin_pt	      "on"
	      bin_pt		      "31"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,336,312"
	      block_type	      "reinterpret"
	      block_version	      "10.1"
	      sg_icon_stat	      "45,20,1,1,white,blue,0,8982c1db,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Reinterpret2"
	      Ports		      [1, 1]
	      Position		      [870, 295, 915, 315]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Reinterpret"
	      SourceType	      "Xilinx Type Reinterpreter Block"
	      infoedit		      "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
	      force_arith_type	      "on"
	      arith_type	      "Signed  (2's comp)"
	      force_bin_pt	      "on"
	      bin_pt		      "32"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,336,312"
	      block_type	      "reinterpret"
	      block_version	      "10.1"
	      sg_icon_stat	      "45,20,1,1,white,blue,0,8982c1db,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Reinterpret3"
	      Ports		      [1, 1]
	      Position		      [270, 600, 315, 620]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Reinterpret"
	      SourceType	      "Xilinx Type Reinterpreter Block"
	      infoedit		      "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
	      force_arith_type	      "on"
	      arith_type	      "Unsigned"
	      force_bin_pt	      "on"
	      bin_pt		      "12"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,336,312"
	      block_type	      "reinterpret"
	      block_version	      "10.1"
	      sg_icon_stat	      "45,20,1,1,white,blue,0,8982c1db,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Reinterpret4"
	      Ports		      [1, 1]
	      Position		      [280, 800, 325, 820]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Reinterpret"
	      SourceType	      "Xilinx Type Reinterpreter Block"
	      infoedit		      "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
	      force_arith_type	      "on"
	      arith_type	      "Unsigned"
	      force_bin_pt	      "on"
	      bin_pt		      "12"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,336,312"
	      block_type	      "reinterpret"
	      block_version	      "10.1"
	      sg_icon_stat	      "45,20,1,1,white,blue,0,8982c1db,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Reinterpret5"
	      Ports		      [1, 1]
	      Position		      [270, 415, 315, 435]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Reinterpret"
	      SourceType	      "Xilinx Type Reinterpreter Block"
	      infoedit		      "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
	      force_arith_type	      "on"
	      arith_type	      "Unsigned"
	      force_bin_pt	      "on"
	      bin_pt		      "8"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,336,312"
	      block_type	      "reinterpret"
	      block_version	      "10.1"
	      sg_icon_stat	      "45,20,1,1,white,blue,0,8982c1db,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Reinterpret6"
	      Ports		      [1, 1]
	      Position		      [330, 910, 375, 930]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Reinterpret"
	      SourceType	      "Xilinx Type Reinterpreter Block"
	      infoedit		      "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
	      force_arith_type	      "on"
	      arith_type	      "Unsigned"
	      force_bin_pt	      "on"
	      bin_pt		      "15"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,336,312"
	      block_type	      "reinterpret"
	      block_version	      "10.1"
	      sg_icon_stat	      "45,20,1,1,white,blue,0,8982c1db,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Reinterpret7"
	      Ports		      [1, 1]
	      Position		      [330, 930, 375, 950]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Reinterpret"
	      SourceType	      "Xilinx Type Reinterpreter Block"
	      infoedit		      "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
	      force_arith_type	      "on"
	      arith_type	      "Unsigned"
	      force_bin_pt	      "on"
	      bin_pt		      "15"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,336,312"
	      block_type	      "reinterpret"
	      block_version	      "10.1"
	      sg_icon_stat	      "45,20,1,1,white,blue,0,8982c1db,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register"
	      Ports		      [0, 1]
	      Position		      [55, 459, 110, 491]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_pktDet_Tresholds'|Unsigned|32|0|(2^8 * pkt_energy_thresh) + pkt_crossCorr_thresh|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_pktDet_Tresholds_w'"
		  init			  "0.7"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register1"
	      Ports		      [0, 1]
	      Position		      [55, 524, 110, 556]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_Constellation_Scaling'|Unsigned|32|0|rx_postEq_scaling|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register1"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_Constellation_Scaling_w'"
		  init			  "134219776"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register10"
	      Ports		      [0, 1]
	      Position		      [720, 699, 775, 731]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_FixedPktLen'|Unsigned|32|0|RxReg_FixedPktLen|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register10"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_FixedPktLen_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register2"
	      Ports		      [0, 1]
	      Position		      [725, 219, 780, 251]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_PreCFO_PilotCalcCorrection'|Unsigned|32|0|regRx_pilotCalcCorrection|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register2"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_PreCFO_PilotCalcCorrection_w'"
		  init			  "2149953254"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register3"
	      Ports		      [0, 1]
	      Position		      [725, 289, 780, 321]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_coarseCFO_correction'|Unsigned|32|0|regRx_coarseCalcCorrection|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register3"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_coarseCFO_correction_w'"
		  init			  "7731"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register4"
	      Ports		      [0, 1]
	      Position		      [55, 689, 110, 721]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_AF_Blanking'|Unsigned|32|0|reg_AF_Tx_Blanking|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register4"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_AF_Blanking_w'"
		  init			  "31392144"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register5"
	      Ports		      [0, 1]
	      Position		      [55, 594, 110, 626]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_PilotCalcParams'|Unsigned|32|0|reg_PilotCalcParams|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register5"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_PilotCalcParams_w'"
		  init			  "262184.96"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register6"
	      Ports		      [0, 1]
	      Position		      [55, 794, 110, 826]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_AF_TxScaling'|Unsigned|32|0|reg_AF_Tx_Scaling|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register6"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_AF_TxScaling_w'"
		  init			  "2944"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register7"
	      Ports		      [0, 1]
	      Position		      [730, 134, 785, 166]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_PreCFO_Options'|Unsigned|32|0|regRx_preCFOoptions|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register7"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_PreCFO_Options_w'"
		  init			  "2"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register8"
	      Ports		      [0, 1]
	      Position		      [55, 904, 110, 936]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_ChanEst_MinMag'|Unsigned|32|0|regRx_chanEst_minMag|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register8"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_ChanEst_MinMag_w'"
		  init			  "1073758208"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Write-Only Register9"
	      Ports		      [0, 1]
	      Position		      [720, 604, 775, 636]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Write-Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's \"From Register\" shared memory block.\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found."
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\n\nif(length(regBlock)>0)\n\n	%Set the shared memory name\n\n    set_param(regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Rx_PktDet_LongCorr_Thresholds'|Unsigned|32|0|Rx_PktDet_LongCorrThresholds|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Write-Only Register9"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Rx_PktDet_LongCorr_Thresholds_w'"
		  init			  "8000"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [265, 53, 295, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0]
		  DstBlock		  "D"
		  DstPort		  1
		}
	      }
	    }
	    Line {
	      SrcBlock		      "Read-Write Register"
	      SrcPort		      1
	      DstBlock		      "Down Sample18"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register2"
	      SrcPort		      1
	      DstBlock		      "Down Sample15"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register3"
	      SrcPort		      1
	      Points		      [60, 0]
	      Branch {
		DstBlock		"7LSB"
		DstPort			1
	      }
	      Branch {
		Points			[0, 45]
		Branch {
		  DstBlock		  "6LSB+7"
		  DstPort		  1
		}
		Branch {
		  Points		  [0, 45]
		  Branch {
		    DstBlock		    "5b+16"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 35]
		    DstBlock		    "8MSB"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Line {
	      SrcBlock		      "Down Sample9"
	      SrcPort		      1
	      DstBlock		      "Goto20"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample15"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		Points			[0, 30]
		DstBlock		"24MSB"
		DstPort			1
	      }
	      Branch {
		DstBlock		"8LSB "
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "8LSB+8"
	      SrcPort		      1
	      DstBlock		      "Goto29"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Read-Write Register1"
	      SrcPort		      1
	      DstBlock		      "Down Sample12"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample12"
	      SrcPort		      1
	      Points		      [25, 0]
	      Branch {
		DstBlock		"8LSB+8"
		DstPort			1
	      }
	      Branch {
		Points			[0, -30]
		DstBlock		"8LSB+0"
		DstPort			1
	      }
	      Branch {
		Points			[0, 40]
		Branch {
		  DstBlock		  "8LSB+16"
		  DstPort		  1
		}
		Branch {
		  Points		  [0, 30]
		  DstBlock		  "8LSB+24"
		  DstPort		  1
		}
	      }
	    }
	    Line {
	      SrcBlock		      "24MSB"
	      SrcPort		      1
	      DstBlock		      "Goto27"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "7LSB"
	      SrcPort		      1
	      DstBlock		      "Down Sample9"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "6LSB+7"
	      SrcPort		      1
	      DstBlock		      "Down Sample17"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample17"
	      SrcPort		      1
	      DstBlock		      "Goto7"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample23"
	      SrcPort		      1
	      DstBlock		      "Goto41"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "5b+16"
	      SrcPort		      1
	      DstBlock		      "Down Sample23"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Write-Only Register"
	      SrcPort		      1
	      DstBlock		      "Down Sample20"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample20"
	      SrcPort		      1
	      DstBlock		      "Goto45"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample18"
	      SrcPort		      1
	      DstBlock		      "ControlBits Slices"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "8LSB "
	      SrcPort		      1
	      DstBlock		      "Goto5"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From3"
	      SrcPort		      1
	      DstBlock		      "Read Only Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From1"
	      SrcPort		      1
	      DstBlock		      "Read Only Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Write-Only Register1"
	      SrcPort		      1
	      DstBlock		      "Goto4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From14"
	      SrcPort		      1
	      DstBlock		      "Read Only Register2"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "From12"
	      SrcPort		      1
	      DstBlock		      "Read Only Register1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From25"
	      SrcPort		      1
	      DstBlock		      "Read Only Register2"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From13"
	      SrcPort		      1
	      DstBlock		      "Read Only Register1"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "From2"
	      SrcPort		      1
	      DstBlock		      "Read Only Register3"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From4"
	      SrcPort		      1
	      DstBlock		      "Read Only Register3"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Write-Only Register6"
	      SrcPort		      1
	      DstBlock		      "18LSB"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Reinterpret4"
	      SrcPort		      1
	      DstBlock		      "Goto1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "18LSB"
	      SrcPort		      1
	      DstBlock		      "Reinterpret4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "8MSB"
	      SrcPort		      1
	      DstBlock		      "Reinterpret5"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample1"
	      SrcPort		      1
	      DstBlock		      "Goto2"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Reinterpret5"
	      SrcPort		      1
	      DstBlock		      "Down Sample1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "1LSB "
	      SrcPort		      1
	      DstBlock		      "Down Sample2"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Write-Only Register7"
	      SrcPort		      1
	      Points		      [55, 0]
	      Branch {
		DstBlock		"1LSB "
		DstPort			1
	      }
	      Branch {
		Points			[0, 40]
		DstBlock		"1LSB+1 "
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Down Sample2"
	      SrcPort		      1
	      DstBlock		      "Goto3"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Write-Only Register5"
	      SrcPort		      1
	      Points		      [45, 0]
	      Branch {
		DstBlock		"12LSB"
		DstPort			1
	      }
	      Branch {
		Points			[0, 40]
		DstBlock		"3LSB+16"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Reinterpret3"
	      SrcPort		      1
	      DstBlock		      "Goto26"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "12LSB"
	      SrcPort		      1
	      DstBlock		      "Reinterpret3"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "3LSB+16"
	      SrcPort		      1
	      DstBlock		      "Goto11"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From5"
	      SrcPort		      1
	      DstBlock		      "Read Only Register4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From6"
	      SrcPort		      1
	      DstBlock		      "Read Only Register4"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "From7"
	      SrcPort		      1
	      DstBlock		      "Read Only Register5"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From8"
	      SrcPort		      1
	      DstBlock		      "Read Only Register5"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "1LSB+1 "
	      SrcPort		      1
	      DstBlock		      "Down Sample3"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample3"
	      SrcPort		      1
	      DstBlock		      "Goto6"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From9"
	      SrcPort		      1
	      DstBlock		      "Read Only Register6"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "From10"
	      SrcPort		      1
	      DstBlock		      "Read Only Register6"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Reinterpret1"
	      SrcPort		      1
	      DstBlock		      "Goto8"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Write-Only Register2"
	      SrcPort		      1
	      DstBlock		      "Reinterpret1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Reinterpret2"
	      SrcPort		      1
	      DstBlock		      "Goto9"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Write-Only Register3"
	      SrcPort		      1
	      DstBlock		      "Reinterpret2"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "8LSB+0"
	      SrcPort		      1
	      DstBlock		      "Goto10"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Write-Only Register4"
	      SrcPort		      1
	      DstBlock		      "Down Sample4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "12LSB+16"
	      SrcPort		      1
	      DstBlock		      "Goto13"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "12LSB "
	      SrcPort		      1
	      DstBlock		      "Goto12"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample4"
	      SrcPort		      1
	      Points		      [40, 0]
	      Branch {
		DstBlock		"12LSB+16"
		DstPort			1
	      }
	      Branch {
		Points			[0, 20]
		DstBlock		"12LSB "
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Down Sample5"
	      SrcPort		      1
	      Points		      [10, 0]
	      Branch {
		Points			[0, 20]
		DstBlock		"16LSB"
		DstPort			1
	      }
	      Branch {
		DstBlock		"16MSB  "
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Write-Only Register8"
	      SrcPort		      1
	      DstBlock		      "Down Sample5"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "16LSB"
	      SrcPort		      1
	      DstBlock		      "Reinterpret7"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "16MSB  "
	      SrcPort		      1
	      DstBlock		      "Reinterpret6"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Reinterpret6"
	      SrcPort		      1
	      DstBlock		      "Goto15"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Reinterpret7"
	      SrcPort		      1
	      DstBlock		      "Goto14"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Write-Only Register9"
	      SrcPort		      1
	      DstBlock		      "Down Sample6"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample6"
	      SrcPort		      1
	      DstBlock		      "16LSB "
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "16LSB "
	      SrcPort		      1
	      DstBlock		      "Goto16"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "8LSB+16"
	      SrcPort		      1
	      DstBlock		      "Goto17"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "8LSB+24"
	      SrcPort		      1
	      DstBlock		      "Goto18"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Write-Only Register10"
	      SrcPort		      1
	      DstBlock		      "Down Sample7"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "1MSB"
	      SrcPort		      1
	      DstBlock		      "Goto19"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "12LSB  "
	      SrcPort		      1
	      DstBlock		      "Goto21"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample7"
	      SrcPort		      1
	      Points		      [50, 0]
	      Branch {
		DstBlock		"1MSB"
		DstPort			1
	      }
	      Branch {
		Points			[0, 50]
		DstBlock		"12LSB  "
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Static Parameters\n(might be registers someday)"
	  Ports			  []
	  Position		  [90, 12, 160, 52]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Static Parameters\n(might be registers someday)"
	    Location		    [1207, 119, 1610, 349]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "112"
	    Block {
	      BlockType		      Reference
	      Name		      "Constant"
	      Ports		      [0, 1]
	      Position		      [25, 25, 70, 55]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Constant"
	      SourceType	      "Xilinx Constant Block Block"
	      arith_type	      "Unsigned"
	      const		      "numSubcarriers"
	      n_bits		      "ceil(log2(max_num_subcarriers)+1)"
	      bin_pt		      "0"
	      explicit_period	      "on"
	      period		      "2"
	      dsp48_infoedit	      "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	      equ		      "P=C"
	      opselect		      "C"
	      inp2		      "PCIN>>17"
	      opr		      "+"
	      inp1		      "P"
	      carry		      "CIN"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "constant"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,30,1,1,white,blue,0,86ec2f60,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'64');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Constant1"
	      Ports		      [0, 1]
	      Position		      [25, 100, 70, 130]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Constant"
	      SourceType	      "Xilinx Constant Block Block"
	      arith_type	      "Unsigned"
	      const		      "numSubcarriers+CPLength-1"
	      n_bits		      "ceil(log2(max_num_subcarriers+CPLength)+1)"
	      bin_pt		      "0"
	      explicit_period	      "on"
	      period		      "2"
	      dsp48_infoedit	      "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	      equ		      "P=C"
	      opselect		      "C"
	      inp2		      "PCIN>>17"
	      opr		      "+"
	      inp1		      "P"
	      carry		      "CIN"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,400,346"
	      block_type	      "constant"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,30,1,1,white,blue,0,c976f10b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'79');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Constant2"
	      Ports		      [0, 1]
	      Position		      [30, 153, 60, 177]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Constant"
	      SourceType	      "Xilinx Constant Block Block"
	      arith_type	      "Unsigned"
	      const		      "16"
	      n_bits		      "5"
	      bin_pt		      "0"
	      explicit_period	      "on"
	      period		      "1"
	      dsp48_infoedit	      "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	      equ		      "P=C"
	      opselect		      "C"
	      inp2		      "PCIN>>17"
	      opr		      "+"
	      inp1		      "P"
	      carry		      "CIN"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "constant"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,24,1,1,white,blue,0,636e1b21,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'16');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample8"
	      Ports		      [1, 1]
	      Position		      [120, 151, 150, 179]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto4"
	      Position		      [180, 155, 335, 175]
	      ShowName		      off
	      GotoTag		      "regRX_CP_Length"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto6"
	      Position		      [130, 30, 285, 50]
	      ShowName		      off
	      GotoTag		      "regRX_numSubcarriers"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto9"
	      Position		      [130, 105, 285, 125]
	      ShowName		      off
	      GotoTag		      "regRX_sampsPerSymMinusOne"
	      TagVisibility	      "global"
	    }
	    Line {
	      SrcBlock		      "Constant"
	      SrcPort		      1
	      DstBlock		      "Goto6"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Constant1"
	      SrcPort		      1
	      DstBlock		      "Goto9"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Down Sample8"
	      SrcPort		      1
	      DstBlock		      "Goto4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Constant2"
	      SrcPort		      1
	      DstBlock		      "Down Sample8"
	      DstPort		      1
	    }
	    Annotation {
	      Name		      "Replace with registers someday\nto support dynamic transform and \ncyclic prefix sizes"
	      Position		      [55, 78]
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Tx Registers"
	  Ports			  []
	  Position		  [95, 95, 165, 132]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Tx Registers"
	    Location		    [849, 50, 1416, 1075]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "124"
	    Block {
	      BlockType		      SubSystem
	      Name		      "Control Bits Slices"
	      Ports		      [1]
	      Position		      [275, 213, 355, 247]
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      System {
		Name			"Control Bits Slices"
		Location		[392, 183, 773, 410]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"145"
		Block {
		  BlockType		  Inport
		  Name			  "32b"
		  Position		  [190, 138, 220, 152]
		  IconDisplay		  "Port number"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample1"
		  Ports			  [1, 1]
		  Position		  [440, 251, 470, 279]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Down Sample3"
		  Ports			  [1, 1]
		  Position		  [405, 171, 435, 199]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Down Sample"
		  SourceType		  "Xilinx Down Sampler Block"
		  infoedit		  "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
		  sample_ratio		  "2"
		  sample_phase		  "Last Value of Frame  (most efficient)"
		  en			  "off"
		  latency		  "1"
		  dbl_ovrd		  "off"
		  xl_use_area		  "off"
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,356,300"
		  block_type		  "dsamp"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "30,28,1,1,white,blue,0,c153b99b,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto1"
		  Position		  [505, 157, 625, 173]
		  ShowName		  off
		  GotoTag		  "TxReg_Alamouti_Mode"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto10"
		  Position		  [475, 462, 620, 478]
		  ShowName		  off
		  GotoTag		  "regTx_AutoTwoTx_En"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto11"
		  Position		  [475, 551, 640, 569]
		  ShowName		  off
		  GotoTag		  "TxReg_TxRunningOut_en1"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto12"
		  Position		  [475, 581, 640, 599]
		  ShowName		  off
		  GotoTag		  "TxReg_FilterSel"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto15"
		  Position		  [505, 177, 625, 193]
		  ShowName		  off
		  GotoTag		  "TxReg_DisableAntBPreamble"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto16"
		  Position		  [505, 197, 625, 213]
		  ShowName		  off
		  GotoTag		  "TxReg_PilotScrambling"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto17"
		  Position		  [555, 257, 675, 273]
		  ShowName		  off
		  GotoTag		  "TxReg_AntBPreambleShift"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto18"
		  Position		  [555, 687, 675, 703]
		  ShowName		  off
		  GotoTag		  "TxReg_PostIFFTCycShift"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto2"
		  Position		  [505, 137, 625, 153]
		  ShowName		  off
		  GotoTag		  "TxReg_SISO_Mode"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto3"
		  Position		  [495, 312, 615, 328]
		  ShowName		  off
		  GotoTag		  "TxReg_SwapAntennas"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto4"
		  Position		  [495, 337, 615, 353]
		  ShowName		  off
		  GotoTag		  "TxReg_SoftTxStart_TxEn"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto5"
		  Position		  [495, 282, 615, 298]
		  ShowName		  off
		  GotoTag		  "regTx_RandomPayload"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto6"
		  Position		  [475, 521, 640, 539]
		  ShowName		  off
		  GotoTag		  "TxReg_TxRunningOut_en0"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto7"
		  Position		  [475, 372, 620, 388]
		  ShowName		  off
		  GotoTag		  "TxReg_Enable_ExtTxEn"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto8"
		  Position		  [475, 397, 620, 413]
		  ShowName		  off
		  GotoTag		  "regTx_AlwaysUsePreSpin"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Goto
		  Name			  "Goto9"
		  Position		  [475, 432, 620, 448]
		  ShowName		  off
		  GotoTag		  "regTx_CaptureRandomPayload"
		  TagVisibility		  "global"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Reinterpret"
		  Ports			  [1, 1]
		  Position		  [365, 256, 400, 274]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Reinterpret"
		  SourceType		  "Xilinx Type Reinterpreter Block"
		  infoedit		  "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
		  force_arith_type	  "on"
		  arith_type		  "Signed  (2's comp)"
		  force_bin_pt		  "off"
		  bin_pt		  "13"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,312"
		  block_type		  "reinterpret"
		  block_version		  "10.1"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,8982c1db,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice1"
		  Ports			  [1, 1]
		  Position		  [275, 136, 310, 154]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "0"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice10"
		  Ports			  [1, 1]
		  Position		  [275, 521, 310, 539]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "15"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice11"
		  Ports			  [1, 1]
		  Position		  [275, 396, 310, 414]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "12"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice12"
		  Ports			  [1, 1]
		  Position		  [275, 431, 310, 449]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "13"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice13"
		  Ports			  [1, 1]
		  Position		  [275, 461, 310, 479]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "14"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice14"
		  Ports			  [1, 1]
		  Position		  [275, 551, 310, 569]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "16"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice15"
		  Ports			  [1, 1]
		  Position		  [275, 581, 310, 599]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "17"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice16"
		  Ports			  [1, 1]
		  Position		  [275, 611, 310, 629]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "18"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice17"
		  Ports			  [1, 1]
		  Position		  [275, 641, 310, 659]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "19"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice18"
		  Ports			  [1, 1]
		  Position		  [275, 686, 310, 704]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "6"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "20"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice2"
		  Ports			  [1, 1]
		  Position		  [275, 156, 310, 174]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "1"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,398"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice3"
		  Ports			  [1, 1]
		  Position		  [275, 176, 310, 194]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "2"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,442,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice4"
		  Ports			  [1, 1]
		  Position		  [275, 196, 310, 214]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "3"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice5"
		  Ports			  [1, 1]
		  Position		  [275, 256, 310, 274]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "4"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "4"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice6"
		  Ports			  [1, 1]
		  Position		  [275, 281, 310, 299]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "8"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice7"
		  Ports			  [1, 1]
		  Position		  [275, 311, 310, 329]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "9"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice8"
		  Ports			  [1, 1]
		  Position		  [275, 336, 310, 354]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "off"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "10"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Slice9"
		  Ports			  [1, 1]
		  Position		  [275, 371, 310, 389]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Slice"
		  SourceType		  "Xilinx Bit Slice Extractor Block"
		  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
		  nbits			  "1"
		  boolean_output	  "on"
		  mode			  "Lower Bit Location + Width"
		  bit1			  "0"
		  base1			  "MSB of Input"
		  bit0			  "11"
		  base0			  "LSB of Input"
		  dbl_ovrd		  "off"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,449,407"
		  block_type		  "slice"
		  block_version		  "VER_STRING_GOES_HERE"
		  sg_icon_stat		  "35,18,1,1,white,blue,0,b1026674,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "Slice1"
		  SrcPort		  1
		  DstBlock		  "Goto2"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "32b"
		  SrcPort		  1
		  Points		  [15, 0]
		  Branch {
		    Points		    [0, 20]
		    Branch {
		    DstBlock		    "Slice2"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 20]
		    Branch {
		    Points		    [0, 60]
		    Branch {
		    DstBlock		    "Slice5"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    DstBlock		    "Slice6"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice7"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    DstBlock		    "Slice8"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 35]
		    Branch {
		    DstBlock		    "Slice9"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 25]
		    Branch {
		    Points		    [0, 35]
		    Branch {
		    DstBlock		    "Slice12"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice13"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 60]
		    Branch {
		    DstBlock		    "Slice10"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice14"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice15"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice16"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 30]
		    Branch {
		    DstBlock		    "Slice17"
		    DstPort		    1
		    }
		    Branch {
		    Points		    [0, 45]
		    DstBlock		    "Slice18"
		    DstPort		    1
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    Branch {
		    DstBlock		    "Slice11"
		    DstPort		    1
		    }
		    }
		    }
		    }
		    }
		    }
		    }
		    Branch {
		    DstBlock		    "Slice4"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "Slice3"
		    DstPort		    1
		    }
		    }
		  }
		  Branch {
		    DstBlock		    "Slice1"
		    DstPort		    1
		  }
		}
		Line {
		  SrcBlock		  "Slice3"
		  SrcPort		  1
		  DstBlock		  "Down Sample3"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice4"
		  SrcPort		  1
		  DstBlock		  "Goto16"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice5"
		  SrcPort		  1
		  DstBlock		  "Reinterpret"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice6"
		  SrcPort		  1
		  DstBlock		  "Goto5"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice2"
		  SrcPort		  1
		  DstBlock		  "Goto1"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice7"
		  SrcPort		  1
		  DstBlock		  "Goto3"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice8"
		  SrcPort		  1
		  DstBlock		  "Goto4"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice9"
		  SrcPort		  1
		  DstBlock		  "Goto7"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice11"
		  SrcPort		  1
		  DstBlock		  "Goto8"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice12"
		  SrcPort		  1
		  DstBlock		  "Goto9"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice13"
		  SrcPort		  1
		  DstBlock		  "Goto10"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice10"
		  SrcPort		  1
		  DstBlock		  "Goto6"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice14"
		  SrcPort		  1
		  DstBlock		  "Goto11"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice15"
		  SrcPort		  1
		  DstBlock		  "Goto12"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Reinterpret"
		  SrcPort		  1
		  DstBlock		  "Down Sample1"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample1"
		  SrcPort		  1
		  DstBlock		  "Goto17"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Down Sample3"
		  SrcPort		  1
		  DstBlock		  "Goto15"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Slice18"
		  SrcPort		  1
		  DstBlock		  "Goto18"
		  DstPort		  1
		}
		Annotation {
		  Name			  "LSB"
		  Position		  [290, 124]
		}
		Annotation {
		  Name			  "0x1"
		  Position		  [646, 145]
		}
		Annotation {
		  Name			  "0x2"
		  Position		  [646, 165]
		}
		Annotation {
		  Name			  "0x4"
		  Position		  [646, 185]
		}
		Annotation {
		  Name			  "0x8"
		  Position		  [646, 205]
		}
		Annotation {
		  Name			  "0xF0"
		  Position		  [706, 265]
		}
		Annotation {
		  Name			  "0x200"
		  Position		  [651, 320]
		}
		Annotation {
		  Name			  "0x400"
		  Position		  [646, 345]
		}
		Annotation {
		  Name			  "0x100"
		  Position		  [646, 290]
		}
		Annotation {
		  Name			  "0x800"
		  Position		  [646, 380]
		}
		Annotation {
		  Name			  "0x1000"
		  Position		  [656, 405]
		}
		Annotation {
		  Name			  "0x2000"
		  Position		  [656, 440]
		}
		Annotation {
		  Name			  "0x4000"
		  Position		  [656, 470]
		}
		Annotation {
		  Name			  "0x8000"
		  Position		  [681, 530]
		}
		Annotation {
		  Name			  "0x1_0000"
		  Position		  [681, 560]
		}
		Annotation {
		  Name			  "0x2_0000"
		  Position		  [681, 590]
		}
		Annotation {
		  Name			  "0x4_0000"
		  Position		  [706, 620]
		}
		Annotation {
		  Name			  "0x8_0000"
		  Position		  [701, 650]
		}
		Annotation {
		  Name			  "0x3F0_0000"
		  Position		  [716, 695]
		}
	      }
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample1"
	      Ports		      [1, 1]
	      Position		      [195, 216, 225, 244]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample3"
	      Ports		      [1, 1]
	      Position		      [190, 26, 220, 54]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,356,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample4"
	      Ports		      [1, 1]
	      Position		      [215, 516, 245, 544]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "4"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,f354a31c,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}4\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Down Sample6"
	      Ports		      [1, 1]
	      Position		      [215, 466, 245, 494]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Down Sample"
	      SourceType	      "Xilinx Down Sampler Block"
	      infoedit		      "Hardware notes: Sample and Latency controls determine the hardware implementation.  The cost in hardware of different implementations varies considerably; press Help for details."
	      sample_ratio	      "2"
	      sample_phase	      "Last Value of Frame  (most efficient)"
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0,0,0,0,0,0,0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,360,300"
	      block_type	      "dsamp"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,28,1,1,white,blue,0,c153b99b,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newline{\\fontsize{14pt}\\bf\\downarrow}2\\newlinez^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From5"
	      Position		      [675, 106, 815, 124]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regTx_PktRunning"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      From
	      Name		      "From6"
	      Position		      [675, 141, 810, 159]
	      ShowName		      off
	      CloseFcn		      "tagdialog Close"
	      GotoTag		      "regTx_PktRunningEn"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto1"
	      Position		      [465, 522, 615, 538]
	      ShowName		      off
	      GotoTag		      "TxReg_TxRunningOut_delay"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto11"
	      Position		      [470, 497, 615, 513]
	      ShowName		      off
	      GotoTag		      "regRx_AutoTx_ExtraDly"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto13"
	      Position		      [355, 32, 475, 48]
	      ShowName		      off
	      GotoTag		      "TxReg_TxReset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto14"
	      Position		      [355, 57, 475, 73]
	      ShowName		      off
	      GotoTag		      "TxReg_TxStart"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto23"
	      Position		      [450, 362, 595, 378]
	      ShowName		      off
	      GotoTag		      "TxReg_PreambleScaling"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto4"
	      Position		      [450, 382, 595, 398]
	      ShowName		      off
	      GotoTag		      "TxReg_postIFFTScaling"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto6"
	      Position		      [470, 472, 615, 488]
	      ShowName		      off
	      GotoTag		      "TxReg_ExtAutoTxEn_Delay"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read Only Register"
	      Ports		      [2]
	      Position		      [1025, 98, 1075, 167]
	      AttributesFormatString  "RO Reg: %<regName>\\n%<ReferenceBlock>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read Only Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for System Generator's To Register shared memory block. This register is designed for use with WARP's sysgen2opb tool.\n\nNote: The Regisger Name paramter below must be unique for every instance of Read-Write and Read-Only registers in your system."
	      MaskPromptString	      "Register Name"
	      MaskStyleString	      "edit"
	      MaskTunableValueString  "off"
	      MaskEnableString	      "on"
	      MaskVisibilityString    "on"
	      MaskToolTipString	      "on"
	      MaskVariables	      "regName=&1;"
	      MaskInitialization      "regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on',   'block_type', 'toreg');\n\nif(length(regBlock) > 0)\n\n    %Set the shared memory name\n    set_param(regBlock{1}, 'shared_memory_name', regName);\n\n	set_param(regBlock{1}, 'explicit_data_type', 'on')\n    set_param(regBlock{1}, 'arith_type', 'unsigned');\n	set_param(regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(regBlock{1}, 'n_bits', '32');\n	set_param(regBlock{1}, 'bin_pt', '0');\n	set_param(regBlock{1}, 'init', '0');\nend\n\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Tx_PktRunning'"
	      System {
		Name			"Read Only Register"
		Location		[567, 173, 1136, 671]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Inport
		  Name			  "D"
		  Position		  [15, 183, 45, 197]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Inport
		  Name			  "En"
		  Position		  [15, 223, 45, 237]
		  Port			  "2"
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Convert"
		  Ports			  [1, 1]
		  Position		  [180, 175, 225, 205]
		  SourceBlock		  "xbsIndex_r4/Convert"
		  SourceType		  "Xilinx Type Converter Block"
		  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  quantization		  "Truncate"
		  overflow		  "Wrap"
		  latency		  "0"
		  dbl_ovrd		  off
		  pipeline		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,461,334"
		  block_type		  "convert"
		  block_version		  "10.1"
		  sg_icon_stat		  "45,30,1,1,white,blue,0,74901e60,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "Reinterpret"
		  Ports			  [1, 1]
		  Position		  [90, 174, 140, 206]
		  SourceBlock		  "xbsIndex_r4/Reinterpret"
		  SourceType		  "Xilinx Type Reinterpreter Block"
		  infoedit		  "Changes signal type without altering the binary representation.   You can changed the signal between signed and unsigned, and relocate the binary point.<P><P>Hardware notes: In hardware this block costs nothing.<P><P>Example:  Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits.  Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)."
		  force_arith_type	  on
		  arith_type		  "Unsigned"
		  force_bin_pt		  on
		  bin_pt		  "0"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,336,312"
		  block_type		  "reinterpret"
		  block_version		  "10.1"
		  sg_icon_stat		  "50,32,1,1,white,blue,0,8982c1db,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [410, 195, 430, 215]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [310, 176, 365, 229]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Tx_PktRunning'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,2,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Line {
		  SrcBlock		  "En"
		  SrcPort		  1
		  Points		  [215, 0; 0, -15]
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "D"
		  SrcPort		  1
		  DstBlock		  "Reinterpret"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Reinterpret"
		  SrcPort		  1
		  DstBlock		  "Convert"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Convert"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register"
	      Ports		      [0, 1]
	      Position		      [75, 24, 130, 56]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Tx_Start_Reset_Control'|Unsigned|32|0|0|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register"
		Location		[2, 74, 582, 375]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Tx_Start_Reset_Control_w'"
		  init			  "0"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Tx_Start_Reset_Control_r'"
		  init			  "0"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register1"
	      Ports		      [0, 1]
	      Position		      [75, 214, 130, 246]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Tx_ControlBits'|Unsigned|32|0|tx_controlBits|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register1"
		Location		[2, 74, 582, 375]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Reference
		  Name			  "Constant"
		  Ports			  [0, 1]
		  Position		  [175, 216, 200, 234]
		  ShowName		  off
		  SourceBlock		  "xbsIndex_r4/Constant"
		  SourceType		  "Xilinx Constant Block Block"
		  arith_type		  "Boolean"
		  const			  "1"
		  n_bits		  "16"
		  bin_pt		  "14"
		  explicit_period	  on
		  period		  "sampPeriod"
		  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
		  equ			  "P=C"
		  opselect		  "C"
		  inp2			  "PCIN>>17"
		  opr			  "+"
		  inp1			  "P"
		  carry			  "CIN"
		  dbl_ovrd		  off
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,400,346"
		  block_type		  "constant"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "25,18,0,1,white,blue,0,06094819,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Reference
		  Name			  "From Register"
		  Ports			  [0, 1]
		  Position		  [150, 35, 195, 85]
		  ShowName		  off
		  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>\\n%<n_bits>\\n%<period>\\n%<bin_pt>\\n%<arith_type>\\n%<ownership>\\n%<init>"
		  SourceBlock		  "xbsIndex_r4/From Register"
		  SourceType		  "Xilinx Shared Memory Based From Register Block"
		  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Tx_ControlBits_w'"
		  init			  "17006650"
		  period		  "sampPeriod"
		  ownership		  "Locally owned and initialized"
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,246"
		  block_type		  "fromreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "45,50,0,1,white,blue,0,4b212927,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Terminator
		  Name			  "Terminator"
		  Position		  [370, 205, 390, 225]
		  ShowName		  off
		}
		Block {
		  BlockType		  Reference
		  Name			  "To Register"
		  Ports			  [2, 1]
		  Position		  [270, 186, 325, 239]
		  ShowName		  off
		  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
		  SourceBlock		  "xbsIndex_r4/To Register"
		  SourceType		  "Xilinx Shared Memory Based To Register Block"
		  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
		  shared_memory_name	  "'Tx_ControlBits_r'"
		  init			  "17006650"
		  ownership		  "Locally owned and initialized"
		  explicit_data_type	  on
		  arith_type		  "Unsigned"
		  n_bits		  "32"
		  bin_pt		  "0"
		  dbl_ovrd		  off
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  has_advanced_control	  "0"
		  sggui_pos		  "20,20,381,270"
		  block_type		  "toreg"
		  block_version		  "8.2.02"
		  sg_icon_stat		  "55,53,1,1,white,blue,0,77cabcdf,right"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
		}
		Block {
		  BlockType		  Outport
		  Name			  "D"
		  Position		  [285, 53, 315, 67]
		  IconDisplay		  "Port number"
		  OutDataType		  "sfix(16)"
		  OutScaling		  "2^0"
		}
		Line {
		  SrcBlock		  "To Register"
		  SrcPort		  1
		  DstBlock		  "Terminator"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Constant"
		  SrcPort		  1
		  DstBlock		  "To Register"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "From Register"
		  SrcPort		  1
		  Points		  [0, 0; 35, 0]
		  Branch {
		    Points		    [0, 140]
		    DstBlock		    "To Register"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "D"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Read-Write Register2"
	      Ports		      [0, 1]
	      Position		      [70, 464, 125, 496]
	      AttributesFormatString  "RW Reg: %<regName>"
	      AncestorBlock	      "WARP_Blockset/Register Wrappers\n(Sysgen 10.1+)/Read-Write Register"
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      MaskDescription	      "This block is a wrapper for two registers from the System Generator Shared Memory blockset:\na) A \"From Register\" block, which provides a write-only register for the host processor\nb) A \"To Register\" block, which provides a read-only register for the host processor\n\nNote: The Regisger Name paramter below must be unique for every instance of shared-memory registers in your system. System Generator will throw an error if duplicate names are found.\n"
	      MaskPromptString	      "Register Name|Output Type|Output Num Bits|Output Binary Point|Initial Value|Sample Period"
	      MaskStyleString	      "edit,popup(Unsigned|Signed  (2's comp)),edit,edit,edit,edit"
	      MaskTunableValueString  "off,off,off,off,off,off"
	      MaskCallbackString      "|||||"
	      MaskEnableString	      "on,on,on,on,on,on"
	      MaskVisibilityString    "on,on,on,on,on,on"
	      MaskToolTipString	      "on,on,on,on,on,on"
	      MaskVarAliasString      ",,,,,"
	      MaskVariables	      "regName=&1;out_dataType=&2;out_numBits=@3;out_binaryPt=@4;initValue=@5;sampPeriod=@6;"
	      MaskInitialization      "wo_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'fromreg');\nro_regBlock = find_system(gcb, 'LookUnderMasks', 'all', 'FollowLinks', 'on', 'block_type', 'toreg');\n\nif(length(wo_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(wo_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_w') '''']);\n\n	set_param(wo_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(wo_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(wo_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(wo_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(wo_regBlock{1}, 'init', num2str(initValue));\nend\n\nif(length(ro_regBlock)>0)\n\n	%Set the shared memory name\n	set_param(ro_regBlock{1}, 'shared_memory_name', ['''' strcat(regName(2:end-1), '_r') '''']);\n\n	set_param(ro_regBlock{1}, 'explicit_data_type', 'on')\n    set_param(ro_regBlock{1}, 'arith_type', sprintf('%s', out_dataType));\n	set_param(ro_regBlock{1}, 'ownership', 'Locally owned and initialized')\n\n	set_param(ro_regBlock{1}, 'n_bits', num2str(out_numBits));\n	set_param(ro_regBlock{1}, 'bin_pt', num2str(out_binaryPt));\n	set_param(ro_regBlock{1}, 'init', num2str(initValue));\nend\n"
	      MaskSelfModifiable      on
	      MaskIconFrame	      on
	      MaskIconOpaque	      on
	      MaskIconRotate	      "none"
	      MaskIconUnits	      "autoscale"
	      MaskValueString	      "'Tx_Delays'|Unsigned|32|0|tx_delays|1"
	      MaskTabNameString	      ",,,,,"
	      System {
		Name			"Read-Write Register2"
		Location		[2, 74, 582, 375]
		Open			off
		ModelBrowserVisibility	on
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMarg