bb_simgen.bat

You only need to use this script if you make changes to the FEC decoder Verilog source code.

This script is part of a workaround for a bug in System Generator 13.3/13.4 that causes a 
MATLAB crash during simulation of the PHY model. The crash is somehow triggered by the HDL
simulation of the FEC decoder. Replacing the source HDL with a NGC->Verilog netlist bypasses the crash.

This script implements two steps:
1) Generates an NGC netlist for fec_decoder_top.v/fec_decoder_rest.v
2) Converts the new NGC netlist into a Verilog netlist for simulation

The netlist generated by this script should be used only in simulation. The original Verilog
source should be used when generating a pcore. The latest PHY model includes a simulation
multiplexer to automate this, using fec_decoder_top.v for implementation and fec_decoder_simOnly.v
for simulation.

Usage:
1) Copy your modified Verilog files, this script and its associated files (*bat *prj *opt) to a new directory.

2) Launch a Xilinx shell and cd to that directory.

3) Run 'bb_simgen.bat'; the script will run for a few minutes and generate a bunch of intermediate files/folders.

4) Copy the new Verilog file (fec_decoder_simOnly.v) to the PHY directory, replacing the existing file.

5) Copy your modified source HDL (fec_decoder_top.v / fec_decoder_rest.v) to the PHY directory, replacing the existing files.

6) If you changed any ports in the HDL you must update BOTH _config.m scripts for the Sysgen black boxes and 
	update the corresponding wires/ports in the Sysgen model


Special thanks to Brian Wiec at Xilinx for figuring out this workaround for the Sysgen crash.