Model {
  Name			  "warp_timer"
  Version		  7.1
  MdlSubVersion		  0
  GraphicalInterface {
    NumRootInports	    0
    NumRootOutports	    0
    ParameterArgumentNames  ""
    ComputedModelVersion    "1.243"
    NumModelReferences	    0
    NumTestPointedSignals   0
  }
  SavedCharacterEncoding  "windows-1252"
  SaveDefaultBlockParams  on
  SampleTimeColors	  on
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ShowTestPointIcons	  on
  ShowSignalResolutionIcons on
  ShowViewerIcons	  on
  SortedOrder		  off
  ExecutionContextIcon	  off
  ShowLinearizationAnnotations on
  ScopeRefreshTime	  0.035000
  OverrideScopeRefreshTime on
  DisableAllScopes	  off
  DataTypeOverride	  "UseLocalSettings"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Sun Feb 18 17:49:04 2007"
  Creator		  "CMC"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "murphpo"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Thu Jun 25 18:09:54 2009"
  RTWModifiedTimeStamp	  0
  ModelVersionFormat	  "1.%<AutoIncrement:243>"
  ConfigurationManager	  "None"
  SimulationMode	  "normal"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  CovReportOnPause	  on
  CovModelRefEnable	  "Off"
  ExtModeBatchMode	  off
  ExtModeEnableFloating	  on
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigDurationFloating "auto"
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  ShowModelReferenceBlockVersion off
  ShowModelReferenceBlockIO off
  Array {
    Type		    "Handle"
    Dimension		    1
    Simulink.ConfigSet {
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	  MaxNumMinSteps	  "-1"
	  MaxOrder		  5
	  ZcThreshold		  "auto"
	  ConsecutiveZCsStepRelTol "10*128*eps"
	  MaxConsecutiveZCs	  "1000"
	  ExtrapolationOrder	  4
	  NumberNewtonIterations  1
	  MaxStep		  "auto"
	  MinStep		  "auto"
	  MaxConsecutiveMinStep	  "1"
	  RelTol		  "1e-3"
	  SolverMode		  "Auto"
	  Solver		  "ode45"
	  SolverName		  "ode45"
	  ShapePreserveControl	  "DisableAll"
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	  AlgebraicLoopSolver	  "TrustRegion"
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	Simulink.DataIOCC {
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	  LoadExternalInput	  off
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	  SaveFormat		  "Array"
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	  SaveState		  off
	  SignalLogging		  on
	  InspectSignalLogs	  off
	  SaveTime		  on
	  StateSaveName		  "xout"
	  TimeSaveName		  "tout"
	  OutputSaveName	  "yout"
	  SignalLoggingName	  "logsout"
	  OutputOption		  "RefineOutputTimes"
	  OutputTimes		  "[]"
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	Simulink.OptimizationCC {
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	    Cell		    "InitFltsAndDblsToZero"
	    Cell		    "OptimizeModelRefInitCode"
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	    PropName		    "DisabledProps"
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	  Version		  "1.4.0"
	  BlockReduction	  on
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	  ExpressionDepthLimit	  2147483647
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	  LifeSpan		  "inf"
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	Simulink.DebuggingCC {
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	  ReadBeforeWriteMsg	  "UseLocalSettings"
	  WriteAfterWriteMsg	  "UseLocalSettings"
	  WriteAfterReadMsg	  "UseLocalSettings"
	  AlgebraicLoopMsg	  "warning"
	  ArtificialAlgebraicLoopMsg "warning"
	  SaveWithDisabledLinksMsg "warning"
	  SaveWithParameterizedLinksMsg	"none"
	  CheckSSInitialOutputMsg on
	  CheckExecutionContextPreStartOutputMsg off
	  CheckExecutionContextRuntimeOutputMsg	off
	  SignalResolutionControl "TryResolveAllWithWarning"
	  BlockPriorityViolationMsg "warning"
	  MinStepSizeMsg	  "warning"
	  TimeAdjustmentMsg	  "none"
	  MaxConsecutiveZCsMsg	  "error"
	  SolverPrmCheckMsg	  "warning"
	  InheritedTsInSrcMsg	  "warning"
	  DiscreteInheritContinuousMsg "warning"
	  MultiTaskDSMMsg	  "warning"
	  MultiTaskCondExecSysMsg "none"
	  MultiTaskRateTransMsg	  "error"
	  SingleTaskRateTransMsg  "none"
	  TasksWithSamePriorityMsg "warning"
	  SigSpecEnsureSampleTimeMsg "warning"
	  CheckMatrixSingularityMsg "none"
	  IntegerOverflowMsg	  "warning"
	  Int32ToFloatConvMsg	  "warning"
	  ParameterDowncastMsg	  "error"
	  ParameterOverflowMsg	  "error"
	  ParameterUnderflowMsg	  "none"
	  ParameterPrecisionLossMsg "warning"
	  ParameterTunabilityLossMsg "warning"
	  UnderSpecifiedDataTypeMsg "none"
	  UnnecessaryDatatypeConvMsg "none"
	  VectorMatrixConversionMsg "none"
	  InvalidFcnCallConnMsg	  "error"
	  FcnCallInpInsideContextMsg "Use local settings"
	  SignalLabelMismatchMsg  "none"
	  UnconnectedInputMsg	  "warning"
	  UnconnectedOutputMsg	  "warning"
	  UnconnectedLineMsg	  "warning"
	  SFcnCompatibilityMsg	  "none"
	  UniqueDataStoreMsg	  "none"
	  BusObjectLabelMismatch  "warning"
	  RootOutportRequireBusObject "warning"
	  AssertControl		  "UseLocalSettings"
	  EnableOverflowDetection off
	  ModelReferenceIOMsg	  "none"
	  ModelReferenceVersionMismatchMessage "none"
	  ModelReferenceIOMismatchMessage "none"
	  ModelReferenceCSMismatchMessage "none"
	  ModelReferenceSimTargetVerbose off
	  UnknownTsInhSupMsg	  "warning"
	  ModelReferenceDataLoggingMessage "warning"
	  ModelReferenceSymbolNameMessage "warning"
	  ModelReferenceExtraNoncontSigs "error"
	  StateNameClashWarn	  "warning"
	  StrictBusMsg		  "Warning"
	  LoggingUnavailableSignals "error"
	  BlockIODiagnostic	  "none"
	}
	Simulink.HardwareCC {
	  $ObjectID		  6
	  Version		  "1.4.0"
	  ProdBitPerChar	  8
	  ProdBitPerShort	  16
	  ProdBitPerInt		  32
	  ProdBitPerLong	  32
	  ProdIntDivRoundTo	  "Undefined"
	  ProdEndianess		  "Unspecified"
	  ProdWordSize		  32
	  ProdShiftRightIntArith  on
	  ProdHWDeviceType	  "32-bit Generic"
	  TargetBitPerChar	  8
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	  TargetBitPerInt	  32
	  TargetBitPerLong	  32
	  TargetShiftRightIntArith on
	  TargetIntDivRoundTo	  "Undefined"
	  TargetEndianess	  "Unspecified"
	  TargetWordSize	  32
	  TargetTypeEmulationWarnSuppressLevel 0
	  TargetPreprocMaxBitsSint 32
	  TargetPreprocMaxBitsUint 32
	  TargetHWDeviceType	  "Specified"
	  TargetUnknown		  off
	  ProdEqTarget		  on
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	Simulink.ModelReferenceCC {
	  $ObjectID		  7
	  Version		  "1.4.0"
	  UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
	  CheckModelReferenceTargetMessage "error"
	  ModelReferenceNumInstancesAllowed "Multi"
	  ModelReferenceSigSizeVariationType "Always allowed"
	  ModelReferencePassRootInputsByReference on
	  ModelReferenceMinAlgLoopOccurrences off
	}
	Simulink.RTWCC {
	  $BackupClass		  "Simulink.RTWCC"
	  $ObjectID		  8
	  Array {
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	    Cell		    "IncludeHyperlinkInReport"
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	  Version		  "1.4.0"
	  SystemTargetFile	  "grt.tlc"
	  GenCodeOnly		  off
	  MakeCommand		  "make_rtw"
	  GenerateMakefile	  on
	  TemplateMakefile	  "grt_default_tmf"
	  GenerateReport	  off
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	  RetainRTWFile		  off
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	  ProcessScriptMode	  "Default"
	  ConfigurationMode	  "Optimized"
	  ConfigAtBuild		  off
	  IncludeHyperlinkInReport off
	  LaunchReport		  off
	  TargetLang		  "C"
	  IncludeBusHierarchyInRTWFileBlockHierarchyMap	off
	  IncludeERTFirstTime	  on
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	  GenerateTraceReportSl	  off
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	  RTWCompilerOptimization "Off"
	  Array {
	    Type		    "Handle"
	    Dimension		    2
	    Simulink.CodeAppCC {
	      $ObjectID		      9
	      Array {
		Type			"Cell"
		Dimension		9
		Cell			"IgnoreCustomStorageClasses"
		Cell			"InsertBlockDesc"
		Cell			"SFDataObjDesc"
		Cell			"SimulinkDataObjDesc"
		Cell			"DefineNamingRule"
		Cell			"SignalNamingRule"
		Cell			"ParamNamingRule"
		Cell			"InlinedPrmAccess"
		Cell			"CustomSymbolStr"
		PropName		"DisabledProps"
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	      Version		      "1.4.0"
	      ForceParamTrailComments off
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	      PreserveNameWithParent  off
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	      CustomSymbolStrGlobalVar "$R$N$M"
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	      CustomSymbolStrBlkIO    "rtb_$N$M"
	      CustomSymbolStrTmpVar   "$N$M"
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	    Simulink.GRTTargetCC {
	      $BackupClass	      "Simulink.TargetCC"
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	      Array {
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		Cell			"IncludeMdlTerminateFcn"
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		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
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		PropName		"DisabledProps"
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	      Version		      "1.4.0"
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	      IsPILTarget	      off
	      ModelReferenceCompliant on
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	      ParenthesesLevel	      "Nominal"
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	      ModelStepFunctionPrototypeControlCompliant off
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	      ExtModeStaticAlloc      off
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	      ExtModeStaticAllocSize  1000000
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	    PropName		    "Components"
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	PropName		"Components"
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      Name		      "Configuration"
      CurrentDlgPage	      "Solver"
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    PropName		    "ConfigurationSets"
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  Simulink.ConfigSet {
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  BlockDefaults {
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    FontSize		    10
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  BlockParameterDefaults {
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      BlockType		      From
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    Block {
      BlockType		      Goto
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    Block {
      BlockType		      Inport
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      BusObject		      "BusObject"
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      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
      Interpolate	      on
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    Block {
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      BusObject		      "BusObject"
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    Block {
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    Block {
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      SaveName		      "ScopeData"
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      MaxDataPoints	      "5000"
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    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
      SFunctionDeploymentMode off
    }
    Block {
      BlockType		      SubSystem
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      SystemSampleTime	      "-1"
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      RTWFileNameOpts	      "Auto"
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
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    Block {
      BlockType		      Terminator
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    Block {
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      SampleTime	      "inf"
      FramePeriod	      "inf"
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    Block {
      BlockType		      DiscretePulseGenerator
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  System {
    Name		    "warp_timer"
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      BlockType		      Reference
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      RTWMemSecFuncInitTerm   "Inherit from model"
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      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      infoedit		      " System Generator"
      xilinxfamily	      "virtex2p"
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      speed		      "-6"
      package		      "ff1517"
      synthesis_tool	      "XST"
      clock_wrapper	      "Clock Enables"
      directory		      "./pcore_v03"
      testbench		      off
      simulink_period	      "1"
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      dcm_input_clock_period  "100"
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      trim_vbits	      "Everywhere in SubSystem"
      dbl_ovrd		      "According to Block Masks"
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      sg_icon_stat	      "51,50,-1,-1,red,beige,0,07734"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 51 51 0 ],[0 0 50 50 ],[0.93 0.92 0.86]);\npatch([12 4 16 4 12 25 29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 45 37 25 13 5 16 5 5 9 5 5 ],[0.6 0.2 0.25]);\nplot([0 0 51 51 0 ],[0 50 50 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
      sg_blockgui_xml	      "<!--  *  Copyright (c) 2005, Xilinx, Inc.  All Rights Reserved.            --><!--  *  Reproduction or reuse, in any form, without the explicit written  --><!--  *  consent of Xilinx, Inc., is strictly prohibited.                  --><sysgenblock has_userdata=\"true\" tag=\"genX\" block_type=\"sysgen\" simulinkname=\" System Generator\" >\n <icon width=\"51\" bg_color=\"beige\" height=\"50\" caption_format=\"System\\nGenerator\" wmark_color=\"red\" />\n <callbacks DeleteFcn=\"xlSysgenGUI('delete', gcs, gcbh);\" OpenFcn=\"xlSysgenGUI('startup',gcs,gcbh)\" ModelCloseFcn=\"xlSysgenGUI('Close',gcs,gcbh)\" PostSaveFcn=\"xlSysgenGUI('Save')\" />\n <libraries>\n  <library name=\"xbsIndex\" />\n  <library name=\"xbsBasic\" />\n  <library name=\"xbsTools\" />\n </libraries>\n <subsystem_model file=\"system_generator_subsystem.mdl\" />\n <blockgui label=\"Xilinx System Generator\" >\n  <editbox evaluate=\"false\" multi_line=\"true\" name=\"infoedit\" read_only=\"true\" default=\" System Generator\" />\n  <editbox evaluate=\"false\" name=\"xilinxfamily\" default=\"Virtex4\" label=\"Xilinx family\" />\n  <editbox evaluate=\"false\" name=\"part\" default=\"xc4vsx35\" label=\"Part\" />\n  <editbox evaluate=\"false\" name=\"speed\" default=\"-10\" label=\"Speed\" />\n  <editbox evaluate=\"false\" name=\"package\" default=\"ff668\" label=\"Package\" />\n  <listbox evaluate=\"true\" name=\"synthesis_tool\" default=\"XST\" label=\"Synthesis tool\" >\n   <item value=\"Spectrum\" />\n   <item value=\"Synplify\" />\n   <item value=\"Synplify Pro\" />\n   <item value=\"XST\" />\n   <item value=\"Precision\" />\n  </listbox>\n  <editbox evaluate=\"false\" name=\"directory\" default=\"./netlist\" label=\"Target directory\" />\n  <checkbox evaluate=\"true\" name=\"testbench\" default=\"off\" label=\"Testbench\" />\n  <editbox evaluate=\"true\" name=\"simulink_period\" default=\"1\" label=\"Simulink period\" />\n  <editbox evaluate=\"true\" name=\"sysclk_period\" default=\"10\" label=\"System clock period\" />\n  <checkbox evaluate=\"true\" name=\"incr_netlist\" default=\"off\" label=\"Incremental netlisting\" />\n  <listbox evaluate=\"true\" name=\"trim_vbits\" default=\"Everywhere in SubSystem\" label=\"Trim valid bits\" >\n   <item value=\"According to Block Masks\" />\n   <item value=\"Everywhere in SubSystem\" />\n   <item value=\"No Where in SubSystem\" />\n  </listbox>\n  <listbox evaluate=\"true\" name=\"dbl_ovrd\" default=\"According to Block Masks\" label=\"Override with doubles\" >\n   <item value=\"According to Block Masks\" />\n   <item value=\"Everywhere in SubSystem\" />\n   <item value=\"No Where in SubSystem\" />\n  </listbox>\n  <listbox evaluate=\"true\" name=\"core_generation\" default=\"According to Block Masks\" label=\"Generate cores\" >\n   <item value=\"According to Block Masks\" />\n   <item value=\"Everywhere Available\" />\n   <item value=\"Not Needed - Already Generated\" />\n  </listbox>\n  <checkbox evaluate=\"true\" name=\"run_coregen\" default=\"off\" label=\"Run CoreGen\" />\n  <checkbox evaluate=\"true\" name=\"deprecated_control\" default=\"off\" label=\"Show deprecated controls\" />\n  <hiddenvar evaluate=\"true\" name=\"eval_field\" default=\"0\" />\n </blockgui>\n</sysgenblock>\n"
    }
    Block {
      BlockType		      Reference
      Name		      "BitBasher"
      Ports		      [3, 1]
      Position		      [480, 77, 515, 173]
      SourceBlock	      "xbsIndex_r4/BitBasher"
      SourceType	      "Xilinx BitBasher Block"
      infoedit		      "Allows extraction, concatenation and augmentation of bits"
      bitexpr		      "<html><head><meta name=\"qrichtext\" content=\"1\" /><style type=\"text/css\">\np, li { white-space: pre-wrap; }\n</style></head><body style=\" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;\">\n<p style=\" margin-top:12px; margin-bottom:12px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg'; font-size:8pt;\">Q={1'b0,a,b,c}<br /></p></body></html>"
      display_expr	      off
      sr_1		      "1"
      arith_type1	      "Unsigned"
      bin_pt1		      "0"
      sr_2		      "2"
      arith_type2	      "Unsigned"
      bin_pt2		      "0"
      sr_3		      "3"
      arith_type3	      "Unsigned"
      bin_pt3		      "0"
      sr_4		      "4"
      arith_type4	      "Unsigned"
      bin_pt4		      "0"
      dbl_ovrd		      off
      has_advanced_control    "0"
      sggui_pos		      "20,20,336,351"
      block_type	      "bitbasher"
      block_version	      "10.1.3"
      sg_icon_stat	      "35,96,3,1,white,blue,0,4b085ed4,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([17 7 21 7 17 33 37 41 58 45 32 23 38 23 32 45 58 41 37 33 17 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      Reference
      Name		      "BitBasher1"
      Ports		      [3, 1]
      Position		      [480, 212, 515, 308]
      SourceBlock	      "xbsIndex_r4/BitBasher"
      SourceType	      "Xilinx BitBasher Block"
      infoedit		      "Allows extraction, concatenation and augmentation of bits"
      bitexpr		      "<html><head><meta name=\"qrichtext\" content=\"1\" /><style type=\"text/css\">\np, li { white-space: pre-wrap; }\n</style></head><body style=\" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;\">\n<p style=\" margin-top:12px; margin-bottom:12px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg'; font-size:8pt;\">Q={1'b0,a,b,c}<br /></p></body></html>"
      display_expr	      off
      sr_1		      "1"
      arith_type1	      "Unsigned"
      bin_pt1		      "0"
      sr_2		      "2"
      arith_type2	      "Unsigned"
      bin_pt2		      "0"
      sr_3		      "3"
      arith_type3	      "Unsigned"
      bin_pt3		      "0"
      sr_4		      "4"
      arith_type4	      "Unsigned"
      bin_pt4		      "0"
      dbl_ovrd		      off
      has_advanced_control    "0"
      sggui_pos		      "20,20,336,351"
      block_type	      "bitbasher"
      block_version	      "10.1.3"
      sg_icon_stat	      "35,96,3,1,white,blue,0,4b085ed4,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([17 7 21 7 17 33 37 41 58 45 32 23 38 23 32 45 58 41 37 33 17 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      Reference
      Name		      "BitBasher2"
      Ports		      [3, 1]
      Position		      [480, 347, 515, 443]
      SourceBlock	      "xbsIndex_r4/BitBasher"
      SourceType	      "Xilinx BitBasher Block"
      infoedit		      "Allows extraction, concatenation and augmentation of bits"
      bitexpr		      "<html><head><meta name=\"qrichtext\" content=\"1\" /><style type=\"text/css\">\np, li { white-space: pre-wrap; }\n</style></head><body style=\" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;\">\n<p style=\" margin-top:12px; margin-bottom:12px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg'; font-size:8pt;\">Q={1'b0,a,b,c}<br /></p></body></html>"
      display_expr	      off
      sr_1		      "1"
      arith_type1	      "Unsigned"
      bin_pt1		      "0"
      sr_2		      "2"
      arith_type2	      "Unsigned"
      bin_pt2		      "0"
      sr_3		      "3"
      arith_type3	      "Unsigned"
      bin_pt3		      "0"
      sr_4		      "4"
      arith_type4	      "Unsigned"
      bin_pt4		      "0"
      dbl_ovrd		      off
      has_advanced_control    "0"
      sggui_pos		      "20,20,336,351"
      block_type	      "bitbasher"
      block_version	      "10.1.3"
      sg_icon_stat	      "35,96,3,1,white,blue,0,4b085ed4,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([17 7 21 7 17 33 37 41 58 45 32 23 38 23 32 45 58 41 37 33 17 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      Reference
      Name		      "BitBasher3"
      Ports		      [3, 1]
      Position		      [480, 487, 515, 583]
      SourceBlock	      "xbsIndex_r4/BitBasher"
      SourceType	      "Xilinx BitBasher Block"
      infoedit		      "Allows extraction, concatenation and augmentation of bits"
      bitexpr		      "<html><head><meta name=\"qrichtext\" content=\"1\" /><style type=\"text/css\">\np, li { white-space: pre-wrap; }\n</style></head><body style=\" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;\">\n<p style=\" margin-top:12px; margin-bottom:12px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg'; font-size:8pt;\">Q={1'b0,a,b,c}<br /></p></body></html>"
      display_expr	      off
      sr_1		      "1"
      arith_type1	      "Unsigned"
      bin_pt1		      "0"
      sr_2		      "2"
      arith_type2	      "Unsigned"
      bin_pt2		      "0"
      sr_3		      "3"
      arith_type3	      "Unsigned"
      bin_pt3		      "0"
      sr_4		      "4"
      arith_type4	      "Unsigned"
      bin_pt4		      "0"
      dbl_ovrd		      off
      has_advanced_control    "0"
      sggui_pos		      "20,20,336,351"
      block_type	      "bitbasher"
      block_version	      "10.1.3"
      sg_icon_stat	      "35,96,3,1,white,blue,0,4b085ed4,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([17 7 21 7 17 33 37 41 58 45 32 23 38 23 32 45 58 41 37 33 17 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      Reference
      Name		      "BitBasher4"
      Ports		      [3, 1]
      Position		      [1010, 67, 1045, 163]
      SourceBlock	      "xbsIndex_r4/BitBasher"
      SourceType	      "Xilinx BitBasher Block"
      infoedit		      "Allows extraction, concatenation and augmentation of bits"
      bitexpr		      "<html><head><meta name=\"qrichtext\" content=\"1\" /><style type=\"text/css\">\np, li { white-space: pre-wrap; }\n</style></head><body style=\" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;\">\n<p style=\" margin-top:12px; margin-bottom:12px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg'; font-size:8pt;\">Q={1'b0,a,b,c}<br /></p></body></html>"
      display_expr	      off
      sr_1		      "1"
      arith_type1	      "Unsigned"
      bin_pt1		      "0"
      sr_2		      "2"
      arith_type2	      "Unsigned"
      bin_pt2		      "0"
      sr_3		      "3"
      arith_type3	      "Unsigned"
      bin_pt3		      "0"
      sr_4		      "4"
      arith_type4	      "Unsigned"
      bin_pt4		      "0"
      dbl_ovrd		      off
      has_advanced_control    "0"
      sggui_pos		      "20,20,336,351"
      block_type	      "bitbasher"
      block_version	      "10.1.3"
      sg_icon_stat	      "35,96,3,1,white,blue,0,4b085ed4,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([17 7 21 7 17 33 37 41 58 45 32 23 38 23 32 45 58 41 37 33 17 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      Reference
      Name		      "BitBasher5"
      Ports		      [3, 1]
      Position		      [1010, 202, 1045, 298]
      SourceBlock	      "xbsIndex_r4/BitBasher"
      SourceType	      "Xilinx BitBasher Block"
      infoedit		      "Allows extraction, concatenation and augmentation of bits"
      bitexpr		      "<html><head><meta name=\"qrichtext\" content=\"1\" /><style type=\"text/css\">\np, li { white-space: pre-wrap; }\n</style></head><body style=\" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;\">\n<p style=\" margin-top:12px; margin-bottom:12px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg'; font-size:8pt;\">Q={1'b0,a,b,c}<br /></p></body></html>"
      display_expr	      off
      sr_1		      "1"
      arith_type1	      "Unsigned"
      bin_pt1		      "0"
      sr_2		      "2"
      arith_type2	      "Unsigned"
      bin_pt2		      "0"
      sr_3		      "3"
      arith_type3	      "Unsigned"
      bin_pt3		      "0"
      sr_4		      "4"
      arith_type4	      "Unsigned"
      bin_pt4		      "0"
      dbl_ovrd		      off
      has_advanced_control    "0"
      sggui_pos		      "20,20,336,351"
      block_type	      "bitbasher"
      block_version	      "10.1.3"
      sg_icon_stat	      "35,96,3,1,white,blue,0,4b085ed4,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([17 7 21 7 17 33 37 41 58 45 32 23 38 23 32 45 58 41 37 33 17 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      Reference
      Name		      "BitBasher6"
      Ports		      [3, 1]
      Position		      [1010, 337, 1045, 433]
      SourceBlock	      "xbsIndex_r4/BitBasher"
      SourceType	      "Xilinx BitBasher Block"
      infoedit		      "Allows extraction, concatenation and augmentation of bits"
      bitexpr		      "<html><head><meta name=\"qrichtext\" content=\"1\" /><style type=\"text/css\">\np, li { white-space: pre-wrap; }\n</style></head><body style=\" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;\">\n<p style=\" margin-top:12px; margin-bottom:12px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg'; font-size:8pt;\">Q={1'b0,a,b,c}<br /></p></body></html>"
      display_expr	      off
      sr_1		      "1"
      arith_type1	      "Unsigned"
      bin_pt1		      "0"
      sr_2		      "2"
      arith_type2	      "Unsigned"
      bin_pt2		      "0"
      sr_3		      "3"
      arith_type3	      "Unsigned"
      bin_pt3		      "0"
      sr_4		      "4"
      arith_type4	      "Unsigned"
      bin_pt4		      "0"
      dbl_ovrd		      off
      has_advanced_control    "0"
      sggui_pos		      "20,20,336,351"
      block_type	      "bitbasher"
      block_version	      "10.1.3"
      sg_icon_stat	      "35,96,3,1,white,blue,0,4b085ed4,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([17 7 21 7 17 33 37 41 58 45 32 23 38 23 32 45 58 41 37 33 17 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      Reference
      Name		      "BitBasher7"
      Ports		      [3, 1]
      Position		      [1010, 477, 1045, 573]
      SourceBlock	      "xbsIndex_r4/BitBasher"
      SourceType	      "Xilinx BitBasher Block"
      infoedit		      "Allows extraction, concatenation and augmentation of bits"
      bitexpr		      "<html><head><meta name=\"qrichtext\" content=\"1\" /><style type=\"text/css\">\np, li { white-space: pre-wrap; }\n</style></head><body style=\" font-family:'MS Shell Dlg 2'; font-size:8.25pt; font-weight:400; font-style:normal;\">\n<p style=\" margin-top:12px; margin-bottom:12px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-family:'MS Shell Dlg'; font-size:8pt;\">Q={1'b0,a,b,c}<br /></p></body></html>"
      display_expr	      off
      sr_1		      "1"
      arith_type1	      "Unsigned"
      bin_pt1		      "0"
      sr_2		      "2"
      arith_type2	      "Unsigned"
      bin_pt2		      "0"
      sr_3		      "3"
      arith_type3	      "Unsigned"
      bin_pt3		      "0"
      sr_4		      "4"
      arith_type4	      "Unsigned"
      bin_pt4		      "0"
      dbl_ovrd		      off
      has_advanced_control    "0"
      sggui_pos		      "20,20,336,351"
      block_type	      "bitbasher"
      block_version	      "10.1.3"
      sg_icon_stat	      "35,96,3,1,white,blue,0,4b085ed4,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([17 7 21 7 17 33 37 41 58 45 32 23 38 23 32 45 58 41 37 33 17 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      Constant
      Name		      "Constant"
      Position		      [25, 176, 45, 194]
      ShowName		      off
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
    }
    Block {
      BlockType		      SubSystem
      Name		      "EDK Processor"
      Ports		      []
      Position		      [449, 687, 500, 737]
      CopyFcn		      "xlProcBlockCopyCallback(gcbh);xlBlockMoveCallback(gcbh);"
      DeleteFcn		      "xlDestroyGui(gcbh);"
      LoadFcn		      "xlBlockLoadCallback(gcbh);"
      ModelCloseFcn	      "xlDestroyGui(gcbh);"
      PreSaveFcn	      "xlBlockPreSaveCallback(gcbh);"
      PostSaveFcn	      "xlBlockPostSaveCallback(gcbh);"
      DestroyFcn	      "xlDestroyGui(gcbh);"
      OpenFcn		      "bh=gcbh;xlProcBlockCallbacks('populatesharedmemorylistbox',bh);xlOpenGui(bh, 'edkprocessor_gui.xml', @xlProcBlockEnablement, @xlProcBlockAction)"
      CloseFcn		      "xlDestroyGui(gcbh);"
      MoveFcn		      "xlBlockMoveCallback(gcbh);"
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      MaskType		      "Xilinx EDK Processor Block"
      MaskDescription	      "Xilinx EDK Processor"
      MaskHelp		      "eval('');xlDoc('-book','sysgen','-topic','EDK_Processor');"
      MaskPromptString	      "Configure Processor for|EDK Project| |Available Memories| | |Bus Type|Base Address| |Lock| |Dual Clocks| |Register Read-Back|Constraint file| |Inherit Device Type| | | | | | | | | | | | | | | | "
      MaskStyleString	      "popup(EDK pcore generation|HDL netlisting),edit,edit,popup(<empty>),edit,edit,popup(PLB|FSL),edit,edit,checkbox,edit,checkbox,edit,checkbox,edit,edit,checkbox,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit"
      MaskTunableValueString  "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on"
      MaskCallbackString      "||||||||||||||||||||||||||||||||"
      MaskEnableString	      "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on"
      MaskVisibilityString    "on,on,off,on,on,off,on,on,off,on,off,on,off,on,on,off,on,off,off,off,off,off,off,off,off,off,off,off,off,off,off,off,off"
      MaskToolTipString	      "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on"
      MaskVarAliasString      ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
      MaskVariables	      "mode=&1;xmp=&2;MemVisToProc=&3;AvailableMemories=&4;portInterfaceTable=&5;bus_type_sgadvanced=&6;bus_type=@7;baseaddr=&8;baseaddr_lock_sgadvanced=&9;baseaddr_lock=@10;dual_clock_sgadvanced=&11;dual_clock=@12;reg_readback_sgadvanced=&13;reg_readback=@14;ucf_file=&15;inheritDeviceType_sgadvanced=&16;inheritDeviceType=@17;clock_name=&18;internalPortList=&19;resetPolarity=&20;memxtable=&21;procinfo=&22;memmapdirty=&23;blockname=&24;xpsintstyle=&25;has_advanced_control=@26;sggui_pos=&27;block_type=&28;block_version=&29;sg_icon_stat=&30;sg_mask_display=&31;sg_list_contents=&32;sg_blockgui_xml=&33;"
      MaskInitialization      "try\n  tmp_gcb = gcb;\n  tmp_gcbh = gcbh;\n  if (strcmp('SysGenIndex',get_param(bdroot(tmp_gcbh),'tag')) && ~isempty(regexp(bdroot(tmp_gcb), '^xbs', 'once')))\n    return;\n  end;\n  xlMungeMaskParams;\n\nblock_type='edkprocessor';\n  serialized_declarations = '{,''block_type''=>''String''}';\n  xledkprocessor_init();\n  ptable_ = xlblockprep(get_param(tmp_gcb, 'MaskWSVariables'));\ncatch\n  global dbgsysgen;\n  if(~isempty(dbgsysgen) && dbgsysgen)\n    e = regexprep(lasterr, '\\n', '\\nError: ');\n    disp(['Error: While running MaskInit code on block ' tmp_gcb ': ' e]);\n    error(e);\n  end\nend\n"
      MaskDisplay	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 51 51 0 ],[0 0 50 50 ],[0.77 0.82 0.91]);\npatch([12 4 16 4 12 25 29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 45 37 25 13 5 16 5 5 9 5 5 ],[0.98 0.96 0.92]);\nplot([0 51 51 0 0 ],[0 0 50 50 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ndisp('');\n\nfprintf('','COMMENT: end icon text');\n"
      MaskSelfModifiable      on
      MaskIconFrame	      off
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      MaskValueString	      "EDK pcore generation||<qt bgcolor=\"#FFFFFF\"><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer0_slotCount&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer1_slotCount&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer2_slotCount&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer3_slotCount&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer4_slotCount&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer5_slotCount&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer6_slotCount&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer7_slotCount&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer_control&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timer_status&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timers01_slotTime&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timers23_slotTime&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timers45_slotTime&gt;&gt;<br></div><div><img src=\"C:\\Xilinx\\10.1\\DSP_Tools\\common\\bin\\..\\..\\sysgen\\data\\images\\registerplus.gif\"> &lt;&lt;timers67_slotTime&gt;&gt;<br></div></qt>|<empty>|{'exposed'=>[],'portdir'=>[],'portname'=>[],'shortname'=>[]}||PLB|0x80000000||off||off||on|||off|plb|{}|0|{'mlist'=>['warp_timer/Registers/From Register9','warp_timer/Registers/From Register1','warp_timer/Registers/From Register3','warp_timer/Registers/From Register2','warp_timer/Registers/From Register7','warp_timer/Registers/From Register4','warp_timer/Registers/From Register6','warp_timer/Registers/From Register5','warp_timer/Registers/From Register8','warp_timer/Registers/To Register4','warp_timer/Registers/From Register11','warp_timer/Registers/From Register12','warp_timer/Registers/From Register13','warp_timer/Registers/From Register14'],'mlname'=>['\\'timer0_slotCount\\'','\\'timer1_slotCount\\'','\\'timer2_slotCount\\'','\\'timer3_slotCount\\'','\\'timer4_slotCount\\'','\\'timer5_slotCount\\'','\\'timer6_slotCount\\'','\\'timer7_slotCount\\'','\\'timer_control\\'','\\'timer_status\\'','\\'timers01_slotTime\\'','\\'timers23_slotTime\\'','\\'timers45_slotTime\\'','\\'timers67_slotTime\\''],'mlstate'=>[0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000]}|{'xmliface'=>'Xilinx//microblaze//iface.xml'}|off||default|0|20,20,383,441|edkprocessor|2.5|51,50,-1,-1,white,blue,0,07734,right|fprintf('','COMMENT: begin icon graphics');\npatch([0 51 51 0 ],[0 0 50 50 ],[0.77 0.82 0.91]);\npatch([12 4 16 4 12 25 29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 45 37 25 13 5 16 5 5 9 5 5 ],[0.98 0.96 0.92]);\nplot([0 51 51 0 0 ],[0 0 50 50 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n|{'table'=>{'AvailableMemories'=>'popup(<empty>)','userSelections'=>{'AvailableMemories'=>'<empty>'}}}|"
      MaskTabNameString	      ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,"
      System {
	Name			"EDK Processor"
	Location		[514, 91, 900, 269]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Constant
	  Name			  "Constant"
	  Position		  [40, 485, 60, 505]
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant1"
	  Position		  [40, 555, 60, 575]
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [40, 625, 60, 645]
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant3"
	  Position		  [40, 690, 60, 710]
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [40, 760, 60, 780]
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant5"
	  Ports			  [0, 1]
	  Position		  [20, 412, 75, 438]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  "on"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "55,26,1,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "Sl_wait"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant6"
	  Position		  [40, 855, 60, 875]
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register"
	  Ports			  [0, 1]
	  Position		  [400, 947, 460, 1003]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer_status'"
	  init			  "0"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  ownership		  "Owned and initialized elsewhere"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer_status_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "PLB_ABus"
	  Ports			  [1, 1]
	  Position		  [175, 555, 245, 575]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_ABus'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "70,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "PLB_ABus"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "PLB_PAValid"
	  Ports			  [1, 1]
	  Position		  [175, 625, 245, 645]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "1"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_PAValid'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "70,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "PLB_PAValid"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "PLB_RNW"
	  Ports			  [1, 1]
	  Position		  [175, 690, 245, 710]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "1"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_RNW'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "70,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "PLB_RNW"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "PLB_wrDBus"
	  Ports			  [1, 1]
	  Position		  [175, 760, 245, 780]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_wrDBus'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "70,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "PLB_wrDBus"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "SPLB_Rst"
	  Ports			  [1, 1]
	  Position		  [175, 485, 245, 505]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "1"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'SPLB_Rst'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "70,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "SPLB_Rst"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_addrAck"
	  Ports			  [1, 1]
	  Position		  [670, 75, 730, 95]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_addrAck'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_rdComp"
	  Ports			  [1, 1]
	  Position		  [670, 165, 730, 185]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdComp'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_rdDAck"
	  Ports			  [1, 1]
	  Position		  [670, 1265, 730, 1285]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDAck'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_rdDBus"
	  Ports			  [1, 1]
	  Position		  [670, 1615, 730, 1635]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDBus'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_wait"
	  Ports			  [1, 1]
	  Position		  [180, 415, 240, 435]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wait'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_wrComp"
	  Ports			  [1, 1]
	  Position		  [670, 445, 730, 465]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrComp'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sl_wrDAck"
	  Ports			  [1, 1]
	  Position		  [670, 280, 730, 300]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrDAck'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator"
	  Position		  [905, 50, 925, 70]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator1"
	  Position		  [905, 115, 925, 135]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator2"
	  Position		  [905, 1690, 925, 1710]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator3"
	  Position		  [905, 1760, 925, 1780]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator4"
	  Position		  [420, 415, 440, 435]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator5"
	  Position		  [905, 185, 925, 205]
	  ShowName		  off
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator6"
	  Position		  [905, 255, 925, 275]
	  ShowName		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register"
	  Ports			  [2, 1]
	  Position		  [885, 322, 945, 378]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer0_slotCount'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer0_slotCount_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register1"
	  Ports			  [2, 1]
	  Position		  [885, 427, 945, 483]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer1_slotCount'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer1_slotCount_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register10"
	  Ports			  [2, 1]
	  Position		  [885, 1377, 945, 1433]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timers23_slotTime'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timers23_slotTime_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register11"
	  Ports			  [2, 1]
	  Position		  [885, 1482, 945, 1538]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timers45_slotTime'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timers45_slotTime_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register12"
	  Ports			  [2, 1]
	  Position		  [885, 1587, 945, 1643]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timers67_slotTime'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timers67_slotTime_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register2"
	  Ports			  [2, 1]
	  Position		  [885, 532, 945, 588]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer2_slotCount'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer2_slotCount_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register3"
	  Ports			  [2, 1]
	  Position		  [885, 637, 945, 693]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer3_slotCount'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer3_slotCount_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register4"
	  Ports			  [2, 1]
	  Position		  [885, 742, 945, 798]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer4_slotCount'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer4_slotCount_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register5"
	  Ports			  [2, 1]
	  Position		  [885, 847, 945, 903]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer5_slotCount'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer5_slotCount_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register6"
	  Ports			  [2, 1]
	  Position		  [885, 952, 945, 1008]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer6_slotCount'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer6_slotCount_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register7"
	  Ports			  [2, 1]
	  Position		  [885, 1057, 945, 1113]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer7_slotCount'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer7_slotCount_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register8"
	  Ports			  [2, 1]
	  Position		  [885, 1167, 945, 1223]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer_control'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timer_control_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register9"
	  Ports			  [2, 1]
	  Position		  [885, 1272, 945, 1328]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timers01_slotTime'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  "on"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "60,56,1,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "timers01_slotTime_dout"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "plb_decode"
	  Ports			  [7, 9]
	  Position		  [345, 484, 515, 896]
	  SourceBlock		  "xbsIndex_r4/MCode"
	  SourceType		  "Xilinx MCode Block Block"
	  infoedit		  "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of the block are input arguments of the function. The output ports of the block are output arguments of the function."
	  mfname		  "xlmax"
	  explicit_period	  "off"
	  period		  "1"
	  dbl_ovrd		  "off"
	  enable_stdout		  "off"
	  enable_debug		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  mfilecontent		  "function [wrDBusReg, addrAck, rdComp, wrDAck, bankAddr, RNWReg, rdDAck, rdDBus, linearAddr] = ...\n    plb_bus_decode(plbRst, plbABus, plbPAValid, plbRNW, plbWrDBus, rdData, addrPref)\n\n% constant variables (TODO: should pass from outside)\nADDRPREF_LEN = 20;\nBANKADDR_LEN = 2;\nLINEARADDR_LEN = 8;\nABUS_LEN = 32;\nDBUS_LEN = 32;\n\n% declare and initialize persistent variables\n% register input bus signals\npersistent plbRstReg_, plbRstReg_ = xl_state(0, {xlBoolean});\npersistent plbABusReg_, plbABusReg_ = xl_state(0, {xlUnsigned, ABUS_LEN, 0});\npersistent plbPAValidReg_, plbPAValidReg_ = xl_state(0, {xlBoolean});\npersistent plbRNWReg_, plbRNWReg_ = xl_state(0, {xlUnsigned, 1, 0});\npersistent plbWrDBusReg_, plbWrDBusReg_ = xl_state(0, {xlUnsigned, DBUS_LEN, 0});\n\n% ===== rest of the outputs =====\n\nbankAddr   = xl_slice(plbABusReg_, 2+BANKADDR_LEN+LINEARADDR_LEN-1, 2+LINEARADDR_LEN);\nlinearAddr = xl_slice(plbABusReg_, 2+LINEARADDR_LEN-1, 2);\nRNWReg = plbRNWReg_;\nwrDBusReg = plbWrDBusReg_;\n\n% ===== p_select =====\n\n% register PAValid\npersistent aValidReg, aValidReg = xl_state(0, {xlBoolean});\naValidReg = plbPAValidReg_;\n\n% extract and register the address prefix\naddrPref_in = xl_slice(plbABusReg_, xl_nbits(plbABusReg_)-1, xl_nbits(plbABusReg_)-ADDRPREF_LEN);\nif addrPref_in == addrPref\n    ps1 = true;\nelse \n    ps1 = false;\nend \n\npersistent ps1Reg, ps1Reg = xl_state(0, ps1);\nps1Reg = ps1;\n\nps = xl_and(ps1Reg, aValidReg);\n\n% ===== addrAck =====\n\n% register ps\npersistent psReg, psReg = xl_state(0, ps);\n\naddrAck = xfix({xlUnsigned, 1, 0}, xl_and(xl_not(plbRstReg_), ps, xl_not(psReg)));\n\npsReg = ps;\n\n% ===== rdComp, rd/wr DAck =====\n \nrdComp1 = xfix({xlUnsigned, 1, 0}, xl_and(addrAck, RNWReg));\n\nNUM_rdCompDelay = 3;\npersistent rdCompDelay, rdCompDelay = xl_state(zeros(1, NUM_rdCompDelay), rdComp1, NUM_rdCompDelay);\nrdComp2 = rdCompDelay.back;\nrdCompDelay.push_front_pop_back(rdComp1);\n\npersistent rdCompReg, rdCompReg = xl_state(0, rdComp1);\nrdComp = rdCompReg;\nrdCompReg = rdComp2;\n\npersistent rdDAckReg, rdDAckReg = xl_state(0, rdComp1);\nrdDAck = rdDAckReg;\nrdDAckReg = rdComp;\n\npersistent wrDAckReg, wrDAckReg = xl_state(0, addrAck);\nwrDAck = wrDAckReg;\nwrDAckReg = xl_and(addrAck, xl_not(RNWReg));\n\n% ===== rdDBus =====\n\nrdSel = xl_or(rdComp2, rdComp);\n\nif rdSel == 1\n    rdDBus1 = rdData;\nelse\n    rdDBus1 = 0;\nend % if\n\npersistent rdDBusReg, rdDBusReg = xl_state(0, rdDBus1);\nrdDBus = rdDBusReg;\nrdDBusReg = rdDBus1;\n\n% rdDBus = xl_concat(rdDBus32, rdDBus32);\n% rdDBus = rdDBus32;\n\n% ===== update the persistent variables =====\n\nplbRstReg_ = plbRst;\nplbABusReg_ = plbABus;\nplbPAValidReg_ = plbPAValid;\nplbRNWReg_ = plbRNW;\nplbWrDBusReg_ = xl_slice(plbWrDBus, DBUS_LEN-1, 0);\n"
	  suppress_output	  "1"
	  defparams		  "{}"
	  hide_port_list	  "{}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mcode"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "170,412,1,1,white,blue,0,8b15b975,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 ],[0 0 412 412 ],[0.77 0.82 0.91]);\npatch([40 12 52 12 40 85 97 109 157 119 83 57 97 57 83 119 157 109 97 85 40 ],[139 167 207 247 275 275 263 275 275 237 273 247 207 167 141 177 139 139 151 139 139 ],[0.98 0.96 0.92]);\nplot([0 170 170 0 0 ],[0 0 412 412 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'plbRst');\ncolor('black');port_label('input',2,'plbABus');\ncolor('black');port_label('input',3,'plbPAValid');\ncolor('black');port_label('input',4,'plbRNW');\ncolor('black');port_label('input',5,'plbWrDBus');\ncolor('black');port_label('input',6,'rdData');\ncolor('black');port_label('input',7,'addrPref');\ncolor('black');port_label('output',1,'wrDBusReg');\ncolor('black');port_label('output',2,'addrAck');\ncolor('black');port_label('output',3,'rdComp');\ncolor('black');port_label('output',4,'wrDAck');\ncolor('black');port_label('output',5,'bankAddr');\ncolor('black');port_label('output',6,'RNWReg');\ncolor('black');port_label('output',7,'rdDAck');\ncolor('black');port_label('output',8,'rdDBus');\ncolor('black');port_label('output',9,'linearAddr');\ncolor('black');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "wrDBusReg"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    2
	    Name		    "Sl_addrAck"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    3
	    Name		    "Sl_rdComp"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    4
	    Name		    "Sl_wrDAck"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    5
	    Name		    "bankAddr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    6
	    Name		    "RNWReg"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    7
	    Name		    "Sl_rdDAck"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    8
	    Name		    "Sl_rdDBus"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    9
	    Name		    "linearAddr"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "plb_memmap"
	  Ports			  [19, 27]
	  Position		  [615, 805, 785, 1075]
	  SourceBlock		  "xbsIndex_r4/MCode"
	  SourceType		  "Xilinx MCode Block Block"
	  infoedit		  "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of the block are input arguments of the function. The output ports of the block are output arguments of the function."
	  mfname		  "xlmax"
	  explicit_period	  "off"
	  period		  "1"
	  dbl_ovrd		  "off"
	  enable_stdout		  "off"
	  enable_debug		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  mfilecontent		  "function [read_bank_out, sm_timer0_slotCount_din, sm_timer0_slotCount_en, sm_timer1_slotCount_din, sm_timer1_slotCount_en, sm_timer2_slotCount_din, sm_timer2_slotCount_en, sm_timer3_slotCount_din, sm_timer3_slotCount_en, sm_timer4_slotCount_din, sm_timer4_slotCount_en, sm_timer5_slotCount_din, sm_timer5_slotCount_en, sm_timer6_slotCount_din, sm_timer6_slotCount_en, sm_timer7_slotCount_din, sm_timer7_slotCount_en, sm_timer_control_din, sm_timer_control_en, sm_timers01_slotTime_din, sm_timers01_slotTime_en, sm_timers23_slotTime_din, sm_timers23_slotTime_en, sm_timers45_slotTime_din, sm_timers45_slotTime_en, sm_timers67_slotTime_din, sm_timers67_slotTime_en] = plb_memmap(wrDBus, bankAddr, linearAddr, RNWReg, addrAck, sm_timer_status, sm_timer0_slotCount, sm_timer1_slotCount, sm_timer2_slotCount, sm_timer3_slotCount, sm_timer4_slotCount, sm_timer5_slotCount, sm_timer6_slotCount, sm_timer7_slotCount, sm_timer_control, sm_timers01_slotTime, sm_timers23_slotTime, sm_timers45_slotTime, sm_timers67_slotTime)\n\n\n% connvert the input data to UFix_32_0 (the bus data type)\n% 'From Register' blocks\n% sm_timer_status_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer_status_bus = xl_force(sm_timer_status, xlUnsigned, 0);\n\n% 'To Register' blocks\n\n% sm_timer0_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer0_slotCount_dout = xl_force(sm_timer0_slotCount, xlUnsigned, 0);\n\n% sm_timer1_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer1_slotCount_dout = xl_force(sm_timer1_slotCount, xlUnsigned, 0);\n\n% sm_timer2_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer2_slotCount_dout = xl_force(sm_timer2_slotCount, xlUnsigned, 0);\n\n% sm_timer3_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer3_slotCount_dout = xl_force(sm_timer3_slotCount, xlUnsigned, 0);\n\n% sm_timer4_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer4_slotCount_dout = xl_force(sm_timer4_slotCount, xlUnsigned, 0);\n\n% sm_timer5_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer5_slotCount_dout = xl_force(sm_timer5_slotCount, xlUnsigned, 0);\n\n% sm_timer6_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer6_slotCount_dout = xl_force(sm_timer6_slotCount, xlUnsigned, 0);\n\n% sm_timer7_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer7_slotCount_dout = xl_force(sm_timer7_slotCount, xlUnsigned, 0);\n\n% sm_timer_control_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer_control_dout = xl_force(sm_timer_control, xlUnsigned, 0);\n\n% sm_timers01_slotTime_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timers01_slotTime_dout = xl_force(sm_timers01_slotTime, xlUnsigned, 0);\n\n% sm_timers23_slotTime_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timers23_slotTime_dout = xl_force(sm_timers23_slotTime, xlUnsigned, 0);\n\n% sm_timers45_slotTime_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timers45_slotTime_dout = xl_force(sm_timers45_slotTime, xlUnsigned, 0);\n\n% sm_timers67_slotTime_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timers67_slotTime_dout = xl_force(sm_timers67_slotTime, xlUnsigned, 0);\n\n\n% 'From FIFO' blocks\n% 'To FIFO' blocks\n% 'Shared Memory' blocks\n\n% 'dout' ports of 'From Register' blocks\n\n% registered register mux output\npersistent reg_bank_out_reg; reg_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nreg_bank_out = reg_bank_out_reg;\n\nif linearAddr == 13\n    reg_bank_out_reg = sm_timer_status_bus;\nelseif linearAddr == 0\n    reg_bank_out_reg = sm_timer0_slotCount_dout;\nelseif linearAddr == 1\n    reg_bank_out_reg = sm_timer1_slotCount_dout;\nelseif linearAddr == 2\n    reg_bank_out_reg = sm_timer2_slotCount_dout;\nelseif linearAddr == 3\n    reg_bank_out_reg = sm_timer3_slotCount_dout;\nelseif linearAddr == 4\n    reg_bank_out_reg = sm_timer4_slotCount_dout;\nelseif linearAddr == 5\n    reg_bank_out_reg = sm_timer5_slotCount_dout;\nelseif linearAddr == 6\n    reg_bank_out_reg = sm_timer6_slotCount_dout;\nelseif linearAddr == 7\n    reg_bank_out_reg = sm_timer7_slotCount_dout;\nelseif linearAddr == 8\n    reg_bank_out_reg = sm_timer_control_dout;\nelseif linearAddr == 9\n    reg_bank_out_reg = sm_timers01_slotTime_dout;\nelseif linearAddr == 10\n    reg_bank_out_reg = sm_timers23_slotTime_dout;\nelseif linearAddr == 11\n    reg_bank_out_reg = sm_timers45_slotTime_dout;\nelseif linearAddr == 12\n    reg_bank_out_reg = sm_timers67_slotTime_dout;\n\nend\n\n\n% 'From FIFO' and 'To FIFO' blocks\n\n\n\n\n\nopCode = xl_concat(addrAck, RNWReg, bankAddr, linearAddr);\n\n% 'Shared Memory' blocks\n\n\n\n\n\n% 'din' ports of 'Shared Memory' blocks\n\n\n% 'we' ports of 'Shared Memory' blocks\n\n\n% 'addr' ports of 'Shared Memory' blocks\n\n\n% 're' ports of 'From FIFO' blocks\n\n\n% 'en' ports of 'To Register' blocks\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 0))\n    sm_timer0_slotCount_en = true;\nelse\n    sm_timer0_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 1))\n    sm_timer1_slotCount_en = true;\nelse\n    sm_timer1_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 2))\n    sm_timer2_slotCount_en = true;\nelse\n    sm_timer2_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 3))\n    sm_timer3_slotCount_en = true;\nelse\n    sm_timer3_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 4))\n    sm_timer4_slotCount_en = true;\nelse\n    sm_timer4_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 5))\n    sm_timer5_slotCount_en = true;\nelse\n    sm_timer5_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 6))\n    sm_timer6_slotCount_en = true;\nelse\n    sm_timer6_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 7))\n    sm_timer7_slotCount_en = true;\nelse\n    sm_timer7_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 8))\n    sm_timer_control_en = true;\nelse\n    sm_timer_control_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 9))\n    sm_timers01_slotTime_en = true;\nelse\n    sm_timers01_slotTime_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 10))\n    sm_timers23_slotTime_en = true;\nelse\n    sm_timers23_slotTime_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 11))\n    sm_timers45_slotTime_en = true;\nelse\n    sm_timers45_slotTime_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n                       xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 12))\n    sm_timers67_slotTime_en = true;\nelse\n    sm_timers67_slotTime_en = false;\nend\n\n\n% 'din' ports of 'To FIFO' blocks\n\n\n% 'we' ports of 'To FIFO' blocks\n\n\n% 'din' ports of 'To Register' blocks\nsm_timer0_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timer1_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timer2_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timer3_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timer4_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timer5_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timer6_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timer7_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timer_control_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timers01_slotTime_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timers23_slotTime_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timers45_slotTime_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\nsm_timers67_slotTime_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n                                 xlUnsigned, ...\n                                 0);\n\n\npersistent read_bank_out_reg; read_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nread_bank_out = read_bank_out_reg;\n\npersistent bankAddr_reg; bankAddr_reg = xl_state(0, bankAddr);\n\nif bankAddr_reg == 0\n    % Bank 0: Shared Memories\n    read_bank_out_reg = 0;\nelseif bankAddr_reg == 1\n    % Bank 1: From/To FIFOs\n    read_bank_out_reg =  0;\nelseif bankAddr_reg == 2\n    % Bank 2: From/To Registers\n    read_bank_out_reg = reg_bank_out;\nelseif bankAddr_reg == 3\n    % Bank 3: Configuration Registers\n    read_bank_out_reg = 0;\nend\n\nbankAddr_reg = bankAddr;\n"
	  suppress_output	  "1"
	  defparams		  "{}"
	  hide_port_list	  "{}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mcode"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "170,270,1,1,white,blue,0,56f4a8ff,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 ],[0 0 270 270 ],[0.77 0.82 0.91]);\npatch([40 12 52 12 40 85 97 109 157 119 83 57 97 57 83 119 157 109 97 85 40 ],[68 96 136 176 204 204 192 204 204 166 202 176 136 96 70 106 68 68 80 68 68 ],[0.98 0.96 0.92]);\nplot([0 170 170 0 0 ],[0 0 270 270 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'wrDBus');\ncolor('black');port_label('input',2,'bankAddr');\ncolor('black');port_label('input',3,'linearAddr');\ncolor('black');port_label('input',4,'RNWReg');\ncolor('black');port_label('input',5,'addrAck');\ncolor('black');port_label('input',6,'sm_timer_status');\ncolor('black');port_label('input',7,'sm_timer0_slotCount');\ncolor('black');port_label('input',8,'sm_timer1_slotCount');\ncolor('black');port_label('input',9,'sm_timer2_slotCount');\ncolor('black');port_label('input',10,'sm_timer3_slotCount');\ncolor('black');port_label('input',11,'sm_timer4_slotCount');\ncolor('black');port_label('input',12,'sm_timer5_slotCount');\ncolor('black');port_label('input',13,'sm_timer6_slotCount');\ncolor('black');port_label('input',14,'sm_timer7_slotCount');\ncolor('black');port_label('input',15,'sm_timer_control');\ncolor('black');port_label('input',16,'sm_timers01_slotTime');\ncolor('black');port_label('input',17,'sm_timers23_slotTime');\ncolor('black');port_label('input',18,'sm_timers45_slotTime');\ncolor('black');port_label('input',19,'sm_timers67_slotTime');\ncolor('black');port_label('output',1,'read_bank_out');\ncolor('black');port_label('output',2,'sm_timer0_slotCount_din');\ncolor('black');port_label('output',3,'sm_timer0_slotCount_en');\ncolor('black');port_label('output',4,'sm_timer1_slotCount_din');\ncolor('black');port_label('output',5,'sm_timer1_slotCount_en');\ncolor('black');port_label('output',6,'sm_timer2_slotCount_din');\ncolor('black');port_label('output',7,'sm_timer2_slotCount_en');\ncolor('black');port_label('output',8,'sm_timer3_slotCount_din');\ncolor('black');port_label('output',9,'sm_timer3_slotCount_en');\ncolor('black');port_label('output',10,'sm_timer4_slotCount_din');\ncolor('black');port_label('output',11,'sm_timer4_slotCount_en');\ncolor('black');port_label('output',12,'sm_timer5_slotCount_din');\ncolor('black');port_label('output',13,'sm_timer5_slotCount_en');\ncolor('black');port_label('output',14,'sm_timer6_slotCount_din');\ncolor('black');port_label('output',15,'sm_timer6_slotCount_en');\ncolor('black');port_label('output',16,'sm_timer7_slotCount_din');\ncolor('black');port_label('output',17,'sm_timer7_slotCount_en');\ncolor('black');port_label('output',18,'sm_timer_control_din');\ncolor('black');port_label('output',19,'sm_timer_control_en');\ncolor('black');port_label('output',20,'sm_timers01_slotTime_din');\ncolor('black');port_label('output',21,'sm_timers01_slotTime_en');\ncolor('black');port_label('output',22,'sm_timers23_slotTime_din');\ncolor('black');port_label('output',23,'sm_timers23_slotTime_en');\ncolor('black');port_label('output',24,'sm_timers45_slotTime_din');\ncolor('black');port_label('output',25,'sm_timers45_slotTime_en');\ncolor('black');port_label('output',26,'sm_timers67_slotTime_din');\ncolor('black');port_label('output',27,'sm_timers67_slotTime_en');\ncolor('black');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "rdData"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    2
	    Name		    "timer0_slotCount_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    3
	    Name		    "timer0_slotCount_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    4
	    Name		    "timer1_slotCount_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    5
	    Name		    "timer1_slotCount_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    6
	    Name		    "timer2_slotCount_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    7
	    Name		    "timer2_slotCount_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    8
	    Name		    "timer3_slotCount_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    9
	    Name		    "timer3_slotCount_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    10
	    Name		    "timer4_slotCount_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    11
	    Name		    "timer4_slotCount_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    12
	    Name		    "timer5_slotCount_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    13
	    Name		    "timer5_slotCount_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    14
	    Name		    "timer6_slotCount_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    15
	    Name		    "timer6_slotCount_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    16
	    Name		    "timer7_slotCount_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    17
	    Name		    "timer7_slotCount_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    18
	    Name		    "timer_control_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    19
	    Name		    "timer_control_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    20
	    Name		    "timers01_slotTime_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    21
	    Name		    "timers01_slotTime_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    22
	    Name		    "timers23_slotTime_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    23
	    Name		    "timers23_slotTime_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    24
	    Name		    "timers45_slotTime_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    25
	    Name		    "timers45_slotTime_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    26
	    Name		    "timers67_slotTime_din"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	  Port {
	    PortNumber		    27
	    Name		    "timers67_slotTime_en"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "sg_plb_addrpref"
	  Ports			  [1, 1]
	  Position		  [175, 855, 245, 875]
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	  arith_type		  "Unsigned"
	  n_bits		  "20"
	  bin_pt		  "0"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetSimulinkPeriod(gcb)"
	  dbl_ovrd		  "off"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  sginterface		  "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'sg_plb_addrpref'}},'iopad'=>{'constraint'=>'#'}}"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "70,20,1,1,white,yellow,0,bc55d28f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	  Port {
	    PortNumber		    1
	    Name		    "addrPref"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	  }
	}
	Line {
	  Name			  "Sl_addrAck"
	  SrcBlock		  "plb_decode"
	  SrcPort		  2
	  Points		  [0, 0]
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "plb_memmap"
	    DstPort		    5
	  }
	  Branch {
	    Labels		    [0, 0]
	    DstBlock		    "Sl_addrAck"
	    DstPort		    1
	  }
	}
	Line {
	  Name			  "Sl_wrDAck"
	  SrcBlock		  "plb_decode"
	  SrcPort		  4
	  Points		  [0, 0]
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "Sl_wrDAck"
	    DstPort		    1
	  }
	  Branch {
	    Labels		    [0, 0]
	    DstBlock		    "Sl_wrComp"
	    DstPort		    1
	  }
	}
	Line {
	  Name			  "timers67_slotTime_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  27
	  DstBlock		  "To Register12"
	  DstPort		  2
	}
	Line {
	  Name			  "timers67_slotTime_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  26
	  DstBlock		  "To Register12"
	  DstPort		  1
	}
	Line {
	  Name			  "timers45_slotTime_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  25
	  DstBlock		  "To Register11"
	  DstPort		  2
	}
	Line {
	  Name			  "timers45_slotTime_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  24
	  DstBlock		  "To Register11"
	  DstPort		  1
	}
	Line {
	  Name			  "timers23_slotTime_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  23
	  DstBlock		  "To Register10"
	  DstPort		  2
	}
	Line {
	  Name			  "timers23_slotTime_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  22
	  DstBlock		  "To Register10"
	  DstPort		  1
	}
	Line {
	  Name			  "timers01_slotTime_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  21
	  DstBlock		  "To Register9"
	  DstPort		  2
	}
	Line {
	  Name			  "timers01_slotTime_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  20
	  DstBlock		  "To Register9"
	  DstPort		  1
	}
	Line {
	  Name			  "timer_control_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  19
	  DstBlock		  "To Register8"
	  DstPort		  2
	}
	Line {
	  Name			  "timer_control_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  18
	  DstBlock		  "To Register8"
	  DstPort		  1
	}
	Line {
	  Name			  "timer7_slotCount_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  17
	  DstBlock		  "To Register7"
	  DstPort		  2
	}
	Line {
	  Name			  "timer7_slotCount_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  16
	  DstBlock		  "To Register7"
	  DstPort		  1
	}
	Line {
	  Name			  "timer6_slotCount_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  15
	  DstBlock		  "To Register6"
	  DstPort		  2
	}
	Line {
	  Name			  "timer6_slotCount_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  14
	  DstBlock		  "To Register6"
	  DstPort		  1
	}
	Line {
	  Name			  "timer5_slotCount_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  13
	  DstBlock		  "To Register5"
	  DstPort		  2
	}
	Line {
	  Name			  "timer5_slotCount_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  12
	  DstBlock		  "To Register5"
	  DstPort		  1
	}
	Line {
	  Name			  "timer4_slotCount_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  11
	  DstBlock		  "To Register4"
	  DstPort		  2
	}
	Line {
	  Name			  "timer4_slotCount_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  10
	  DstBlock		  "To Register4"
	  DstPort		  1
	}
	Line {
	  Name			  "timer3_slotCount_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  9
	  DstBlock		  "To Register3"
	  DstPort		  2
	}
	Line {
	  Name			  "timer3_slotCount_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  8
	  DstBlock		  "To Register3"
	  DstPort		  1
	}
	Line {
	  Name			  "timer2_slotCount_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  7
	  DstBlock		  "To Register2"
	  DstPort		  2
	}
	Line {
	  Name			  "timer2_slotCount_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  6
	  DstBlock		  "To Register2"
	  DstPort		  1
	}
	Line {
	  Name			  "timer1_slotCount_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  5
	  DstBlock		  "To Register1"
	  DstPort		  2
	}
	Line {
	  Name			  "timer1_slotCount_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  4
	  DstBlock		  "To Register1"
	  DstPort		  1
	}
	Line {
	  Name			  "timer0_slotCount_en"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  3
	  DstBlock		  "To Register"
	  DstPort		  2
	}
	Line {
	  Name			  "timer0_slotCount_din"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  2
	  DstBlock		  "To Register"
	  DstPort		  1
	}
	Line {
	  Name			  "rdData"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_memmap"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  6
	}
	Line {
	  Name			  "timers67_slotTime_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register12"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  19
	}
	Line {
	  Name			  "timers45_slotTime_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register11"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  18
	}
	Line {
	  Name			  "timers23_slotTime_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register10"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  17
	}
	Line {
	  Name			  "timers01_slotTime_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register9"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  16
	}
	Line {
	  Name			  "timer_control_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register8"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  15
	}
	Line {
	  Name			  "timer7_slotCount_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register7"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  14
	}
	Line {
	  Name			  "timer6_slotCount_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register6"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  13
	}
	Line {
	  Name			  "timer5_slotCount_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register5"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  12
	}
	Line {
	  Name			  "timer4_slotCount_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register4"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  11
	}
	Line {
	  Name			  "timer3_slotCount_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register3"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  10
	}
	Line {
	  Name			  "timer2_slotCount_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register2"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  9
	}
	Line {
	  Name			  "timer1_slotCount_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register1"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  8
	}
	Line {
	  Name			  "timer0_slotCount_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "To Register"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  7
	}
	Line {
	  Name			  "timer_status_dout"
	  Labels		  [0, 0]
	  SrcBlock		  "From Register"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  6
	}
	Line {
	  Name			  "RNWReg"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  6
	  DstBlock		  "plb_memmap"
	  DstPort		  4
	}
	Line {
	  Name			  "linearAddr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  9
	  DstBlock		  "plb_memmap"
	  DstPort		  3
	}
	Line {
	  Name			  "bankAddr"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  5
	  DstBlock		  "plb_memmap"
	  DstPort		  2
	}
	Line {
	  Name			  "wrDBusReg"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  1
	  DstBlock		  "plb_memmap"
	  DstPort		  1
	}
	Line {
	  Name			  "Sl_rdDBus"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  8
	  DstBlock		  "Sl_rdDBus"
	  DstPort		  1
	}
	Line {
	  Name			  "Sl_rdDAck"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  7
	  DstBlock		  "Sl_rdDAck"
	  DstPort		  1
	}
	Line {
	  Name			  "Sl_rdComp"
	  Labels		  [0, 0]
	  SrcBlock		  "plb_decode"
	  SrcPort		  3
	  DstBlock		  "Sl_rdComp"
	  DstPort		  1
	}
	Line {
	  Name			  "addrPref"
	  Labels		  [0, 0]
	  SrcBlock		  "sg_plb_addrpref"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  7
	}
	Line {
	  Name			  "PLB_wrDBus"
	  Labels		  [0, 0]
	  SrcBlock		  "PLB_wrDBus"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  5
	}
	Line {
	  Name			  "PLB_RNW"
	  Labels		  [0, 0]
	  SrcBlock		  "PLB_RNW"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  4
	}
	Line {
	  Name			  "PLB_PAValid"
	  Labels		  [0, 0]
	  SrcBlock		  "PLB_PAValid"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  3
	}
	Line {
	  Name			  "PLB_ABus"
	  Labels		  [0, 0]
	  SrcBlock		  "PLB_ABus"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  2
	}
	Line {
	  Name			  "SPLB_Rst"
	  Labels		  [0, 0]
	  SrcBlock		  "SPLB_Rst"
	  SrcPort		  1
	  DstBlock		  "plb_decode"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant6"
	  SrcPort		  1
	  DstBlock		  "sg_plb_addrpref"
	  DstPort		  1
	}
	Line {
	  Name			  "Sl_wait"
	  Labels		  [0, 0]
	  SrcBlock		  "Constant5"
	  SrcPort		  1
	  DstBlock		  "Sl_wait"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "PLB_wrDBus"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant3"
	  SrcPort		  1
	  DstBlock		  "PLB_RNW"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "PLB_PAValid"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "PLB_ABus"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "SPLB_Rst"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_wrComp"
	  SrcPort		  1
	  DstBlock		  "Terminator6"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_wrDAck"
	  SrcPort		  1
	  DstBlock		  "Terminator5"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_wait"
	  SrcPort		  1
	  DstBlock		  "Terminator4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_rdDBus"
	  SrcPort		  1
	  DstBlock		  "Terminator3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_rdDAck"
	  SrcPort		  1
	  DstBlock		  "Terminator2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_rdComp"
	  SrcPort		  1
	  DstBlock		  "Terminator1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sl_addrAck"
	  SrcPort		  1
	  DstBlock		  "Terminator"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      From
      Name		      "From"
      Position		      [150, 131, 265, 149]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer0_doneReset"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From1"
      Position		      [150, 116, 265, 134]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer0_mode"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From10"
      Position		      [150, 281, 265, 299]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer1_slotCount"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From11"
      Position		      [150, 296, 265, 314]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer1_slotTime"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From12"
      Position		      [150, 416, 265, 434]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer2_slotCount"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From13"
      Position		      [150, 431, 265, 449]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer2_slotTime"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From14"
      Position		      [150, 401, 265, 419]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer2_doneReset"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From15"
      Position		      [150, 386, 265, 404]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer2_mode"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From16"
      Position		      [150, 371, 265, 389]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer2_pause"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From17"
      Position		      [150, 356, 265, 374]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer2_start"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From18"
      Position		      [150, 556, 265, 574]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer3_slotCount"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From19"
      Position		      [150, 571, 265, 589]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer3_slotTime"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From2"
      Position		      [150, 101, 265, 119]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer0_pause"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From20"
      Position		      [150, 541, 265, 559]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer3_doneReset"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From21"
      Position		      [150, 526, 265, 544]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer3_mode"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From22"
      Position		      [150, 511, 265, 529]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer3_pause"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From23"
      Position		      [150, 496, 265, 514]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer3_start"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From24"
      Position		      [665, 121, 780, 139]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer4_doneReset"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From25"
      Position		      [665, 106, 780, 124]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer4_mode"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From26"
      Position		      [665, 271, 780, 289]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer5_slotCount"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From27"
      Position		      [665, 286, 780, 304]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer5_slotTime"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From28"
      Position		      [665, 406, 780, 424]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer6_slotCount"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From29"
      Position		      [665, 421, 780, 439]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer6_slotTime"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From3"
      Position		      [150, 86, 265, 104]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer0_start"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From30"
      Position		      [665, 391, 780, 409]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer6_doneReset"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From31"
      Position		      [665, 376, 780, 394]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer6_mode"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From32"
      Position		      [665, 361, 780, 379]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer6_pause"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From33"
      Position		      [665, 346, 780, 364]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer6_start"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From34"
      Position		      [665, 546, 780, 564]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer7_slotCount"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From35"
      Position		      [665, 561, 780, 579]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer7_slotTime"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From36"
      Position		      [665, 91, 780, 109]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer4_pause"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From37"
      Position		      [665, 531, 780, 549]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer7_doneReset"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From38"
      Position		      [665, 516, 780, 534]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer7_mode"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From39"
      Position		      [665, 501, 780, 519]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer7_pause"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From4"
      Position		      [150, 146, 265, 164]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer0_slotCount"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From40"
      Position		      [665, 486, 780, 504]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer7_start"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From41"
      Position		      [665, 76, 780, 94]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer4_start"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From42"
      Position		      [665, 136, 780, 154]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer4_slotCount"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From43"
      Position		      [665, 151, 780, 169]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer4_slotTime"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From44"
      Position		      [665, 256, 780, 274]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer5_doneReset"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From45"
      Position		      [665, 241, 780, 259]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer5_mode"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From46"
      Position		      [665, 226, 780, 244]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer5_pause"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From47"
      Position		      [665, 211, 780, 229]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer5_start"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From5"
      Position		      [150, 161, 265, 179]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer0_slotTime"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From6"
      Position		      [150, 266, 265, 284]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer1_doneReset"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From7"
      Position		      [150, 251, 265, 269]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer1_mode"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From8"
      Position		      [150, 236, 265, 254]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer1_pause"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From9"
      Position		      [150, 221, 265, 239]
      ShowName		      off
      CloseFcn		      "tagdialog Close"
      GotoTag		      "timer1_start"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      Reference
      Name		      "IDLEFORDIFS"
      Ports		      [1, 1]
      Position		      [70, 177, 135, 193]
      SourceBlock	      "xbsIndex_r4/Gateway In"
      SourceType	      "Xilinx Gateway In Block"
      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
      arith_type	      "Unsigned"
      n_bits		      "1"
      bin_pt		      "0"
      quantization	      "Round  (unbiased: +/- Inf)"
      overflow		      "Saturate"
      period		      "1"
      dbl_ovrd		      off
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "20,20,356,432"
      block_type	      "gatewayin"
      block_version	      "8.2"
      sg_icon_stat	      "65,16,1,1,white,yellow,0,bc55d28f,right"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
    }
    Block {
      BlockType		      SubSystem
      Name		      "Registers"
      Ports		      []
      Position		      [585, 687, 636, 737]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Registers"
	Location		[1101, 654, 1279, 882]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Reference
	  Name			  "16LSB"
	  Ports			  [1, 1]
	  Position		  [580, 254, 605, 266]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "16"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "0"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "16LSB1"
	  Ports			  [1, 1]
	  Position		  [580, 319, 605, 331]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "16"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "0"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "16LSB2"
	  Ports			  [1, 1]
	  Position		  [580, 384, 605, 396]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "16"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "0"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "16LSB3"
	  Ports			  [1, 1]
	  Position		  [580, 449, 605, 461]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "16"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "0"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "16MSB"
	  Ports			  [1, 1]
	  Position		  [580, 269, 605, 281]
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "16"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "16"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "16MSB1"
	  Ports			  [1, 1]
	  Position		  [580, 334, 605, 346]
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "16"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "16"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "16MSB2"
	  Ports			  [1, 1]
	  Position		  [580, 399, 605, 411]
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "16"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "16"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "16MSB3"
	  Ports			  [1, 1]
	  Position		  [580, 464, 605, 476]
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "16"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "16"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant5"
	  Ports			  [0, 1]
	  Position		  [560, 600, 595, 620]
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Boolean"
	  const			  "1"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  "off"
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,400,346"
	  block_type		  "constant"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,20,1,1,white,blue,0,06094819,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register1"
	  Ports			  [0, 1]
	  Position		  [120, 302, 145, 328]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer1_slotCount'"
	  init			  "500"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register11"
	  Ports			  [0, 1]
	  Position		  [455, 262, 480, 288]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timers01_slotTime'"
	  init			  "0"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register12"
	  Ports			  [0, 1]
	  Position		  [455, 327, 480, 353]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timers23_slotTime'"
	  init			  "0"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register13"
	  Ports			  [0, 1]
	  Position		  [455, 392, 480, 418]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timers45_slotTime'"
	  init			  "0"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register14"
	  Ports			  [0, 1]
	  Position		  [455, 457, 480, 483]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timers67_slotTime'"
	  init			  "0"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register2"
	  Ports			  [0, 1]
	  Position		  [120, 427, 145, 453]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer3_slotCount'"
	  init			  "500"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register3"
	  Ports			  [0, 1]
	  Position		  [120, 362, 145, 388]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer2_slotCount'"
	  init			  "500"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register4"
	  Ports			  [0, 1]
	  Position		  [120, 557, 145, 583]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer5_slotCount'"
	  init			  "500"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register5"
	  Ports			  [0, 1]
	  Position		  [120, 682, 145, 708]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer7_slotCount'"
	  init			  "500"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register6"
	  Ports			  [0, 1]
	  Position		  [120, 617, 145, 643]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer6_slotCount'"
	  init			  "500"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register7"
	  Ports			  [0, 1]
	  Position		  [120, 492, 145, 518]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer4_slotCount'"
	  init			  "500"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register8"
	  Ports			  [0, 1]
	  Position		  [365, 132, 390, 158]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer_control'"
	  init			  "0"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "412,24,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register9"
	  Ports			  [0, 1]
	  Position		  [120, 237, 145, 263]
	  ShowName		  off
	  AttributesFormatString  "From Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer0_slotCount'"
	  init			  "500"
	  period		  "1"
	  ownership		  "Locally owned and initialized"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "514,418,383,246"
	  block_type		  "fromreg"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,26,0,1,white,blue,0,4b212927,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  From
	  Name			  "From40"
	  Position		  [455, 576, 570, 594]
	  ShowName		  off
	  CloseFcn		  "tagdialog Close"
	  GotoTag		  "timers_status"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto"
	  Position		  [200, 241, 335, 259]
	  ShowName		  off
	  GotoTag		  "timer0_slotCount"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto1"
	  Position		  [200, 306, 335, 324]
	  ShowName		  off
	  GotoTag		  "timer1_slotCount"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto10"
	  Position		  [670, 316, 805, 334]
	  ShowName		  off
	  GotoTag		  "timer2_slotTime"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto11"
	  Position		  [670, 331, 805, 349]
	  ShowName		  off
	  GotoTag		  "timer3_slotTime"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto12"
	  Position		  [670, 381, 805, 399]
	  ShowName		  off
	  GotoTag		  "timer4_slotTime"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto13"
	  Position		  [670, 396, 805, 414]
	  ShowName		  off
	  GotoTag		  "timer5_slotTime"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto14"
	  Position		  [670, 446, 805, 464]
	  ShowName		  off
	  GotoTag		  "timer6_slotTime"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto15"
	  Position		  [670, 461, 805, 479]
	  ShowName		  off
	  GotoTag		  "timer7_slotTime"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto2"
	  Position		  [200, 366, 335, 384]
	  ShowName		  off
	  GotoTag		  "timer2_slotCount"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto3"
	  Position		  [200, 431, 335, 449]
	  ShowName		  off
	  GotoTag		  "timer3_slotCount"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto4"
	  Position		  [200, 496, 335, 514]
	  ShowName		  off
	  GotoTag		  "timer4_slotCount"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto5"
	  Position		  [200, 561, 335, 579]
	  ShowName		  off
	  GotoTag		  "timer5_slotCount"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto6"
	  Position		  [200, 621, 335, 639]
	  ShowName		  off
	  GotoTag		  "timer6_slotCount"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto7"
	  Position		  [200, 686, 335, 704]
	  ShowName		  off
	  GotoTag		  "timer7_slotCount"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto8"
	  Position		  [670, 251, 805, 269]
	  ShowName		  off
	  GotoTag		  "timer0_slotTime"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto9"
	  Position		  [670, 266, 805, 284]
	  ShowName		  off
	  GotoTag		  "timer1_slotTime"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Slices & Gotos"
	  Ports			  [1]
	  Position		  [445, 134, 500, 156]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Slices & Gotos"
	    Location		    [494, 176, 924, 786]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "32b"
	      Position		      [25, 28, 55, 42]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "4LSB"
	      Ports		      [1, 1]
	      Position		      [115, 29, 140, 41]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "4"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "4LSB+12"
	      Ports		      [1, 1]
	      Position		      [115, 244, 140, 256]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "4"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "12"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "4LSB+16"
	      Ports		      [1, 1]
	      Position		      [115, 314, 140, 326]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "4"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "16"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "4LSB+20"
	      Ports		      [1, 1]
	      Position		      [115, 384, 140, 396]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "4"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "20"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "4LSB+24"
	      Ports		      [1, 1]
	      Position		      [115, 454, 140, 466]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "4"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "24"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "4LSB+28"
	      Ports		      [1, 1]
	      Position		      [115, 524, 140, 536]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "4"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "28"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "4LSB+4"
	      Ports		      [1, 1]
	      Position		      [115, 99, 140, 111]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "4"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "4"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "4LSB+8"
	      Ports		      [1, 1]
	      Position		      [115, 174, 140, 186]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "4"
	      boolean_output	      "off"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "8"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto"
	      Position		      [270, 26, 405, 44]
	      ShowName		      off
	      GotoTag		      "timer0_start"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto1"
	      Position		      [270, 41, 405, 59]
	      ShowName		      off
	      GotoTag		      "timer0_pause"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto10"
	      Position		      [270, 202, 405, 218]
	      ShowName		      off
	      GotoTag		      "timer2_mode"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto11"
	      Position		      [270, 216, 405, 234]
	      ShowName		      off
	      GotoTag		      "timer2_doneReset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto12"
	      Position		      [270, 272, 405, 288]
	      ShowName		      off
	      GotoTag		      "timer3_mode"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto13"
	      Position		      [270, 286, 405, 304]
	      ShowName		      off
	      GotoTag		      "timer3_doneReset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto14"
	      Position		      [270, 241, 405, 259]
	      ShowName		      off
	      GotoTag		      "timer3_start"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto15"
	      Position		      [270, 256, 405, 274]
	      ShowName		      off
	      GotoTag		      "timer3_pause"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto16"
	      Position		      [270, 311, 405, 329]
	      ShowName		      off
	      GotoTag		      "timer4_start"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto17"
	      Position		      [270, 326, 405, 344]
	      ShowName		      off
	      GotoTag		      "timer4_pause"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto18"
	      Position		      [270, 482, 405, 498]
	      ShowName		      off
	      GotoTag		      "timer6_mode"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto19"
	      Position		      [270, 496, 405, 514]
	      ShowName		      off
	      GotoTag		      "timer6_doneReset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto2"
	      Position		      [270, 57, 405, 73]
	      ShowName		      off
	      GotoTag		      "timer0_mode"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto20"
	      Position		      [270, 552, 405, 568]
	      ShowName		      off
	      GotoTag		      "timer7_mode"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto21"
	      Position		      [270, 566, 405, 584]
	      ShowName		      off
	      GotoTag		      "timer7_doneReset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto22"
	      Position		      [270, 521, 405, 539]
	      ShowName		      off
	      GotoTag		      "timer7_start"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto23"
	      Position		      [270, 536, 405, 554]
	      ShowName		      off
	      GotoTag		      "timer7_pause"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto24"
	      Position		      [270, 342, 405, 358]
	      ShowName		      off
	      GotoTag		      "timer4_mode"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto25"
	      Position		      [270, 356, 405, 374]
	      ShowName		      off
	      GotoTag		      "timer4_doneReset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto26"
	      Position		      [270, 381, 405, 399]
	      ShowName		      off
	      GotoTag		      "timer5_start"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto27"
	      Position		      [270, 396, 405, 414]
	      ShowName		      off
	      GotoTag		      "timer5_pause"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto28"
	      Position		      [270, 412, 405, 428]
	      ShowName		      off
	      GotoTag		      "timer5_mode"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto29"
	      Position		      [270, 426, 405, 444]
	      ShowName		      off
	      GotoTag		      "timer5_doneReset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto3"
	      Position		      [270, 71, 405, 89]
	      ShowName		      off
	      GotoTag		      "timer0_doneReset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto30"
	      Position		      [270, 451, 405, 469]
	      ShowName		      off
	      GotoTag		      "timer6_start"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto31"
	      Position		      [270, 466, 405, 484]
	      ShowName		      off
	      GotoTag		      "timer6_pause"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto4"
	      Position		      [270, 96, 405, 114]
	      ShowName		      off
	      GotoTag		      "timer1_start"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto5"
	      Position		      [270, 111, 405, 129]
	      ShowName		      off
	      GotoTag		      "timer1_pause"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto6"
	      Position		      [270, 127, 405, 143]
	      ShowName		      off
	      GotoTag		      "timer1_mode"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto7"
	      Position		      [270, 141, 405, 159]
	      ShowName		      off
	      GotoTag		      "timer1_doneReset"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto8"
	      Position		      [270, 171, 405, 189]
	      ShowName		      off
	      GotoTag		      "timer2_start"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto9"
	      Position		      [270, 186, 405, 204]
	      ShowName		      off
	      GotoTag		      "timer2_pause"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice"
	      Ports		      [1, 1]
	      Position		      [190, 29, 215, 41]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice1"
	      Ports		      [1, 1]
	      Position		      [190, 59, 215, 71]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "2"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice10"
	      Ports		      [1, 1]
	      Position		      [190, 219, 215, 231]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "3"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice11"
	      Ports		      [1, 1]
	      Position		      [190, 244, 215, 256]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice12"
	      Ports		      [1, 1]
	      Position		      [190, 274, 215, 286]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "2"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice13"
	      Ports		      [1, 1]
	      Position		      [190, 289, 215, 301]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "3"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice14"
	      Ports		      [1, 1]
	      Position		      [190, 189, 215, 201]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice15"
	      Ports		      [1, 1]
	      Position		      [190, 259, 215, 271]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice16"
	      Ports		      [1, 1]
	      Position		      [190, 314, 215, 326]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice17"
	      Ports		      [1, 1]
	      Position		      [190, 344, 215, 356]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "2"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice18"
	      Ports		      [1, 1]
	      Position		      [190, 499, 215, 511]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "3"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice19"
	      Ports		      [1, 1]
	      Position		      [190, 524, 215, 536]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice2"
	      Ports		      [1, 1]
	      Position		      [190, 74, 215, 86]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "3"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice20"
	      Ports		      [1, 1]
	      Position		      [190, 554, 215, 566]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "2"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice21"
	      Ports		      [1, 1]
	      Position		      [190, 569, 215, 581]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "3"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice22"
	      Ports		      [1, 1]
	      Position		      [190, 469, 215, 481]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice23"
	      Ports		      [1, 1]
	      Position		      [190, 539, 215, 551]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice24"
	      Ports		      [1, 1]
	      Position		      [190, 359, 215, 371]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "3"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice25"
	      Ports		      [1, 1]
	      Position		      [190, 384, 215, 396]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice26"
	      Ports		      [1, 1]
	      Position		      [190, 414, 215, 426]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "2"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice27"
	      Ports		      [1, 1]
	      Position		      [190, 429, 215, 441]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "3"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice28"
	      Ports		      [1, 1]
	      Position		      [190, 329, 215, 341]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice29"
	      Ports		      [1, 1]
	      Position		      [190, 399, 215, 411]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice3"
	      Ports		      [1, 1]
	      Position		      [190, 99, 215, 111]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice30"
	      Ports		      [1, 1]
	      Position		      [190, 454, 215, 466]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice31"
	      Ports		      [1, 1]
	      Position		      [190, 484, 215, 496]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "2"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice4"
	      Ports		      [1, 1]
	      Position		      [190, 129, 215, 141]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "2"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice5"
	      Ports		      [1, 1]
	      Position		      [190, 144, 215, 156]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "3"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice6"
	      Ports		      [1, 1]
	      Position		      [190, 44, 215, 56]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice7"
	      Ports		      [1, 1]
	      Position		      [190, 114, 215, 126]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice8"
	      Ports		      [1, 1]
	      Position		      [190, 174, 215, 186]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Slice9"
	      Ports		      [1, 1]
	      Position		      [190, 204, 215, 216]
	      ShowName		      off
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      "on"
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "LSB of Input"
	      bit0		      "2"
	      base0		      "LSB of Input"
	      dbl_ovrd		      "off"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,407"
	      block_type	      "slice"
	      block_version	      "9.1.01"
	      sg_icon_stat	      "25,12,1,1,white,blue,0,b1026674,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Line {
	      SrcBlock		      "32b"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		Points			[0, 70]
		Branch {
		  Points		  [0, 75]
		  Branch {
		    Points		    [0, 70]
		    Branch {
		    Points		    [0, 70]
		    Branch {
		    Points		    [0, 70]
		    Branch {
		    Points		    [0, 70]
		    Branch {
		    Points		    [0, 70]
		    DstBlock		    "4LSB+28"
		    DstPort		    1
		    }
		    Branch {
		    DstBlock		    "4LSB+24"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "4LSB+20"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "4LSB+16"
		    DstPort		    1
		    }
		    }
		    Branch {
		    DstBlock		    "4LSB+12"
		    DstPort		    1
		    }
		  }
		  Branch {
		    DstBlock		    "4LSB+8"
		    DstPort		    1
		  }
		}
		Branch {
		  DstBlock		  "4LSB+4"
		  DstPort		  1
		}
	      }
	      Branch {
		DstBlock		"4LSB"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "4LSB"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		DstBlock		"Slice"
		DstPort			1
	      }
	      Branch {
		Points			[0, 15]
		Branch {
		  DstBlock		  "Slice6"
		  DstPort		  1
		}
		Branch {
		  Points		  [0, 15]
		  Branch {
		    Points		    [0, 15]
		    DstBlock		    "Slice2"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "Slice1"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Line {
	      SrcBlock		      "4LSB+4"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		Points			[0, 15]
		Branch {
		  Points		  [0, 15]
		  Branch {
		    DstBlock		    "Slice4"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 15]
		    DstBlock		    "Slice5"
		    DstPort		    1
		  }
		}
		Branch {
		  DstBlock		  "Slice7"
		  DstPort		  1
		}
	      }
	      Branch {
		DstBlock		"Slice3"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Slice"
	      SrcPort		      1
	      DstBlock		      "Goto"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice6"
	      SrcPort		      1
	      DstBlock		      "Goto1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice1"
	      SrcPort		      1
	      DstBlock		      "Goto2"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice2"
	      SrcPort		      1
	      DstBlock		      "Goto3"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice3"
	      SrcPort		      1
	      DstBlock		      "Goto4"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice7"
	      SrcPort		      1
	      DstBlock		      "Goto5"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice4"
	      SrcPort		      1
	      DstBlock		      "Goto6"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice5"
	      SrcPort		      1
	      DstBlock		      "Goto7"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "4LSB+8"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		Points			[0, 15]
		Branch {
		  Points		  [0, 15]
		  Branch {
		    DstBlock		    "Slice9"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 15]
		    DstBlock		    "Slice10"
		    DstPort		    1
		  }
		}
		Branch {
		  DstBlock		  "Slice14"
		  DstPort		  1
		}
	      }
	      Branch {
		DstBlock		"Slice8"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "4LSB+12"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		DstBlock		"Slice11"
		DstPort			1
	      }
	      Branch {
		Points			[0, 15]
		Branch {
		  DstBlock		  "Slice15"
		  DstPort		  1
		}
		Branch {
		  Points		  [0, 15]
		  Branch {
		    Points		    [0, 15]
		    DstBlock		    "Slice13"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "Slice12"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Line {
	      SrcBlock		      "Slice8"
	      SrcPort		      1
	      DstBlock		      "Goto8"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice14"
	      SrcPort		      1
	      DstBlock		      "Goto9"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice9"
	      SrcPort		      1
	      DstBlock		      "Goto10"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice10"
	      SrcPort		      1
	      DstBlock		      "Goto11"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice11"
	      SrcPort		      1
	      DstBlock		      "Goto14"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice15"
	      SrcPort		      1
	      DstBlock		      "Goto15"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice12"
	      SrcPort		      1
	      DstBlock		      "Goto12"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice13"
	      SrcPort		      1
	      DstBlock		      "Goto13"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "4LSB+16"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		Points			[0, 15]
		Branch {
		  Points		  [0, 15]
		  Branch {
		    DstBlock		    "Slice17"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 15]
		    DstBlock		    "Slice24"
		    DstPort		    1
		  }
		}
		Branch {
		  DstBlock		  "Slice28"
		  DstPort		  1
		}
	      }
	      Branch {
		DstBlock		"Slice16"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "4LSB+20"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		DstBlock		"Slice25"
		DstPort			1
	      }
	      Branch {
		Points			[0, 15]
		Branch {
		  DstBlock		  "Slice29"
		  DstPort		  1
		}
		Branch {
		  Points		  [0, 15]
		  Branch {
		    Points		    [0, 15]
		    DstBlock		    "Slice27"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "Slice26"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Line {
	      SrcBlock		      "Slice16"
	      SrcPort		      1
	      DstBlock		      "Goto16"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice28"
	      SrcPort		      1
	      DstBlock		      "Goto17"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice17"
	      SrcPort		      1
	      DstBlock		      "Goto24"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice24"
	      SrcPort		      1
	      DstBlock		      "Goto25"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice25"
	      SrcPort		      1
	      DstBlock		      "Goto26"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice29"
	      SrcPort		      1
	      DstBlock		      "Goto27"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice26"
	      SrcPort		      1
	      DstBlock		      "Goto28"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice27"
	      SrcPort		      1
	      DstBlock		      "Goto29"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "4LSB+24"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		DstBlock		"Slice30"
		DstPort			1
	      }
	      Branch {
		Points			[0, 15]
		Branch {
		  DstBlock		  "Slice22"
		  DstPort		  1
		}
		Branch {
		  Points		  [0, 15]
		  Branch {
		    Points		    [0, 15]
		    DstBlock		    "Slice18"
		    DstPort		    1
		  }
		  Branch {
		    DstBlock		    "Slice31"
		    DstPort		    1
		  }
		}
	      }
	    }
	    Line {
	      SrcBlock		      "4LSB+28"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		Points			[0, 15]
		Branch {
		  Points		  [0, 15]
		  Branch {
		    DstBlock		    "Slice20"
		    DstPort		    1
		  }
		  Branch {
		    Points		    [0, 15]
		    DstBlock		    "Slice21"
		    DstPort		    1
		  }
		}
		Branch {
		  DstBlock		  "Slice23"
		  DstPort		  1
		}
	      }
	      Branch {
		DstBlock		"Slice19"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Slice30"
	      SrcPort		      1
	      DstBlock		      "Goto30"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice22"
	      SrcPort		      1
	      DstBlock		      "Goto31"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice31"
	      SrcPort		      1
	      DstBlock		      "Goto18"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice18"
	      SrcPort		      1
	      DstBlock		      "Goto19"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice19"
	      SrcPort		      1
	      DstBlock		      "Goto22"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice23"
	      SrcPort		      1
	      DstBlock		      "Goto23"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice20"
	      SrcPort		      1
	      DstBlock		      "Goto20"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Slice21"
	      SrcPort		      1
	      DstBlock		      "Goto21"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register4"
	  Ports			  [2, 1]
	  Position		  [615, 571, 670, 624]
	  ShowName		  off
	  AttributesFormatString  "To Register\\n<< %<shared_memory_name> >>"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'timer_status'"
	  init			  "0"
	  ownership		  "Locally owned and initialized"
	  explicit_data_type	  on
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "290,195,381,270"
	  block_type		  "toreg"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "55,53,2,1,white,blue,0,77cabcdf,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n"
	}
	Line {
	  Labels		  [0, 0]
	  SrcBlock		  "From Register8"
	  SrcPort		  1
	  DstBlock		  "Slices & Gotos"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register9"
	  SrcPort		  1
	  DstBlock		  "Goto"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register5"
	  SrcPort		  1
	  DstBlock		  "Goto7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register6"
	  SrcPort		  1
	  DstBlock		  "Goto6"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register4"
	  SrcPort		  1
	  DstBlock		  "Goto5"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register7"
	  SrcPort		  1
	  DstBlock		  "Goto4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register2"
	  SrcPort		  1
	  DstBlock		  "Goto3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register3"
	  SrcPort		  1
	  DstBlock		  "Goto2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register1"
	  SrcPort		  1
	  DstBlock		  "Goto1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register11"
	  SrcPort		  1
	  Points		  [55, 0]
	  Branch {
	    DstBlock		    "16MSB"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, -15]
	    DstBlock		    "16LSB"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "16LSB"
	  SrcPort		  1
	  DstBlock		  "Goto8"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "16MSB"
	  SrcPort		  1
	  DstBlock		  "Goto9"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "16LSB1"
	  SrcPort		  1
	  DstBlock		  "Goto10"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "16MSB1"
	  SrcPort		  1
	  DstBlock		  "Goto11"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "16LSB2"
	  SrcPort		  1
	  DstBlock		  "Goto12"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "16MSB2"
	  SrcPort		  1
	  DstBlock		  "Goto13"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "16LSB3"
	  SrcPort		  1
	  DstBlock		  "Goto14"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "16MSB3"
	  SrcPort		  1
	  DstBlock		  "Goto15"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register12"
	  SrcPort		  1
	  Points		  [55, 0]
	  Branch {
	    Points		    [0, -15]
	    DstBlock		    "16LSB1"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "16MSB1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "From Register13"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    Points		    [0, -15]
	    DstBlock		    "16LSB2"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "16MSB2"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "From Register14"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    Points		    [0, -15]
	    DstBlock		    "16LSB3"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "16MSB3"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Constant5"
	  SrcPort		  1
	  DstBlock		  "To Register4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "From40"
	  SrcPort		  1
	  DstBlock		  "To Register4"
	  DstPort		  1
	}
	Annotation {
	  Name			  "Slot Count Registers\n(1 per timer)"
	  Position		  [147, 210]
	}
	Annotation {
	  Name			  "Timer Control Register\n(1 shared by all timers)"
	  Position		  [397, 105]
	}
	Annotation {
	  Name			  "Timer Slot Time Register\n(2 timers share each register)"
	  Position		  [592, 210]
	}
	Annotation {
	  Name			  "Timer Status Register\n(1 shared by all timers)"
	  Position		  [597, 545]
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Status\nOutputs"
      Ports		      [8]
      Position		      [1215, 257, 1250, 343]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Status\nOutputs"
	Location		[1449, 133, 1639, 374]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "T0"
	  Position		  [265, 313, 295, 327]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "T1"
	  Position		  [265, 288, 295, 302]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "T2"
	  Position		  [265, 263, 295, 277]
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "T3"
	  Position		  [265, 238, 295, 252]
	  Port			  "4"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "T4"
	  Position		  [265, 213, 295, 227]
	  Port			  "5"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "T5"
	  Position		  [265, 188, 295, 202]
	  Port			  "6"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "T6"
	  Position		  [265, 163, 295, 177]
	  Port			  "7"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "T7"
	  Position		  [265, 138, 295, 152]
	  Port			  "8"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Concat13"
	  Ports			  [8, 1]
	  Position		  [390, 140, 420, 325]
	  SourceBlock		  "xbsIndex_r4/Concat"
	  SourceType		  "Xilinx Bus Concatenator Block"
	  infoedit		  "Concatenates two or more inputs.  Output will be cast to an unsigned value with the binary point at zero."
	  num_inputs		  "8"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,165"
	  block_type		  "concat"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,185,1,1,white,blue,0,7ccc19ac,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 185 185 ],[0.77 0.82 0.91]);\npatch([7 2 9 2 7 15 17 19 27 20 14 9 15 9 14 20 27 19 17 15 7 ],[81 86 93 100 105 105 103 105 105 98 104 99 93 87 82 88 81 81 83 81 81 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 185 185 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',8,'lo');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Goto
	  Name			  "Goto"
	  Position		  [535, 226, 670, 244]
	  ShowName		  off
	  GotoTag		  "timers_status"
	  TagVisibility		  "global"
	}
	Block {
	  BlockType		  Reference
	  Name			  "LSB+1"
	  Ports			  [1, 1]
	  Position		  [415, 409, 440, 421]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "1"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "1"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "LSB+2"
	  Ports			  [1, 1]
	  Position		  [415, 379, 440, 391]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "1"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "1"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "LSB+3"
	  Ports			  [1, 1]
	  Position		  [415, 439, 440, 451]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "1"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "1"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "LSB+4"
	  Ports			  [1, 1]
	  Position		  [415, 499, 440, 511]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "1"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "1"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "LSB+5"
	  Ports			  [1, 1]
	  Position		  [415, 469, 440, 481]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "1"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "1"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "LSB+6"
	  Ports			  [1, 1]
	  Position		  [415, 529, 440, 541]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "1"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "1"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "LSB+7"
	  Ports			  [1, 1]
	  Position		  [415, 559, 440, 571]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "1"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "1"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "LSB+8"
	  Ports			  [1, 1]
	  Position		  [415, 589, 440, 601]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
	  nbits			  "1"
	  boolean_output	  "off"
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "LSB of Input"
	  bit0			  "1"
	  base0			  "LSB of Input"
	  dbl_ovrd		  "off"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,407"
	  block_type		  "slice"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "25,12,1,1,white,blue,0,b1026674,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical"
	  Ports			  [8, 1]
	  Position		  [500, 629, 535, 711]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "8"
	  en			  "off"
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  "on"
	  dbl_ovrd		  "off"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "35,82,1,1,white,blue,0,84119f55,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "TIMEREXPIRE"
	  Ports			  [1, 1]
	  Position		  [575, 660, 635, 680]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,352"
	  block_type		  "gatewayout"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,20,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "timer0_active"
	  Ports			  [1, 1]
	  Position		  [515, 378, 575, 392]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "60,14,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([26 24 27 24 26 30 31 32 36 33 30 28 31 28 30 33 36 32 31 30 26 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "timer1_active"
	  Ports			  [1, 1]
	  Position		  [515, 408, 575, 422]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "60,14,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([26 24 27 24 26 30 31 32 36 33 30 28 31 28 30 33 36 32 31 30 26 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "timer2_active"
	  Ports			  [1, 1]
	  Position		  [515, 438, 575, 452]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "60,14,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([26 24 27 24 26 30 31 32 36 33 30 28 31 28 30 33 36 32 31 30 26 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "timer3_active"
	  Ports			  [1, 1]
	  Position		  [515, 468, 575, 482]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "60,14,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([26 24 27 24 26 30 31 32 36 33 30 28 31 28 30 33 36 32 31 30 26 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "timer4_active"
	  Ports			  [1, 1]
	  Position		  [515, 498, 575, 512]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "60,14,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([26 24 27 24 26 30 31 32 36 33 30 28 31 28 30 33 36 32 31 30 26 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "timer5_active"
	  Ports			  [1, 1]
	  Position		  [515, 528, 575, 542]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "60,14,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([26 24 27 24 26 30 31 32 36 33 30 28 31 28 30 33 36 32 31 30 26 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "timer6_active"
	  Ports			  [1, 1]
	  Position		  [515, 558, 575, 572]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "60,14,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([26 24 27 24 26 30 31 32 36 33 30 28 31 28 30 33 36 32 31 30 26 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "timer7_active"
	  Ports			  [1, 1]
	  Position		  [515, 588, 575, 602]
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Hardware notes:  In hardware these blocks become top level output ports or are discarded, depending on how they are configured."
	  hdl_port		  "on"
	  timing_constraint	  "None"
	  locs_specified	  "off"
	  LOCs			  "{}"
	  xl_use_area		  "off"
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "60,14,1,1,white,yellow,0,38220381,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([26 24 27 24 26 30 31 32 36 33 30 28 31 28 30 33 36 32 31 30 26 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Line {
	  SrcBlock		  "T7"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    DstBlock		    "Concat13"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 450]
	    DstBlock		    "LSB+8"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "T6"
	  SrcPort		  1
	  Points		  [40, 0]
	  Branch {
	    DstBlock		    "Concat13"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 395]
	    DstBlock		    "LSB+7"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "T5"
	  SrcPort		  1
	  Points		  [45, 0]
	  Branch {
	    DstBlock		    "Concat13"
	    DstPort		    3
	  }
	  Branch {
	    Points		    [0, 340]
	    DstBlock		    "LSB+6"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "T4"
	  SrcPort		  1
	  Points		  [50, 0]
	  Branch {
	    DstBlock		    "Concat13"
	    DstPort		    4
	  }
	  Branch {
	    Points		    [0, 285]
	    DstBlock		    "LSB+4"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "T3"
	  SrcPort		  1
	  Points		  [55, 0]
	  Branch {
	    DstBlock		    "Concat13"
	    DstPort		    5
	  }
	  Branch {
	    Points		    [0, 230]
	    DstBlock		    "LSB+5"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "T2"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    DstBlock		    "Concat13"
	    DstPort		    6
	  }
	  Branch {
	    Points		    [0, 175]
	    DstBlock		    "LSB+3"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "T1"
	  SrcPort		  1
	  Points		  [65, 0]
	  Branch {
	    DstBlock		    "Concat13"
	    DstPort		    7
	  }
	  Branch {
	    Points		    [0, 120]
	    DstBlock		    "LSB+1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "T0"
	  SrcPort		  1
	  Points		  [70, 0]
	  Branch {
	    DstBlock		    "Concat13"
	    DstPort		    8
	  }
	  Branch {
	    Points		    [0, 65]
	    DstBlock		    "LSB+2"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "LSB+2"
	  SrcPort		  1
	  Points		  [40, 0]
	  Branch {
	    DstBlock		    "timer0_active"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Logical"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "LSB+1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    DstBlock		    "timer1_active"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 230]
	    DstBlock		    "Logical"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "LSB+3"
	  SrcPort		  1
	  Points		  [30, 0]
	  Branch {
	    DstBlock		    "timer2_active"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 210]
	    DstBlock		    "Logical"
	    DstPort		    3
	  }
	}
	Line {
	  SrcBlock		  "LSB+5"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    DstBlock		    "timer3_active"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 190]
	    DstBlock		    "Logical"
	    DstPort		    4
	  }
	}
	Line {
	  SrcBlock		  "LSB+4"
	  SrcPort		  1
	  Points		  [20, 0]
	  Branch {
	    DstBlock		    "timer4_active"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 170]
	    DstBlock		    "Logical"
	    DstPort		    5
	  }
	}
	Line {
	  SrcBlock		  "LSB+6"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "timer5_active"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 150]
	    DstBlock		    "Logical"
	    DstPort		    6
	  }
	}
	Line {
	  SrcBlock		  "LSB+7"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    DstBlock		    "timer6_active"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 130]
	    DstBlock		    "Logical"
	    DstPort		    7
	  }
	}
	Line {
	  SrcBlock		  "LSB+8"
	  SrcPort		  1
	  Points		  [5, 0]
	  Branch {
	    DstBlock		    "timer7_active"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110]
	    DstBlock		    "Logical"
	    DstPort		    8
	  }
	}
	Line {
	  SrcBlock		  "Logical"
	  SrcPort		  1
	  DstBlock		  "TIMEREXPIRE"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Concat13"
	  SrcPort		  1
	  DstBlock		  "Goto"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Timer 0"
      Ports		      [7, 4]
      Position		      [335, 80, 440, 200]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Timer 0"
	Location		[202, 70, 1438, 850]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "start"
	  Position		  [310, 283, 340, 297]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "pause"
	  Position		  [310, 323, 340, 337]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "mode"
	  Position		  [255, 648, 285, 662]
	  NamePlacement		  "alternate"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "done_reset"
	  Position		  [1175, 283, 1205, 297]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotCount"
	  Position		  [980, 238, 1010, 252]
	  NamePlacement		  "alternate"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotTime"
	  Position		  [930, 658, 960, 672]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "Medium Idle"
	  Position		  [250, 698, 280, 712]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AddSub"
	  Ports			  [2, 1]
	  Position		  [1210, 339, 1255, 386]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/AddSub"
	  SourceType		  "Xilinx Adder/Subtractor Block"
	  mode			  "Subtraction"
	  use_carryin		  off
	  use_carryout		  off
	  en			  off
	  latency		  "0"
	  precision		  "User Defined"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  pipelined		  off
	  use_rpm		  on
	  hw_selection		  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[16 0 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "addsub"
	  block_version		  "8.2"
	  sg_icon_stat		  "45,47,2,1,white,blue,0,46b4c804,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [940, 454, 970, 466]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "32"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "50,50,400,346"
	  block_type		  "constant"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "30,12,0,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  Ports			  [0, 1]
	  Position		  [255, 672, 290, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "1"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,16,0,1,white,blue,0,06094819,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [260, 261, 275, 279]
	  ShowName		  off
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [315, 576, 330, 594]
	  ShowName		  off
	  Value			  "0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Convert1"
	  Ports			  [1, 1]
	  Position		  [380, 670, 415, 690]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Convert"
	  SourceType		  "Xilinx Type Converter Block"
	  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  latency		  "0"
	  dbl_ovrd		  off
	  pipeline		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,461,375"
	  block_type		  "convert"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,20,1,1,white,blue,0,74901e60,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter"
	  Ports			  [2, 1]
	  Position		  [905, 224, 965, 326]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter1"
	  Ports			  [2, 1]
	  Position		  [835, 644, 895, 746]
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [1, 1]
	  Position		  [925, 331, 950, 359]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Delay"
	  SourceType		  "Xilinx Delay Block"
	  infoedit		  "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  reg_retiming		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "delay"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "25,28,1,1,white,blue,0,fc531c0e,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 24 18 13 9 14 9 13 18 24 17 15 13 6 ],[4 8 14 20 24 24 22 24 24 18 23 19 14 9 5 10 4 4 6 4 4 ],[0.98 0.96 0.92]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter"
	  Ports			  [1, 1]
	  Position		  [1080, 476, 1125, 494]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter1"
	  Ports			  [1, 1]
	  Position		  [590, 661, 635, 679]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical1"
	  Ports			  [2, 1]
	  Position		  [855, 231, 885, 264]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical2"
	  Ports			  [2, 1]
	  Position		  [590, 306, 620, 339]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical3"
	  Ports			  [2, 1]
	  Position		  [590, 271, 620, 304]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical4"
	  Ports			  [2, 1]
	  Position		  [1155, 433, 1200, 502]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,69,2,1,white,blue,0,087b5522,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical5"
	  Ports			  [3, 1]
	  Position		  [770, 652, 805, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,bd50cad4,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical6"
	  Ports			  [3, 1]
	  Position		  [850, 282, 885, 318]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical7"
	  Ports			  [3, 1]
	  Position		  [1175, 243, 1205, 277]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,34,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 34 34 ],[0.77 0.82 0.91]);\npatch([7 2 9 2 7 15 17 19 27 20 14 9 15 9 14 20 27 19 17 15 7 ],[5 10 17 24 29 29 27 29 29 22 28 23 17 11 6 12 5 5 7 5 5 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Mux"
	  Ports			  [3, 1]
	  Position		  [320, 643, 345, 717]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Mux"
	  SourceType		  "Xilinx Bus Multiplexer Block"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mux"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,74,3,1,white,blue,3,613f58e1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational"
	  Ports			  [2, 1]
	  Position		  [1060, 231, 1100, 289]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational1"
	  Ports			  [2, 1]
	  Position		  [1005, 431, 1050, 469]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a>b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[16 1 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,38,2,1,white,blue,0,064af3a6,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational2"
	  Ports			  [2, 1]
	  Position		  [985, 651, 1025, 709]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch1"
	  Ports			  [2, 1]
	  Position		  [665, 272, 705, 343]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch1"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch2"
	  Ports			  [2, 1]
	  Position		  [1285, 245, 1325, 305]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch2"
	    Location		    [521, 318, 918, 591]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch3"
	  Ports			  [2, 1]
	  Position		  [665, 167, 705, 238]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch3"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  Scope
	  Name			  "Scope"
	  Ports			  [3]
	  Position		  [1530, 305, 1560, 405]
	  Floating		  off
	  Location		  [1, 45, 1441, 869]
	  Open			  off
	  NumInputPorts		  "3"
	  ZoomMode		  "xonly"
	  List {
	    ListType		    AxesTitles
	    axes1		    "%<SignalLabel>"
	    axes2		    "%<SignalLabel>"
	    axes3		    "%<SignalLabel>"
	  }
	  YMin			  "-5~-5~-5"
	  YMax			  "5~5~5"
	  DataFormat		  "StructureWithTime"
	  SampleTime		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux"
	  Ports			  [2, 1]
	  Position		  [405, 261, 445, 299]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux1"
	  Ports			  [2, 1]
	  Position		  [470, 576, 510, 614]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In"
	  Ports			  [1, 1]
	  Position		  [305, 260, 350, 280]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In"
	    Location		    [269, 280, 494, 362]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [86, 85, 144, 143]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In2"
	  Ports			  [1, 1]
	  Position		  [360, 575, 405, 595]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In2"
	    Location		    [214, 70, 1918, 1152]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [71, 110, 129, 168]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "negedge"
	  Ports			  [1, 1]
	  Position		  [495, 288, 525, 302]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "negedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [170, 213, 200, 227]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [230, 247, 290, 303]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [290, 191, 345, 249]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [410, 205, 465, 265]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [490, 228, 520, 242]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [90, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      DstBlock		      "Logical"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge"
	  Ports			  [1, 1]
	  Position		  [495, 273, 525, 287]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge2"
	  Ports			  [1, 1]
	  Position		  [495, 323, 525, 337]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge2"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "done"
	  Position		  [1350, 268, 1380, 282]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "running"
	  Position		  [1245, 518, 1275, 532]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "paused"
	  Position		  [1240, 463, 1270, 477]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "timeLeft"
	  Position		  [1285, 358, 1315, 372]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Line {
	  SrcBlock		  "mode"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Medium Idle"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "Convert1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical4"
	  SrcPort		  1
	  DstBlock		  "paused"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "start"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sim Mux"
	  SrcPort		  1
	  DstBlock		  "posedge"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "AddSub"
	  SrcPort		  1
	  DstBlock		  "timeLeft"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "Relational1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational1"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Inverter"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "S-R_Latch1"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    Points		    [0, 175]
	    Branch {
	      Points		      [0, 235]
	      DstBlock		      "Counter1"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [290, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, 40]
		DstBlock		"running"
		DstPort			1
	      }
	    }
	  }
	  Branch {
	    Points		    [0, -20]
	    DstBlock		    "Logical6"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "slotCount"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    Points		    [0, 105]
	    DstBlock		    "AddSub"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Relational"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Counter"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "Relational"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 100]
	    Branch {
	      DstBlock		      "AddSub"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [0, 30]
	      Branch {
		Points			[0, 35]
		DstBlock		"Relational1"
		DstPort			1
	      }
	      Branch {
		Points			[445, 0; 0, -85]
		DstBlock		"Scope"
		DstPort			1
	      }
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical1"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S-R_Latch2"
	  SrcPort		  1
	  DstBlock		  "done"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Relational"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    Points		    [0, 110; -550, 0; 0, -40]
	    DstBlock		    "Logical2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -80; -290, 0; 0, 60]
	    DstBlock		    "Logical1"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Logical7"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "done_reset"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "S-R_Latch2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -145; -625, 0; 0, 75]
	    DstBlock		    "S-R_Latch3"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "posedge"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Logical3"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 400]
	    DstBlock		    "Logical5"
	    DstPort		    3
	  }
	  Branch {
	    Points		    [0, -25]
	    Branch {
	      DstBlock		      "Logical1"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [0, -70]
	      DstBlock		      "S-R_Latch3"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical3"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "negedge"
	  SrcPort		  1
	  DstBlock		  "Logical3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "pause"
	  SrcPort		  1
	  Points		  [115, 0]
	  Branch {
	    DstBlock		    "posedge2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, -35]
	    DstBlock		    "negedge"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "slotTime"
	  SrcPort		  1
	  DstBlock		  "Relational2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    DstBlock		    "Relational2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 35; 505, 0; 0, -340]
	    DstBlock		    "Scope"
	    DstPort		    3
	  }
	}
	Line {
	  SrcBlock		  "Logical5"
	  SrcPort		  1
	  DstBlock		  "Counter1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Relational2"
	  SrcPort		  1
	  Points		  [20, 0; 0, -60]
	  Branch {
	    Points		    [-295, 0]
	    Branch {
	      DstBlock		      "Logical5"
	      DstPort		      1
	    }
	    Branch {
	      Points		      [0, -320]
	      DstBlock		      "Logical6"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Points		    [380, 0; 0, -265]
	    DstBlock		    "Scope"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Inverter1"
	  SrcPort		  1
	  DstBlock		  "Logical5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical6"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Convert1"
	  SrcPort		  1
	  Points		  [25, 0; 0, -75]
	  DstBlock		  "Sim Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sim Mux1"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    DstBlock		    "Inverter1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [260, 0; 0, -250]
	    Branch {
	      DstBlock		      "Logical6"
	      DstPort		      3
	    }
	    Branch {
	      DstBlock		      "Delay"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "posedge2"
	  SrcPort		  1
	  Points		  [25, 0; 0, -15]
	  DstBlock		  "Logical2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical2"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In2"
	  SrcPort		  1
	  DstBlock		  "Sim Mux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical7"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S-R_Latch3"
	  SrcPort		  1
	  Points		  [70, 0; 0, -50; 350, 0; 0, 95]
	  DstBlock		  "Logical7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  Points		  [195, 0; 0, -75]
	  DstBlock		  "Logical7"
	  DstPort		  3
	}
	Annotation {
	  Name			  "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount to 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until the next user-initiated start."
	  Position		  [697, 92]
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Timer 1"
      Ports		      [7, 4]
      Position		      [335, 215, 440, 335]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Timer 1"
	Location		[214, 74, 1910, 1156]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "start"
	  Position		  [310, 283, 340, 297]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "pause"
	  Position		  [310, 323, 340, 337]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "mode"
	  Position		  [255, 648, 285, 662]
	  NamePlacement		  "alternate"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "done_reset"
	  Position		  [1175, 283, 1205, 297]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotCount"
	  Position		  [980, 238, 1010, 252]
	  NamePlacement		  "alternate"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotTime"
	  Position		  [930, 658, 960, 672]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "Medium Idle"
	  Position		  [250, 698, 280, 712]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AddSub"
	  Ports			  [2, 1]
	  Position		  [1210, 339, 1255, 386]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/AddSub"
	  SourceType		  "Xilinx Adder/Subtractor Block"
	  mode			  "Subtraction"
	  use_carryin		  off
	  use_carryout		  off
	  en			  off
	  latency		  "0"
	  precision		  "User Defined"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  pipelined		  off
	  use_rpm		  on
	  hw_selection		  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[16 0 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "addsub"
	  block_version		  "8.2"
	  sg_icon_stat		  "45,47,2,1,white,blue,0,46b4c804,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [940, 454, 970, 466]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "32"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "50,50,400,346"
	  block_type		  "constant"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "30,12,0,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  Ports			  [0, 1]
	  Position		  [255, 672, 290, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "1"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,16,0,1,white,blue,0,06094819,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [260, 261, 275, 279]
	  ShowName		  off
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [315, 576, 330, 594]
	  ShowName		  off
	  Value			  "0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Convert1"
	  Ports			  [1, 1]
	  Position		  [380, 670, 415, 690]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Convert"
	  SourceType		  "Xilinx Type Converter Block"
	  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  latency		  "0"
	  dbl_ovrd		  off
	  pipeline		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,461,375"
	  block_type		  "convert"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,20,1,1,white,blue,0,74901e60,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter"
	  Ports			  [2, 1]
	  Position		  [905, 224, 965, 326]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter1"
	  Ports			  [2, 1]
	  Position		  [835, 644, 895, 746]
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [1, 1]
	  Position		  [925, 331, 950, 359]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Delay"
	  SourceType		  "Xilinx Delay Block"
	  infoedit		  "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  reg_retiming		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "delay"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "25,28,1,1,white,blue,0,fc531c0e,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 24 18 13 9 14 9 13 18 24 17 15 13 6 ],[4 8 14 20 24 24 22 24 24 18 23 19 14 9 5 10 4 4 6 4 4 ],[0.98 0.96 0.92]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter"
	  Ports			  [1, 1]
	  Position		  [1080, 476, 1125, 494]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter1"
	  Ports			  [1, 1]
	  Position		  [590, 661, 635, 679]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical1"
	  Ports			  [2, 1]
	  Position		  [855, 231, 885, 264]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical2"
	  Ports			  [2, 1]
	  Position		  [590, 306, 620, 339]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical3"
	  Ports			  [2, 1]
	  Position		  [590, 271, 620, 304]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical4"
	  Ports			  [2, 1]
	  Position		  [1155, 433, 1200, 502]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,69,2,1,white,blue,0,087b5522,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical5"
	  Ports			  [3, 1]
	  Position		  [770, 652, 805, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,bd50cad4,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical6"
	  Ports			  [3, 1]
	  Position		  [850, 282, 885, 318]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical7"
	  Ports			  [3, 1]
	  Position		  [1175, 243, 1205, 277]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,34,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 34 34 ],[0.77 0.82 0.91]);\npatch([7 2 9 2 7 15 17 19 27 20 14 9 15 9 14 20 27 19 17 15 7 ],[5 10 17 24 29 29 27 29 29 22 28 23 17 11 6 12 5 5 7 5 5 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Mux"
	  Ports			  [3, 1]
	  Position		  [320, 643, 345, 717]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Mux"
	  SourceType		  "Xilinx Bus Multiplexer Block"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mux"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,74,3,1,white,blue,3,613f58e1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational"
	  Ports			  [2, 1]
	  Position		  [1060, 231, 1100, 289]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational1"
	  Ports			  [2, 1]
	  Position		  [1005, 431, 1050, 469]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a>b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[16 1 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,38,2,1,white,blue,0,064af3a6,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational2"
	  Ports			  [2, 1]
	  Position		  [985, 651, 1025, 709]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch1"
	  Ports			  [2, 1]
	  Position		  [665, 272, 705, 343]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch1"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch2"
	  Ports			  [2, 1]
	  Position		  [1285, 245, 1325, 305]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch2"
	    Location		    [521, 318, 918, 591]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch3"
	  Ports			  [2, 1]
	  Position		  [665, 167, 705, 238]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch3"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  Scope
	  Name			  "Scope"
	  Ports			  [3]
	  Position		  [1530, 305, 1560, 405]
	  Floating		  off
	  Location		  [1, 45, 1441, 869]
	  Open			  off
	  NumInputPorts		  "3"
	  ZoomMode		  "xonly"
	  List {
	    ListType		    AxesTitles
	    axes1		    "%<SignalLabel>"
	    axes2		    "%<SignalLabel>"
	    axes3		    "%<SignalLabel>"
	  }
	  YMin			  "-5~-5~-5"
	  YMax			  "5~5~5"
	  DataFormat		  "StructureWithTime"
	  SampleTime		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux"
	  Ports			  [2, 1]
	  Position		  [405, 261, 445, 299]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux1"
	  Ports			  [2, 1]
	  Position		  [470, 576, 510, 614]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In"
	  Ports			  [1, 1]
	  Position		  [305, 260, 350, 280]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In"
	    Location		    [269, 280, 494, 362]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [86, 85, 144, 143]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In2"
	  Ports			  [1, 1]
	  Position		  [360, 575, 405, 595]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In2"
	    Location		    [214, 70, 1918, 1152]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [71, 110, 129, 168]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "negedge"
	  Ports			  [1, 1]
	  Position		  [495, 288, 525, 302]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "negedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [170, 213, 200, 227]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [230, 247, 290, 303]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [290, 191, 345, 249]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [410, 205, 465, 265]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [490, 228, 520, 242]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      DstBlock		      "Logical"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [90, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge"
	  Ports			  [1, 1]
	  Position		  [495, 273, 525, 287]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge2"
	  Ports			  [1, 1]
	  Position		  [495, 323, 525, 337]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge2"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "done"
	  Position		  [1350, 268, 1380, 282]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "running"
	  Position		  [1245, 518, 1275, 532]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "paused"
	  Position		  [1240, 463, 1270, 477]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "timeLeft"
	  Position		  [1285, 358, 1315, 372]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  Points		  [195, 0; 0, -75]
	  DstBlock		  "Logical7"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "S-R_Latch3"
	  SrcPort		  1
	  Points		  [70, 0; 0, -50; 350, 0; 0, 95]
	  DstBlock		  "Logical7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical7"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In2"
	  SrcPort		  1
	  DstBlock		  "Sim Mux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical2"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "posedge2"
	  SrcPort		  1
	  Points		  [25, 0; 0, -15]
	  DstBlock		  "Logical2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim Mux1"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    Points		    [260, 0; 0, -250]
	    Branch {
	      DstBlock		      "Delay"
	      DstPort		      1
	    }
	    Branch {
	      DstBlock		      "Logical6"
	      DstPort		      3
	    }
	  }
	  Branch {
	    DstBlock		    "Inverter1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Convert1"
	  SrcPort		  1
	  Points		  [25, 0; 0, -75]
	  DstBlock		  "Sim Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical6"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Inverter1"
	  SrcPort		  1
	  DstBlock		  "Logical5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational2"
	  SrcPort		  1
	  Points		  [20, 0; 0, -60]
	  Branch {
	    Points		    [380, 0; 0, -265]
	    DstBlock		    "Scope"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [-295, 0]
	    Branch {
	      Points		      [0, -320]
	      DstBlock		      "Logical6"
	      DstPort		      2
	    }
	    Branch {
	      DstBlock		      "Logical5"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical5"
	  SrcPort		  1
	  DstBlock		  "Counter1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    Points		    [0, 35; 505, 0; 0, -340]
	    DstBlock		    "Scope"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "Relational2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "slotTime"
	  SrcPort		  1
	  DstBlock		  "Relational2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "pause"
	  SrcPort		  1
	  Points		  [115, 0]
	  Branch {
	    Points		    [0, -35]
	    DstBlock		    "negedge"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "posedge2"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "negedge"
	  SrcPort		  1
	  DstBlock		  "Logical3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical3"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "posedge"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -25]
	    Branch {
	      Points		      [0, -70]
	      DstBlock		      "S-R_Latch3"
	      DstPort		      1
	    }
	    Branch {
	      DstBlock		      "Logical1"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Points		    [0, 400]
	    DstBlock		    "Logical5"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "Logical3"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "done_reset"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -145; -625, 0; 0, 75]
	    DstBlock		    "S-R_Latch3"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "S-R_Latch2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Relational"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    DstBlock		    "Logical7"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -80; -290, 0; 0, 60]
	    DstBlock		    "Logical1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110; -550, 0; 0, -40]
	    DstBlock		    "Logical2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "S-R_Latch2"
	  SrcPort		  1
	  DstBlock		  "done"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical1"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Points		    [0, 100]
	    Branch {
	      Points		      [0, 30]
	      Branch {
		Points			[445, 0; 0, -85]
		DstBlock		"Scope"
		DstPort			1
	      }
	      Branch {
		Points			[0, 35]
		DstBlock		"Relational1"
		DstPort			1
	      }
	    }
	    Branch {
	      DstBlock		      "AddSub"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "Relational"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "slotCount"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    DstBlock		    "Relational"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 105]
	    DstBlock		    "AddSub"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "S-R_Latch1"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    Points		    [0, -20]
	    DstBlock		    "Logical6"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 175]
	    Branch {
	      Points		      [290, 0]
	      Branch {
		Points			[0, 40]
		DstBlock		"running"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	    Branch {
	      Points		      [0, 235]
	      DstBlock		      "Counter1"
	      DstPort		      2
	    }
	  }
	}
	Line {
	  SrcBlock		  "Inverter"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational1"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "Relational1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "AddSub"
	  SrcPort		  1
	  DstBlock		  "timeLeft"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim Mux"
	  SrcPort		  1
	  DstBlock		  "posedge"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "start"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical4"
	  SrcPort		  1
	  DstBlock		  "paused"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "Convert1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Medium Idle"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "mode"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Annotation {
	  Name			  "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount to 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until the next user-initiated start."
	  Position		  [697, 92]
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Timer 2"
      Ports		      [7, 4]
      Position		      [335, 350, 440, 470]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Timer 2"
	Location		[214, 74, 1910, 1156]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "start"
	  Position		  [310, 283, 340, 297]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "pause"
	  Position		  [310, 323, 340, 337]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "mode"
	  Position		  [255, 648, 285, 662]
	  NamePlacement		  "alternate"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "done_reset"
	  Position		  [1175, 283, 1205, 297]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotCount"
	  Position		  [980, 238, 1010, 252]
	  NamePlacement		  "alternate"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotTime"
	  Position		  [930, 658, 960, 672]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "Medium Idle"
	  Position		  [250, 698, 280, 712]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AddSub"
	  Ports			  [2, 1]
	  Position		  [1210, 339, 1255, 386]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/AddSub"
	  SourceType		  "Xilinx Adder/Subtractor Block"
	  mode			  "Subtraction"
	  use_carryin		  off
	  use_carryout		  off
	  en			  off
	  latency		  "0"
	  precision		  "User Defined"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  pipelined		  off
	  use_rpm		  on
	  hw_selection		  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[16 0 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "addsub"
	  block_version		  "8.2"
	  sg_icon_stat		  "45,47,2,1,white,blue,0,46b4c804,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [940, 454, 970, 466]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "32"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "50,50,400,346"
	  block_type		  "constant"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "30,12,0,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  Ports			  [0, 1]
	  Position		  [255, 672, 290, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "1"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,16,0,1,white,blue,0,06094819,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [260, 261, 275, 279]
	  ShowName		  off
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [315, 576, 330, 594]
	  ShowName		  off
	  Value			  "0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Convert1"
	  Ports			  [1, 1]
	  Position		  [380, 670, 415, 690]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Convert"
	  SourceType		  "Xilinx Type Converter Block"
	  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  latency		  "0"
	  dbl_ovrd		  off
	  pipeline		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,461,375"
	  block_type		  "convert"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,20,1,1,white,blue,0,74901e60,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter"
	  Ports			  [2, 1]
	  Position		  [905, 224, 965, 326]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter1"
	  Ports			  [2, 1]
	  Position		  [835, 644, 895, 746]
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [1, 1]
	  Position		  [925, 331, 950, 359]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Delay"
	  SourceType		  "Xilinx Delay Block"
	  infoedit		  "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  reg_retiming		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "delay"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "25,28,1,1,white,blue,0,fc531c0e,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 24 18 13 9 14 9 13 18 24 17 15 13 6 ],[4 8 14 20 24 24 22 24 24 18 23 19 14 9 5 10 4 4 6 4 4 ],[0.98 0.96 0.92]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter"
	  Ports			  [1, 1]
	  Position		  [1080, 476, 1125, 494]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter1"
	  Ports			  [1, 1]
	  Position		  [590, 661, 635, 679]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical1"
	  Ports			  [2, 1]
	  Position		  [855, 231, 885, 264]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical2"
	  Ports			  [2, 1]
	  Position		  [590, 306, 620, 339]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical3"
	  Ports			  [2, 1]
	  Position		  [590, 271, 620, 304]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical4"
	  Ports			  [2, 1]
	  Position		  [1155, 433, 1200, 502]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,69,2,1,white,blue,0,087b5522,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical5"
	  Ports			  [3, 1]
	  Position		  [770, 652, 805, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,bd50cad4,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical6"
	  Ports			  [3, 1]
	  Position		  [850, 282, 885, 318]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical7"
	  Ports			  [3, 1]
	  Position		  [1175, 243, 1205, 277]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,34,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 34 34 ],[0.77 0.82 0.91]);\npatch([7 2 9 2 7 15 17 19 27 20 14 9 15 9 14 20 27 19 17 15 7 ],[5 10 17 24 29 29 27 29 29 22 28 23 17 11 6 12 5 5 7 5 5 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Mux"
	  Ports			  [3, 1]
	  Position		  [320, 643, 345, 717]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Mux"
	  SourceType		  "Xilinx Bus Multiplexer Block"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mux"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,74,3,1,white,blue,3,613f58e1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational"
	  Ports			  [2, 1]
	  Position		  [1060, 231, 1100, 289]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational1"
	  Ports			  [2, 1]
	  Position		  [1005, 431, 1050, 469]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a>b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[16 1 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,38,2,1,white,blue,0,064af3a6,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational2"
	  Ports			  [2, 1]
	  Position		  [985, 651, 1025, 709]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch1"
	  Ports			  [2, 1]
	  Position		  [665, 272, 705, 343]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch1"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch2"
	  Ports			  [2, 1]
	  Position		  [1285, 245, 1325, 305]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch2"
	    Location		    [521, 318, 918, 591]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch3"
	  Ports			  [2, 1]
	  Position		  [665, 167, 705, 238]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch3"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  Scope
	  Name			  "Scope"
	  Ports			  [3]
	  Position		  [1530, 305, 1560, 405]
	  Floating		  off
	  Location		  [1, 45, 1441, 869]
	  Open			  off
	  NumInputPorts		  "3"
	  ZoomMode		  "xonly"
	  List {
	    ListType		    AxesTitles
	    axes1		    "%<SignalLabel>"
	    axes2		    "%<SignalLabel>"
	    axes3		    "%<SignalLabel>"
	  }
	  YMin			  "-5~-5~-5"
	  YMax			  "5~5~5"
	  DataFormat		  "StructureWithTime"
	  SampleTime		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux"
	  Ports			  [2, 1]
	  Position		  [405, 261, 445, 299]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux1"
	  Ports			  [2, 1]
	  Position		  [470, 576, 510, 614]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In"
	  Ports			  [1, 1]
	  Position		  [305, 260, 350, 280]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In"
	    Location		    [269, 280, 494, 362]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [86, 85, 144, 143]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In2"
	  Ports			  [1, 1]
	  Position		  [360, 575, 405, 595]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In2"
	    Location		    [214, 70, 1918, 1152]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [71, 110, 129, 168]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "negedge"
	  Ports			  [1, 1]
	  Position		  [495, 288, 525, 302]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "negedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [170, 213, 200, 227]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [230, 247, 290, 303]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [290, 191, 345, 249]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [410, 205, 465, 265]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [490, 228, 520, 242]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [90, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      DstBlock		      "Logical"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge"
	  Ports			  [1, 1]
	  Position		  [495, 273, 525, 287]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
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	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
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	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge2"
	  Ports			  [1, 1]
	  Position		  [495, 323, 525, 337]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge2"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "done"
	  Position		  [1350, 268, 1380, 282]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "running"
	  Position		  [1245, 518, 1275, 532]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "paused"
	  Position		  [1240, 463, 1270, 477]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "timeLeft"
	  Position		  [1285, 358, 1315, 372]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Line {
	  SrcBlock		  "mode"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Medium Idle"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "Convert1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical4"
	  SrcPort		  1
	  DstBlock		  "paused"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "start"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sim Mux"
	  SrcPort		  1
	  DstBlock		  "posedge"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "AddSub"
	  SrcPort		  1
	  DstBlock		  "timeLeft"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "Relational1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational1"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Inverter"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "S-R_Latch1"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    Points		    [0, 175]
	    Branch {
	      Points		      [0, 235]
	      DstBlock		      "Counter1"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [290, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, 40]
		DstBlock		"running"
		DstPort			1
	      }
	    }
	  }
	  Branch {
	    Points		    [0, -20]
	    DstBlock		    "Logical6"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "slotCount"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    Points		    [0, 105]
	    DstBlock		    "AddSub"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Relational"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Counter"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "Relational"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 100]
	    Branch {
	      DstBlock		      "AddSub"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [0, 30]
	      Branch {
		Points			[0, 35]
		DstBlock		"Relational1"
		DstPort			1
	      }
	      Branch {
		Points			[445, 0; 0, -85]
		DstBlock		"Scope"
		DstPort			1
	      }
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical1"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S-R_Latch2"
	  SrcPort		  1
	  DstBlock		  "done"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Relational"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    Points		    [0, 110; -550, 0; 0, -40]
	    DstBlock		    "Logical2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -80; -290, 0; 0, 60]
	    DstBlock		    "Logical1"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Logical7"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "done_reset"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "S-R_Latch2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -145; -625, 0; 0, 75]
	    DstBlock		    "S-R_Latch3"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "posedge"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Logical3"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 400]
	    DstBlock		    "Logical5"
	    DstPort		    3
	  }
	  Branch {
	    Points		    [0, -25]
	    Branch {
	      DstBlock		      "Logical1"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [0, -70]
	      DstBlock		      "S-R_Latch3"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical3"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "negedge"
	  SrcPort		  1
	  DstBlock		  "Logical3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "pause"
	  SrcPort		  1
	  Points		  [115, 0]
	  Branch {
	    DstBlock		    "posedge2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, -35]
	    DstBlock		    "negedge"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "slotTime"
	  SrcPort		  1
	  DstBlock		  "Relational2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    DstBlock		    "Relational2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 35; 505, 0; 0, -340]
	    DstBlock		    "Scope"
	    DstPort		    3
	  }
	}
	Line {
	  SrcBlock		  "Logical5"
	  SrcPort		  1
	  DstBlock		  "Counter1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Relational2"
	  SrcPort		  1
	  Points		  [20, 0; 0, -60]
	  Branch {
	    Points		    [-295, 0]
	    Branch {
	      DstBlock		      "Logical5"
	      DstPort		      1
	    }
	    Branch {
	      Points		      [0, -320]
	      DstBlock		      "Logical6"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Points		    [380, 0; 0, -265]
	    DstBlock		    "Scope"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Inverter1"
	  SrcPort		  1
	  DstBlock		  "Logical5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical6"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Convert1"
	  SrcPort		  1
	  Points		  [25, 0; 0, -75]
	  DstBlock		  "Sim Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sim Mux1"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    DstBlock		    "Inverter1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [260, 0; 0, -250]
	    Branch {
	      DstBlock		      "Logical6"
	      DstPort		      3
	    }
	    Branch {
	      DstBlock		      "Delay"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "posedge2"
	  SrcPort		  1
	  Points		  [25, 0; 0, -15]
	  DstBlock		  "Logical2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical2"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In2"
	  SrcPort		  1
	  DstBlock		  "Sim Mux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical7"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S-R_Latch3"
	  SrcPort		  1
	  Points		  [70, 0; 0, -50; 350, 0; 0, 95]
	  DstBlock		  "Logical7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  Points		  [195, 0; 0, -75]
	  DstBlock		  "Logical7"
	  DstPort		  3
	}
	Annotation {
	  Name			  "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount to 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until the next user-initiated start."
	  Position		  [697, 92]
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Timer 3"
      Ports		      [7, 4]
      Position		      [335, 490, 440, 610]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Timer 3"
	Location		[214, 74, 1910, 1156]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "start"
	  Position		  [310, 283, 340, 297]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "pause"
	  Position		  [310, 323, 340, 337]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "mode"
	  Position		  [255, 648, 285, 662]
	  NamePlacement		  "alternate"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "done_reset"
	  Position		  [1175, 283, 1205, 297]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotCount"
	  Position		  [980, 238, 1010, 252]
	  NamePlacement		  "alternate"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotTime"
	  Position		  [930, 658, 960, 672]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "Medium Idle"
	  Position		  [250, 698, 280, 712]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AddSub"
	  Ports			  [2, 1]
	  Position		  [1210, 339, 1255, 386]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/AddSub"
	  SourceType		  "Xilinx Adder/Subtractor Block"
	  mode			  "Subtraction"
	  use_carryin		  off
	  use_carryout		  off
	  en			  off
	  latency		  "0"
	  precision		  "User Defined"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  pipelined		  off
	  use_rpm		  on
	  hw_selection		  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[16 0 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "addsub"
	  block_version		  "8.2"
	  sg_icon_stat		  "45,47,2,1,white,blue,0,46b4c804,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [940, 454, 970, 466]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "32"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "50,50,400,346"
	  block_type		  "constant"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "30,12,0,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  Ports			  [0, 1]
	  Position		  [255, 672, 290, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "1"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,16,0,1,white,blue,0,06094819,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [260, 261, 275, 279]
	  ShowName		  off
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [315, 576, 330, 594]
	  ShowName		  off
	  Value			  "0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Convert1"
	  Ports			  [1, 1]
	  Position		  [380, 670, 415, 690]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Convert"
	  SourceType		  "Xilinx Type Converter Block"
	  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  latency		  "0"
	  dbl_ovrd		  off
	  pipeline		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,461,375"
	  block_type		  "convert"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,20,1,1,white,blue,0,74901e60,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter"
	  Ports			  [2, 1]
	  Position		  [905, 224, 965, 326]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter1"
	  Ports			  [2, 1]
	  Position		  [835, 644, 895, 746]
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [1, 1]
	  Position		  [925, 331, 950, 359]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Delay"
	  SourceType		  "Xilinx Delay Block"
	  infoedit		  "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  reg_retiming		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "delay"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "25,28,1,1,white,blue,0,fc531c0e,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 24 18 13 9 14 9 13 18 24 17 15 13 6 ],[4 8 14 20 24 24 22 24 24 18 23 19 14 9 5 10 4 4 6 4 4 ],[0.98 0.96 0.92]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter"
	  Ports			  [1, 1]
	  Position		  [1080, 476, 1125, 494]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter1"
	  Ports			  [1, 1]
	  Position		  [590, 661, 635, 679]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical1"
	  Ports			  [2, 1]
	  Position		  [855, 231, 885, 264]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical2"
	  Ports			  [2, 1]
	  Position		  [590, 306, 620, 339]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical3"
	  Ports			  [2, 1]
	  Position		  [590, 271, 620, 304]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical4"
	  Ports			  [2, 1]
	  Position		  [1155, 433, 1200, 502]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,69,2,1,white,blue,0,087b5522,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical5"
	  Ports			  [3, 1]
	  Position		  [770, 652, 805, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,bd50cad4,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical6"
	  Ports			  [3, 1]
	  Position		  [850, 282, 885, 318]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical7"
	  Ports			  [3, 1]
	  Position		  [1175, 243, 1205, 277]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,34,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 34 34 ],[0.77 0.82 0.91]);\npatch([7 2 9 2 7 15 17 19 27 20 14 9 15 9 14 20 27 19 17 15 7 ],[5 10 17 24 29 29 27 29 29 22 28 23 17 11 6 12 5 5 7 5 5 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Mux"
	  Ports			  [3, 1]
	  Position		  [320, 643, 345, 717]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Mux"
	  SourceType		  "Xilinx Bus Multiplexer Block"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mux"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,74,3,1,white,blue,3,613f58e1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational"
	  Ports			  [2, 1]
	  Position		  [1060, 231, 1100, 289]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational1"
	  Ports			  [2, 1]
	  Position		  [1005, 431, 1050, 469]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a>b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[16 1 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,38,2,1,white,blue,0,064af3a6,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational2"
	  Ports			  [2, 1]
	  Position		  [985, 651, 1025, 709]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch1"
	  Ports			  [2, 1]
	  Position		  [665, 272, 705, 343]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch1"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch2"
	  Ports			  [2, 1]
	  Position		  [1285, 245, 1325, 305]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch2"
	    Location		    [521, 318, 918, 591]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch3"
	  Ports			  [2, 1]
	  Position		  [665, 167, 705, 238]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch3"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  Scope
	  Name			  "Scope"
	  Ports			  [3]
	  Position		  [1530, 305, 1560, 405]
	  Floating		  off
	  Location		  [1, 45, 1441, 869]
	  Open			  off
	  NumInputPorts		  "3"
	  ZoomMode		  "xonly"
	  List {
	    ListType		    AxesTitles
	    axes1		    "%<SignalLabel>"
	    axes2		    "%<SignalLabel>"
	    axes3		    "%<SignalLabel>"
	  }
	  YMin			  "-5~-5~-5"
	  YMax			  "5~5~5"
	  DataFormat		  "StructureWithTime"
	  SampleTime		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux"
	  Ports			  [2, 1]
	  Position		  [405, 261, 445, 299]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux1"
	  Ports			  [2, 1]
	  Position		  [470, 576, 510, 614]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In"
	  Ports			  [1, 1]
	  Position		  [305, 260, 350, 280]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In"
	    Location		    [269, 280, 494, 362]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [86, 85, 144, 143]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In2"
	  Ports			  [1, 1]
	  Position		  [360, 575, 405, 595]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In2"
	    Location		    [214, 70, 1918, 1152]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [71, 110, 129, 168]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "negedge"
	  Ports			  [1, 1]
	  Position		  [495, 288, 525, 302]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "negedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [170, 213, 200, 227]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [230, 247, 290, 303]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [290, 191, 345, 249]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [410, 205, 465, 265]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [490, 228, 520, 242]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      DstBlock		      "Logical"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [90, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge"
	  Ports			  [1, 1]
	  Position		  [495, 273, 525, 287]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge2"
	  Ports			  [1, 1]
	  Position		  [495, 323, 525, 337]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge2"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "done"
	  Position		  [1350, 268, 1380, 282]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "running"
	  Position		  [1245, 518, 1275, 532]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "paused"
	  Position		  [1240, 463, 1270, 477]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "timeLeft"
	  Position		  [1285, 358, 1315, 372]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  Points		  [195, 0; 0, -75]
	  DstBlock		  "Logical7"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "S-R_Latch3"
	  SrcPort		  1
	  Points		  [70, 0; 0, -50; 350, 0; 0, 95]
	  DstBlock		  "Logical7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical7"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In2"
	  SrcPort		  1
	  DstBlock		  "Sim Mux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical2"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "posedge2"
	  SrcPort		  1
	  Points		  [25, 0; 0, -15]
	  DstBlock		  "Logical2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim Mux1"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    Points		    [260, 0; 0, -250]
	    Branch {
	      DstBlock		      "Delay"
	      DstPort		      1
	    }
	    Branch {
	      DstBlock		      "Logical6"
	      DstPort		      3
	    }
	  }
	  Branch {
	    DstBlock		    "Inverter1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Convert1"
	  SrcPort		  1
	  Points		  [25, 0; 0, -75]
	  DstBlock		  "Sim Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical6"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Inverter1"
	  SrcPort		  1
	  DstBlock		  "Logical5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational2"
	  SrcPort		  1
	  Points		  [20, 0; 0, -60]
	  Branch {
	    Points		    [380, 0; 0, -265]
	    DstBlock		    "Scope"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [-295, 0]
	    Branch {
	      Points		      [0, -320]
	      DstBlock		      "Logical6"
	      DstPort		      2
	    }
	    Branch {
	      DstBlock		      "Logical5"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical5"
	  SrcPort		  1
	  DstBlock		  "Counter1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    Points		    [0, 35; 505, 0; 0, -340]
	    DstBlock		    "Scope"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "Relational2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "slotTime"
	  SrcPort		  1
	  DstBlock		  "Relational2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "pause"
	  SrcPort		  1
	  Points		  [115, 0]
	  Branch {
	    Points		    [0, -35]
	    DstBlock		    "negedge"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "posedge2"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "negedge"
	  SrcPort		  1
	  DstBlock		  "Logical3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical3"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "posedge"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -25]
	    Branch {
	      Points		      [0, -70]
	      DstBlock		      "S-R_Latch3"
	      DstPort		      1
	    }
	    Branch {
	      DstBlock		      "Logical1"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Points		    [0, 400]
	    DstBlock		    "Logical5"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "Logical3"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "done_reset"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -145; -625, 0; 0, 75]
	    DstBlock		    "S-R_Latch3"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "S-R_Latch2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Relational"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    DstBlock		    "Logical7"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -80; -290, 0; 0, 60]
	    DstBlock		    "Logical1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110; -550, 0; 0, -40]
	    DstBlock		    "Logical2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "S-R_Latch2"
	  SrcPort		  1
	  DstBlock		  "done"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical1"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Points		    [0, 100]
	    Branch {
	      Points		      [0, 30]
	      Branch {
		Points			[445, 0; 0, -85]
		DstBlock		"Scope"
		DstPort			1
	      }
	      Branch {
		Points			[0, 35]
		DstBlock		"Relational1"
		DstPort			1
	      }
	    }
	    Branch {
	      DstBlock		      "AddSub"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "Relational"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "slotCount"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    DstBlock		    "Relational"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 105]
	    DstBlock		    "AddSub"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "S-R_Latch1"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    Points		    [0, -20]
	    DstBlock		    "Logical6"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 175]
	    Branch {
	      Points		      [290, 0]
	      Branch {
		Points			[0, 40]
		DstBlock		"running"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	    Branch {
	      Points		      [0, 235]
	      DstBlock		      "Counter1"
	      DstPort		      2
	    }
	  }
	}
	Line {
	  SrcBlock		  "Inverter"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational1"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "Relational1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "AddSub"
	  SrcPort		  1
	  DstBlock		  "timeLeft"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim Mux"
	  SrcPort		  1
	  DstBlock		  "posedge"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "start"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical4"
	  SrcPort		  1
	  DstBlock		  "paused"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "Convert1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Medium Idle"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "mode"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Annotation {
	  Name			  "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount to 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until the next user-initiated start."
	  Position		  [697, 92]
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Timer 4"
      Ports		      [7, 4]
      Position		      [855, 70, 960, 190]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Timer 4"
	Location		[214, 74, 1910, 1156]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "start"
	  Position		  [310, 283, 340, 297]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "pause"
	  Position		  [310, 323, 340, 337]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "mode"
	  Position		  [255, 648, 285, 662]
	  NamePlacement		  "alternate"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "done_reset"
	  Position		  [1175, 283, 1205, 297]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotCount"
	  Position		  [980, 238, 1010, 252]
	  NamePlacement		  "alternate"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotTime"
	  Position		  [930, 658, 960, 672]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "Medium Idle"
	  Position		  [250, 698, 280, 712]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AddSub"
	  Ports			  [2, 1]
	  Position		  [1210, 339, 1255, 386]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/AddSub"
	  SourceType		  "Xilinx Adder/Subtractor Block"
	  mode			  "Subtraction"
	  use_carryin		  off
	  use_carryout		  off
	  en			  off
	  latency		  "0"
	  precision		  "User Defined"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  pipelined		  off
	  use_rpm		  on
	  hw_selection		  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[16 0 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "addsub"
	  block_version		  "8.2"
	  sg_icon_stat		  "45,47,2,1,white,blue,0,46b4c804,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [940, 454, 970, 466]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "32"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "50,50,400,346"
	  block_type		  "constant"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "30,12,0,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  Ports			  [0, 1]
	  Position		  [255, 672, 290, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "1"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,16,0,1,white,blue,0,06094819,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [260, 261, 275, 279]
	  ShowName		  off
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [315, 576, 330, 594]
	  ShowName		  off
	  Value			  "0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Convert1"
	  Ports			  [1, 1]
	  Position		  [380, 670, 415, 690]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Convert"
	  SourceType		  "Xilinx Type Converter Block"
	  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  latency		  "0"
	  dbl_ovrd		  off
	  pipeline		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,461,375"
	  block_type		  "convert"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,20,1,1,white,blue,0,74901e60,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter"
	  Ports			  [2, 1]
	  Position		  [905, 224, 965, 326]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter1"
	  Ports			  [2, 1]
	  Position		  [835, 644, 895, 746]
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [1, 1]
	  Position		  [925, 331, 950, 359]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Delay"
	  SourceType		  "Xilinx Delay Block"
	  infoedit		  "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  reg_retiming		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "delay"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "25,28,1,1,white,blue,0,fc531c0e,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 24 18 13 9 14 9 13 18 24 17 15 13 6 ],[4 8 14 20 24 24 22 24 24 18 23 19 14 9 5 10 4 4 6 4 4 ],[0.98 0.96 0.92]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter"
	  Ports			  [1, 1]
	  Position		  [1080, 476, 1125, 494]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter1"
	  Ports			  [1, 1]
	  Position		  [590, 661, 635, 679]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical1"
	  Ports			  [2, 1]
	  Position		  [855, 231, 885, 264]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical2"
	  Ports			  [2, 1]
	  Position		  [590, 306, 620, 339]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical3"
	  Ports			  [2, 1]
	  Position		  [590, 271, 620, 304]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical4"
	  Ports			  [2, 1]
	  Position		  [1155, 433, 1200, 502]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,69,2,1,white,blue,0,087b5522,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical5"
	  Ports			  [3, 1]
	  Position		  [770, 652, 805, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,bd50cad4,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical6"
	  Ports			  [3, 1]
	  Position		  [850, 282, 885, 318]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical7"
	  Ports			  [3, 1]
	  Position		  [1175, 243, 1205, 277]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,34,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 34 34 ],[0.77 0.82 0.91]);\npatch([7 2 9 2 7 15 17 19 27 20 14 9 15 9 14 20 27 19 17 15 7 ],[5 10 17 24 29 29 27 29 29 22 28 23 17 11 6 12 5 5 7 5 5 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Mux"
	  Ports			  [3, 1]
	  Position		  [320, 643, 345, 717]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Mux"
	  SourceType		  "Xilinx Bus Multiplexer Block"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mux"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,74,3,1,white,blue,3,613f58e1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational"
	  Ports			  [2, 1]
	  Position		  [1060, 231, 1100, 289]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational1"
	  Ports			  [2, 1]
	  Position		  [1005, 431, 1050, 469]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a>b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[16 1 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,38,2,1,white,blue,0,064af3a6,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational2"
	  Ports			  [2, 1]
	  Position		  [985, 651, 1025, 709]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch1"
	  Ports			  [2, 1]
	  Position		  [665, 272, 705, 343]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch1"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch2"
	  Ports			  [2, 1]
	  Position		  [1285, 245, 1325, 305]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch2"
	    Location		    [521, 318, 918, 591]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch3"
	  Ports			  [2, 1]
	  Position		  [665, 167, 705, 238]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch3"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  Scope
	  Name			  "Scope"
	  Ports			  [3]
	  Position		  [1530, 305, 1560, 405]
	  Floating		  off
	  Location		  [1, 45, 1441, 869]
	  Open			  off
	  NumInputPorts		  "3"
	  ZoomMode		  "xonly"
	  List {
	    ListType		    AxesTitles
	    axes1		    "%<SignalLabel>"
	    axes2		    "%<SignalLabel>"
	    axes3		    "%<SignalLabel>"
	  }
	  YMin			  "-5~-5~-5"
	  YMax			  "5~5~5"
	  DataFormat		  "StructureWithTime"
	  SampleTime		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux"
	  Ports			  [2, 1]
	  Position		  [405, 261, 445, 299]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux1"
	  Ports			  [2, 1]
	  Position		  [470, 576, 510, 614]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In"
	  Ports			  [1, 1]
	  Position		  [305, 260, 350, 280]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In"
	    Location		    [269, 280, 494, 362]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [86, 85, 144, 143]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In2"
	  Ports			  [1, 1]
	  Position		  [360, 575, 405, 595]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In2"
	    Location		    [214, 70, 1918, 1152]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [71, 110, 129, 168]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "negedge"
	  Ports			  [1, 1]
	  Position		  [495, 288, 525, 302]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "negedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [170, 213, 200, 227]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [230, 247, 290, 303]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [290, 191, 345, 249]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [410, 205, 465, 265]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [490, 228, 520, 242]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [90, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      DstBlock		      "Logical"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge"
	  Ports			  [1, 1]
	  Position		  [495, 273, 525, 287]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge2"
	  Ports			  [1, 1]
	  Position		  [495, 323, 525, 337]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge2"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "done"
	  Position		  [1350, 268, 1380, 282]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "running"
	  Position		  [1245, 518, 1275, 532]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "paused"
	  Position		  [1240, 463, 1270, 477]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "timeLeft"
	  Position		  [1285, 358, 1315, 372]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Line {
	  SrcBlock		  "mode"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Medium Idle"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "Convert1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical4"
	  SrcPort		  1
	  DstBlock		  "paused"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "start"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sim Mux"
	  SrcPort		  1
	  DstBlock		  "posedge"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "AddSub"
	  SrcPort		  1
	  DstBlock		  "timeLeft"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "Relational1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational1"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Inverter"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "S-R_Latch1"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    Points		    [0, 175]
	    Branch {
	      Points		      [0, 235]
	      DstBlock		      "Counter1"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [290, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, 40]
		DstBlock		"running"
		DstPort			1
	      }
	    }
	  }
	  Branch {
	    Points		    [0, -20]
	    DstBlock		    "Logical6"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "slotCount"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    Points		    [0, 105]
	    DstBlock		    "AddSub"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Relational"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Counter"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "Relational"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 100]
	    Branch {
	      DstBlock		      "AddSub"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [0, 30]
	      Branch {
		Points			[0, 35]
		DstBlock		"Relational1"
		DstPort			1
	      }
	      Branch {
		Points			[445, 0; 0, -85]
		DstBlock		"Scope"
		DstPort			1
	      }
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical1"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S-R_Latch2"
	  SrcPort		  1
	  DstBlock		  "done"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Relational"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    Points		    [0, 110; -550, 0; 0, -40]
	    DstBlock		    "Logical2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -80; -290, 0; 0, 60]
	    DstBlock		    "Logical1"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Logical7"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "done_reset"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "S-R_Latch2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -145; -625, 0; 0, 75]
	    DstBlock		    "S-R_Latch3"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "posedge"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Logical3"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 400]
	    DstBlock		    "Logical5"
	    DstPort		    3
	  }
	  Branch {
	    Points		    [0, -25]
	    Branch {
	      DstBlock		      "Logical1"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [0, -70]
	      DstBlock		      "S-R_Latch3"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical3"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "negedge"
	  SrcPort		  1
	  DstBlock		  "Logical3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "pause"
	  SrcPort		  1
	  Points		  [115, 0]
	  Branch {
	    DstBlock		    "posedge2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, -35]
	    DstBlock		    "negedge"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "slotTime"
	  SrcPort		  1
	  DstBlock		  "Relational2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    DstBlock		    "Relational2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 35; 505, 0; 0, -340]
	    DstBlock		    "Scope"
	    DstPort		    3
	  }
	}
	Line {
	  SrcBlock		  "Logical5"
	  SrcPort		  1
	  DstBlock		  "Counter1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Relational2"
	  SrcPort		  1
	  Points		  [20, 0; 0, -60]
	  Branch {
	    Points		    [-295, 0]
	    Branch {
	      DstBlock		      "Logical5"
	      DstPort		      1
	    }
	    Branch {
	      Points		      [0, -320]
	      DstBlock		      "Logical6"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Points		    [380, 0; 0, -265]
	    DstBlock		    "Scope"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Inverter1"
	  SrcPort		  1
	  DstBlock		  "Logical5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical6"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Convert1"
	  SrcPort		  1
	  Points		  [25, 0; 0, -75]
	  DstBlock		  "Sim Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sim Mux1"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    DstBlock		    "Inverter1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [260, 0; 0, -250]
	    Branch {
	      DstBlock		      "Logical6"
	      DstPort		      3
	    }
	    Branch {
	      DstBlock		      "Delay"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "posedge2"
	  SrcPort		  1
	  Points		  [25, 0; 0, -15]
	  DstBlock		  "Logical2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical2"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In2"
	  SrcPort		  1
	  DstBlock		  "Sim Mux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical7"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S-R_Latch3"
	  SrcPort		  1
	  Points		  [70, 0; 0, -50; 350, 0; 0, 95]
	  DstBlock		  "Logical7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  Points		  [195, 0; 0, -75]
	  DstBlock		  "Logical7"
	  DstPort		  3
	}
	Annotation {
	  Name			  "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount to 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until the next user-initiated start."
	  Position		  [697, 92]
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Timer 5"
      Ports		      [7, 4]
      Position		      [855, 205, 960, 325]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Timer 5"
	Location		[214, 74, 1910, 1156]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "start"
	  Position		  [310, 283, 340, 297]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "pause"
	  Position		  [310, 323, 340, 337]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "mode"
	  Position		  [255, 648, 285, 662]
	  NamePlacement		  "alternate"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "done_reset"
	  Position		  [1175, 283, 1205, 297]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotCount"
	  Position		  [980, 238, 1010, 252]
	  NamePlacement		  "alternate"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotTime"
	  Position		  [930, 658, 960, 672]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "Medium Idle"
	  Position		  [250, 698, 280, 712]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AddSub"
	  Ports			  [2, 1]
	  Position		  [1210, 339, 1255, 386]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/AddSub"
	  SourceType		  "Xilinx Adder/Subtractor Block"
	  mode			  "Subtraction"
	  use_carryin		  off
	  use_carryout		  off
	  en			  off
	  latency		  "0"
	  precision		  "User Defined"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  pipelined		  off
	  use_rpm		  on
	  hw_selection		  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[16 0 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "addsub"
	  block_version		  "8.2"
	  sg_icon_stat		  "45,47,2,1,white,blue,0,46b4c804,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [940, 454, 970, 466]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "32"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "50,50,400,346"
	  block_type		  "constant"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "30,12,0,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  Ports			  [0, 1]
	  Position		  [255, 672, 290, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "1"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,16,0,1,white,blue,0,06094819,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [260, 261, 275, 279]
	  ShowName		  off
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [315, 576, 330, 594]
	  ShowName		  off
	  Value			  "0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Convert1"
	  Ports			  [1, 1]
	  Position		  [380, 670, 415, 690]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Convert"
	  SourceType		  "Xilinx Type Converter Block"
	  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  latency		  "0"
	  dbl_ovrd		  off
	  pipeline		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,461,375"
	  block_type		  "convert"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,20,1,1,white,blue,0,74901e60,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter"
	  Ports			  [2, 1]
	  Position		  [905, 224, 965, 326]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter1"
	  Ports			  [2, 1]
	  Position		  [835, 644, 895, 746]
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [1, 1]
	  Position		  [925, 331, 950, 359]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Delay"
	  SourceType		  "Xilinx Delay Block"
	  infoedit		  "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  reg_retiming		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "delay"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "25,28,1,1,white,blue,0,fc531c0e,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 24 18 13 9 14 9 13 18 24 17 15 13 6 ],[4 8 14 20 24 24 22 24 24 18 23 19 14 9 5 10 4 4 6 4 4 ],[0.98 0.96 0.92]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter"
	  Ports			  [1, 1]
	  Position		  [1080, 476, 1125, 494]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter1"
	  Ports			  [1, 1]
	  Position		  [590, 661, 635, 679]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical1"
	  Ports			  [2, 1]
	  Position		  [855, 231, 885, 264]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical2"
	  Ports			  [2, 1]
	  Position		  [590, 306, 620, 339]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical3"
	  Ports			  [2, 1]
	  Position		  [590, 271, 620, 304]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical4"
	  Ports			  [2, 1]
	  Position		  [1155, 433, 1200, 502]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,69,2,1,white,blue,0,087b5522,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical5"
	  Ports			  [3, 1]
	  Position		  [770, 652, 805, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,bd50cad4,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical6"
	  Ports			  [3, 1]
	  Position		  [850, 282, 885, 318]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical7"
	  Ports			  [3, 1]
	  Position		  [1175, 243, 1205, 277]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,34,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 34 34 ],[0.77 0.82 0.91]);\npatch([7 2 9 2 7 15 17 19 27 20 14 9 15 9 14 20 27 19 17 15 7 ],[5 10 17 24 29 29 27 29 29 22 28 23 17 11 6 12 5 5 7 5 5 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Mux"
	  Ports			  [3, 1]
	  Position		  [320, 643, 345, 717]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Mux"
	  SourceType		  "Xilinx Bus Multiplexer Block"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mux"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,74,3,1,white,blue,3,613f58e1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational"
	  Ports			  [2, 1]
	  Position		  [1060, 231, 1100, 289]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational1"
	  Ports			  [2, 1]
	  Position		  [1005, 431, 1050, 469]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a>b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[16 1 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,38,2,1,white,blue,0,064af3a6,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational2"
	  Ports			  [2, 1]
	  Position		  [985, 651, 1025, 709]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch1"
	  Ports			  [2, 1]
	  Position		  [665, 272, 705, 343]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch1"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch2"
	  Ports			  [2, 1]
	  Position		  [1285, 245, 1325, 305]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch2"
	    Location		    [521, 318, 918, 591]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch3"
	  Ports			  [2, 1]
	  Position		  [665, 167, 705, 238]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch3"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  Scope
	  Name			  "Scope"
	  Ports			  [3]
	  Position		  [1530, 305, 1560, 405]
	  Floating		  off
	  Location		  [1, 45, 1441, 869]
	  Open			  off
	  NumInputPorts		  "3"
	  ZoomMode		  "xonly"
	  List {
	    ListType		    AxesTitles
	    axes1		    "%<SignalLabel>"
	    axes2		    "%<SignalLabel>"
	    axes3		    "%<SignalLabel>"
	  }
	  YMin			  "-5~-5~-5"
	  YMax			  "5~5~5"
	  DataFormat		  "StructureWithTime"
	  SampleTime		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux"
	  Ports			  [2, 1]
	  Position		  [405, 261, 445, 299]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux1"
	  Ports			  [2, 1]
	  Position		  [470, 576, 510, 614]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In"
	  Ports			  [1, 1]
	  Position		  [305, 260, 350, 280]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In"
	    Location		    [269, 280, 494, 362]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [86, 85, 144, 143]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In2"
	  Ports			  [1, 1]
	  Position		  [360, 575, 405, 595]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In2"
	    Location		    [214, 70, 1918, 1152]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [71, 110, 129, 168]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "negedge"
	  Ports			  [1, 1]
	  Position		  [495, 288, 525, 302]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "negedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [170, 213, 200, 227]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [230, 247, 290, 303]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [290, 191, 345, 249]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [410, 205, 465, 265]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [490, 228, 520, 242]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      DstBlock		      "Logical"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [90, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge"
	  Ports			  [1, 1]
	  Position		  [495, 273, 525, 287]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge2"
	  Ports			  [1, 1]
	  Position		  [495, 323, 525, 337]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge2"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "done"
	  Position		  [1350, 268, 1380, 282]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "running"
	  Position		  [1245, 518, 1275, 532]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "paused"
	  Position		  [1240, 463, 1270, 477]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "timeLeft"
	  Position		  [1285, 358, 1315, 372]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  Points		  [195, 0; 0, -75]
	  DstBlock		  "Logical7"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "S-R_Latch3"
	  SrcPort		  1
	  Points		  [70, 0; 0, -50; 350, 0; 0, 95]
	  DstBlock		  "Logical7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical7"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In2"
	  SrcPort		  1
	  DstBlock		  "Sim Mux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical2"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "posedge2"
	  SrcPort		  1
	  Points		  [25, 0; 0, -15]
	  DstBlock		  "Logical2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim Mux1"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    Points		    [260, 0; 0, -250]
	    Branch {
	      DstBlock		      "Delay"
	      DstPort		      1
	    }
	    Branch {
	      DstBlock		      "Logical6"
	      DstPort		      3
	    }
	  }
	  Branch {
	    DstBlock		    "Inverter1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Convert1"
	  SrcPort		  1
	  Points		  [25, 0; 0, -75]
	  DstBlock		  "Sim Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical6"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Inverter1"
	  SrcPort		  1
	  DstBlock		  "Logical5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational2"
	  SrcPort		  1
	  Points		  [20, 0; 0, -60]
	  Branch {
	    Points		    [380, 0; 0, -265]
	    DstBlock		    "Scope"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [-295, 0]
	    Branch {
	      Points		      [0, -320]
	      DstBlock		      "Logical6"
	      DstPort		      2
	    }
	    Branch {
	      DstBlock		      "Logical5"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical5"
	  SrcPort		  1
	  DstBlock		  "Counter1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    Points		    [0, 35; 505, 0; 0, -340]
	    DstBlock		    "Scope"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "Relational2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "slotTime"
	  SrcPort		  1
	  DstBlock		  "Relational2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "pause"
	  SrcPort		  1
	  Points		  [115, 0]
	  Branch {
	    Points		    [0, -35]
	    DstBlock		    "negedge"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "posedge2"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "negedge"
	  SrcPort		  1
	  DstBlock		  "Logical3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical3"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "posedge"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -25]
	    Branch {
	      Points		      [0, -70]
	      DstBlock		      "S-R_Latch3"
	      DstPort		      1
	    }
	    Branch {
	      DstBlock		      "Logical1"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Points		    [0, 400]
	    DstBlock		    "Logical5"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "Logical3"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "done_reset"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -145; -625, 0; 0, 75]
	    DstBlock		    "S-R_Latch3"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "S-R_Latch2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Relational"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    DstBlock		    "Logical7"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -80; -290, 0; 0, 60]
	    DstBlock		    "Logical1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110; -550, 0; 0, -40]
	    DstBlock		    "Logical2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "S-R_Latch2"
	  SrcPort		  1
	  DstBlock		  "done"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical1"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Points		    [0, 100]
	    Branch {
	      Points		      [0, 30]
	      Branch {
		Points			[445, 0; 0, -85]
		DstBlock		"Scope"
		DstPort			1
	      }
	      Branch {
		Points			[0, 35]
		DstBlock		"Relational1"
		DstPort			1
	      }
	    }
	    Branch {
	      DstBlock		      "AddSub"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "Relational"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "slotCount"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    DstBlock		    "Relational"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 105]
	    DstBlock		    "AddSub"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "S-R_Latch1"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    Points		    [0, -20]
	    DstBlock		    "Logical6"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 175]
	    Branch {
	      Points		      [290, 0]
	      Branch {
		Points			[0, 40]
		DstBlock		"running"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	    Branch {
	      Points		      [0, 235]
	      DstBlock		      "Counter1"
	      DstPort		      2
	    }
	  }
	}
	Line {
	  SrcBlock		  "Inverter"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational1"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "Relational1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "AddSub"
	  SrcPort		  1
	  DstBlock		  "timeLeft"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim Mux"
	  SrcPort		  1
	  DstBlock		  "posedge"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "start"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical4"
	  SrcPort		  1
	  DstBlock		  "paused"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "Convert1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Medium Idle"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "mode"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Annotation {
	  Name			  "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount to 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until the next user-initiated start."
	  Position		  [697, 92]
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Timer 6"
      Ports		      [7, 4]
      Position		      [860, 340, 965, 460]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Timer 6"
	Location		[214, 74, 1910, 1156]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "start"
	  Position		  [310, 283, 340, 297]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "pause"
	  Position		  [310, 323, 340, 337]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "mode"
	  Position		  [255, 648, 285, 662]
	  NamePlacement		  "alternate"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "done_reset"
	  Position		  [1175, 283, 1205, 297]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotCount"
	  Position		  [980, 238, 1010, 252]
	  NamePlacement		  "alternate"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotTime"
	  Position		  [930, 658, 960, 672]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "Medium Idle"
	  Position		  [250, 698, 280, 712]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AddSub"
	  Ports			  [2, 1]
	  Position		  [1210, 339, 1255, 386]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/AddSub"
	  SourceType		  "Xilinx Adder/Subtractor Block"
	  mode			  "Subtraction"
	  use_carryin		  off
	  use_carryout		  off
	  en			  off
	  latency		  "0"
	  precision		  "User Defined"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  pipelined		  off
	  use_rpm		  on
	  hw_selection		  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[16 0 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "addsub"
	  block_version		  "8.2"
	  sg_icon_stat		  "45,47,2,1,white,blue,0,46b4c804,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [940, 454, 970, 466]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "32"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "50,50,400,346"
	  block_type		  "constant"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "30,12,0,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  Ports			  [0, 1]
	  Position		  [255, 672, 290, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "1"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,16,0,1,white,blue,0,06094819,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [260, 261, 275, 279]
	  ShowName		  off
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [315, 576, 330, 594]
	  ShowName		  off
	  Value			  "0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Convert1"
	  Ports			  [1, 1]
	  Position		  [380, 670, 415, 690]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Convert"
	  SourceType		  "Xilinx Type Converter Block"
	  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  latency		  "0"
	  dbl_ovrd		  off
	  pipeline		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,461,375"
	  block_type		  "convert"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,20,1,1,white,blue,0,74901e60,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter"
	  Ports			  [2, 1]
	  Position		  [905, 224, 965, 326]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter1"
	  Ports			  [2, 1]
	  Position		  [835, 644, 895, 746]
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [1, 1]
	  Position		  [925, 331, 950, 359]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Delay"
	  SourceType		  "Xilinx Delay Block"
	  infoedit		  "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  reg_retiming		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "delay"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "25,28,1,1,white,blue,0,fc531c0e,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 24 18 13 9 14 9 13 18 24 17 15 13 6 ],[4 8 14 20 24 24 22 24 24 18 23 19 14 9 5 10 4 4 6 4 4 ],[0.98 0.96 0.92]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter"
	  Ports			  [1, 1]
	  Position		  [1080, 476, 1125, 494]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter1"
	  Ports			  [1, 1]
	  Position		  [590, 661, 635, 679]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical1"
	  Ports			  [2, 1]
	  Position		  [855, 231, 885, 264]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical2"
	  Ports			  [2, 1]
	  Position		  [590, 306, 620, 339]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical3"
	  Ports			  [2, 1]
	  Position		  [590, 271, 620, 304]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical4"
	  Ports			  [2, 1]
	  Position		  [1155, 433, 1200, 502]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,69,2,1,white,blue,0,087b5522,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical5"
	  Ports			  [3, 1]
	  Position		  [770, 652, 805, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,bd50cad4,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical6"
	  Ports			  [3, 1]
	  Position		  [850, 282, 885, 318]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical7"
	  Ports			  [3, 1]
	  Position		  [1175, 243, 1205, 277]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,34,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 34 34 ],[0.77 0.82 0.91]);\npatch([7 2 9 2 7 15 17 19 27 20 14 9 15 9 14 20 27 19 17 15 7 ],[5 10 17 24 29 29 27 29 29 22 28 23 17 11 6 12 5 5 7 5 5 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Mux"
	  Ports			  [3, 1]
	  Position		  [320, 643, 345, 717]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Mux"
	  SourceType		  "Xilinx Bus Multiplexer Block"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mux"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,74,3,1,white,blue,3,613f58e1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational"
	  Ports			  [2, 1]
	  Position		  [1060, 231, 1100, 289]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational1"
	  Ports			  [2, 1]
	  Position		  [1005, 431, 1050, 469]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a>b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[16 1 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,38,2,1,white,blue,0,064af3a6,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational2"
	  Ports			  [2, 1]
	  Position		  [985, 651, 1025, 709]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch1"
	  Ports			  [2, 1]
	  Position		  [665, 272, 705, 343]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch1"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch2"
	  Ports			  [2, 1]
	  Position		  [1285, 245, 1325, 305]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch2"
	    Location		    [521, 318, 918, 591]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch3"
	  Ports			  [2, 1]
	  Position		  [665, 167, 705, 238]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch3"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  Scope
	  Name			  "Scope"
	  Ports			  [3]
	  Position		  [1530, 305, 1560, 405]
	  Floating		  off
	  Location		  [1, 45, 1441, 869]
	  Open			  off
	  NumInputPorts		  "3"
	  ZoomMode		  "xonly"
	  List {
	    ListType		    AxesTitles
	    axes1		    "%<SignalLabel>"
	    axes2		    "%<SignalLabel>"
	    axes3		    "%<SignalLabel>"
	  }
	  YMin			  "-5~-5~-5"
	  YMax			  "5~5~5"
	  DataFormat		  "StructureWithTime"
	  SampleTime		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux"
	  Ports			  [2, 1]
	  Position		  [405, 261, 445, 299]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux1"
	  Ports			  [2, 1]
	  Position		  [470, 576, 510, 614]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In"
	  Ports			  [1, 1]
	  Position		  [305, 260, 350, 280]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In"
	    Location		    [269, 280, 494, 362]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [86, 85, 144, 143]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In2"
	  Ports			  [1, 1]
	  Position		  [360, 575, 405, 595]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In2"
	    Location		    [214, 70, 1918, 1152]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [71, 110, 129, 168]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "negedge"
	  Ports			  [1, 1]
	  Position		  [495, 288, 525, 302]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "negedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [170, 213, 200, 227]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [230, 247, 290, 303]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [290, 191, 345, 249]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [410, 205, 465, 265]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [490, 228, 520, 242]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [90, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      DstBlock		      "Logical"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge"
	  Ports			  [1, 1]
	  Position		  [495, 273, 525, 287]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge2"
	  Ports			  [1, 1]
	  Position		  [495, 323, 525, 337]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge2"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "done"
	  Position		  [1350, 268, 1380, 282]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "running"
	  Position		  [1245, 518, 1275, 532]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "paused"
	  Position		  [1240, 463, 1270, 477]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "timeLeft"
	  Position		  [1285, 358, 1315, 372]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Line {
	  SrcBlock		  "mode"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Medium Idle"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "Convert1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical4"
	  SrcPort		  1
	  DstBlock		  "paused"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "start"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sim Mux"
	  SrcPort		  1
	  DstBlock		  "posedge"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "AddSub"
	  SrcPort		  1
	  DstBlock		  "timeLeft"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "Relational1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational1"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Inverter"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "S-R_Latch1"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    Points		    [0, 175]
	    Branch {
	      Points		      [0, 235]
	      DstBlock		      "Counter1"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [290, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, 40]
		DstBlock		"running"
		DstPort			1
	      }
	    }
	  }
	  Branch {
	    Points		    [0, -20]
	    DstBlock		    "Logical6"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "slotCount"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    Points		    [0, 105]
	    DstBlock		    "AddSub"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Relational"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Counter"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "Relational"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 100]
	    Branch {
	      DstBlock		      "AddSub"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [0, 30]
	      Branch {
		Points			[0, 35]
		DstBlock		"Relational1"
		DstPort			1
	      }
	      Branch {
		Points			[445, 0; 0, -85]
		DstBlock		"Scope"
		DstPort			1
	      }
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical1"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S-R_Latch2"
	  SrcPort		  1
	  DstBlock		  "done"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Relational"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    Points		    [0, 110; -550, 0; 0, -40]
	    DstBlock		    "Logical2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -80; -290, 0; 0, 60]
	    DstBlock		    "Logical1"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Logical7"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "done_reset"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "S-R_Latch2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -145; -625, 0; 0, 75]
	    DstBlock		    "S-R_Latch3"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "posedge"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Logical3"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 400]
	    DstBlock		    "Logical5"
	    DstPort		    3
	  }
	  Branch {
	    Points		    [0, -25]
	    Branch {
	      DstBlock		      "Logical1"
	      DstPort		      2
	    }
	    Branch {
	      Points		      [0, -70]
	      DstBlock		      "S-R_Latch3"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical3"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "negedge"
	  SrcPort		  1
	  DstBlock		  "Logical3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "pause"
	  SrcPort		  1
	  Points		  [115, 0]
	  Branch {
	    DstBlock		    "posedge2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, -35]
	    DstBlock		    "negedge"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "slotTime"
	  SrcPort		  1
	  DstBlock		  "Relational2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    DstBlock		    "Relational2"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 35; 505, 0; 0, -340]
	    DstBlock		    "Scope"
	    DstPort		    3
	  }
	}
	Line {
	  SrcBlock		  "Logical5"
	  SrcPort		  1
	  DstBlock		  "Counter1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Relational2"
	  SrcPort		  1
	  Points		  [20, 0; 0, -60]
	  Branch {
	    Points		    [-295, 0]
	    Branch {
	      DstBlock		      "Logical5"
	      DstPort		      1
	    }
	    Branch {
	      Points		      [0, -320]
	      DstBlock		      "Logical6"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Points		    [380, 0; 0, -265]
	    DstBlock		    "Scope"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Inverter1"
	  SrcPort		  1
	  DstBlock		  "Logical5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical6"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Convert1"
	  SrcPort		  1
	  Points		  [25, 0; 0, -75]
	  DstBlock		  "Sim Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sim Mux1"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    DstBlock		    "Inverter1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [260, 0; 0, -250]
	    Branch {
	      DstBlock		      "Logical6"
	      DstPort		      3
	    }
	    Branch {
	      DstBlock		      "Delay"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "posedge2"
	  SrcPort		  1
	  Points		  [25, 0; 0, -15]
	  DstBlock		  "Logical2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical2"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In2"
	  SrcPort		  1
	  DstBlock		  "Sim Mux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical7"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S-R_Latch3"
	  SrcPort		  1
	  Points		  [70, 0; 0, -50; 350, 0; 0, 95]
	  DstBlock		  "Logical7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  Points		  [195, 0; 0, -75]
	  DstBlock		  "Logical7"
	  DstPort		  3
	}
	Annotation {
	  Name			  "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount to 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until the next user-initiated start."
	  Position		  [697, 92]
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Timer 7"
      Ports		      [7, 4]
      Position		      [860, 480, 965, 600]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Timer 7"
	Location		[214, 74, 1910, 1156]
	Open			off
	ModelBrowserVisibility	on
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "start"
	  Position		  [310, 283, 340, 297]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "pause"
	  Position		  [310, 323, 340, 337]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "mode"
	  Position		  [255, 648, 285, 662]
	  NamePlacement		  "alternate"
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "done_reset"
	  Position		  [1175, 283, 1205, 297]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotCount"
	  Position		  [980, 238, 1010, 252]
	  NamePlacement		  "alternate"
	  Port			  "5"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "slotTime"
	  Position		  [930, 658, 960, 672]
	  Port			  "6"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Inport
	  Name			  "Medium Idle"
	  Position		  [250, 698, 280, 712]
	  Port			  "7"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "AddSub"
	  Ports			  [2, 1]
	  Position		  [1210, 339, 1255, 386]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/AddSub"
	  SourceType		  "Xilinx Adder/Subtractor Block"
	  mode			  "Subtraction"
	  use_carryin		  off
	  use_carryout		  off
	  en			  off
	  latency		  "0"
	  precision		  "User Defined"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  pipelined		  off
	  use_rpm		  on
	  hw_selection		  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[16 0 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "addsub"
	  block_version		  "8.2"
	  sg_icon_stat		  "45,47,2,1,white,blue,0,46b4c804,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant"
	  Ports			  [0, 1]
	  Position		  [940, 454, 970, 466]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "0"
	  n_bits		  "32"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "50,50,400,346"
	  block_type		  "constant"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "30,12,0,1,white,blue,0,72d575a1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  Ports			  [0, 1]
	  Position		  [255, 672, 290, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  arith_type		  "Unsigned"
	  const			  "1"
	  n_bits		  "1"
	  bin_pt		  "0"
	  explicit_period	  off
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,16,0,1,white,blue,0,06094819,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  Position		  [260, 261, 275, 279]
	  ShowName		  off
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  Position		  [315, 576, 330, 594]
	  ShowName		  off
	  Value			  "0"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Convert1"
	  Ports			  [1, 1]
	  Position		  [380, 670, 415, 690]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Convert"
	  SourceType		  "Xilinx Type Converter Block"
	  infoedit		  "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not."
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  latency		  "0"
	  dbl_ovrd		  off
	  pipeline		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,461,375"
	  block_type		  "convert"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,20,1,1,white,blue,0,74901e60,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter"
	  Ports			  [2, 1]
	  Position		  [905, 224, 965, 326]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Counter1"
	  Ports			  [2, 1]
	  Position		  [835, 644, 895, 746]
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "Inf"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  on
	  explicit_period	  "on"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  use_rpm		  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[17 32 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,356,630"
	  block_type		  "counter"
	  block_version		  "8.2"
	  sg_icon_stat		  "60,102,2,1,white,blue,0,46c73e85,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [1, 1]
	  Position		  [925, 331, 950, 359]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Delay"
	  SourceType		  "Xilinx Delay Block"
	  infoedit		  "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  reg_retiming		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "delay"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "25,28,1,1,white,blue,0,fc531c0e,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([6 2 8 2 6 13 15 17 24 18 13 9 14 9 13 18 24 17 15 13 6 ],[4 8 14 20 24 24 22 24 24 18 23 19 14 9 5 10 4 4 6 4 4 ],[0.98 0.96 0.92]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter"
	  Ports			  [1, 1]
	  Position		  [1080, 476, 1125, 494]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter1"
	  Ports			  [1, 1]
	  Position		  [590, 661, 635, 679]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,18,1,1,white,blue,0,1ab4a85f,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical1"
	  Ports			  [2, 1]
	  Position		  [855, 231, 885, 264]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical2"
	  Ports			  [2, 1]
	  Position		  [590, 306, 620, 339]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical3"
	  Ports			  [2, 1]
	  Position		  [590, 271, 620, 304]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,33,2,1,white,blue,0,f4a65842,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical4"
	  Ports			  [2, 1]
	  Position		  [1155, 433, 1200, 502]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,69,2,1,white,blue,0,087b5522,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical5"
	  Ports			  [3, 1]
	  Position		  [770, 652, 805, 688]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "OR"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,bd50cad4,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical6"
	  Ports			  [3, 1]
	  Position		  [850, 282, 885, 318]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "8.2"
	  sg_icon_stat		  "35,36,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical7"
	  Ports			  [3, 1]
	  Position		  [1175, 243, 1205, 277]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "3"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "0"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,261"
	  block_type		  "logical"
	  block_version		  "9.1.01"
	  sg_icon_stat		  "30,34,3,1,white,blue,0,5c2bfaa2,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 34 34 ],[0.77 0.82 0.91]);\npatch([7 2 9 2 7 15 17 19 27 20 14 9 15 9 14 20 27 19 17 15 7 ],[5 10 17 24 29 29 27 29 29 22 28 23 17 11 6 12 5 5 7 5 5 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Mux"
	  Ports			  [3, 1]
	  Position		  [320, 643, 345, 717]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Mux"
	  SourceType		  "Xilinx Bus Multiplexer Block"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "16"
	  bin_pt		  "14"
	  quantization		  "Truncate"
	  overflow		  "Wrap"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "mux"
	  block_version		  "8.2"
	  sg_icon_stat		  "25,74,3,1,white,blue,3,613f58e1,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational"
	  Ports			  [2, 1]
	  Position		  [1060, 231, 1100, 289]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational1"
	  Ports			  [2, 1]
	  Position		  [1005, 431, 1050, 469]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a>b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[16 1 0 32 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "10.1.2"
	  sg_icon_stat		  "45,38,2,1,white,blue,0,064af3a6,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational2"
	  Ports			  [2, 1]
	  Position		  [985, 651, 1025, 709]
	  ShowName		  off
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a<=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[8 0 0 16 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,348,193"
	  block_type		  "relational"
	  block_version		  "8.2"
	  sg_icon_stat		  "40,58,2,1,white,blue,0,07808d72,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch1"
	  Ports			  [2, 1]
	  Position		  [665, 272, 705, 343]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch1"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch2"
	  Ports			  [2, 1]
	  Position		  [1285, 245, 1325, 305]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch2"
	    Location		    [521, 318, 918, 591]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "S-R_Latch3"
	  Ports			  [2, 1]
	  Position		  [665, 167, 705, 238]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "S-R_Latch3"
	    Location		    [202, 70, 1438, 850]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "S"
	      Position		      [95, 58, 125, 72]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "R"
	      Position		      [95, 88, 125, 102]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [220, 82, 250, 108]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "30,26,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Register"
	      Ports		      [3, 1]
	      Position		      [150, 70, 195, 120]
	      SourceBlock	      "xbsIndex_r4/Register"
	      SourceType	      "Xilinx Register Block"
	      init		      "0"
	      rst		      "on"
	      en		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,193"
	      block_type	      "register"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "45,50,1,1,white,blue,0,923c1847,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [285, 63, 315, 77]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "R"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "S"
	      SrcPort		      1
	      DstBlock		      "Register"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [10, 0; 0, 55; -130, 0]
	      DstBlock		      "Register"
	      DstPort		      3
	    }
	    Line {
	      SrcBlock		      "Register"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, -25]
		DstBlock		"Q"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	  }
	}
	Block {
	  BlockType		  Scope
	  Name			  "Scope"
	  Ports			  [3]
	  Position		  [1530, 305, 1560, 405]
	  Floating		  off
	  Location		  [1, 45, 1441, 869]
	  Open			  off
	  NumInputPorts		  "3"
	  ZoomMode		  "xonly"
	  List {
	    ListType		    AxesTitles
	    axes1		    "%<SignalLabel>"
	    axes2		    "%<SignalLabel>"
	    axes3		    "%<SignalLabel>"
	  }
	  YMin			  "-5~-5~-5"
	  YMax			  "5~5~5"
	  DataFormat		  "StructureWithTime"
	  SampleTime		  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux"
	  Ports			  [2, 1]
	  Position		  [405, 261, 445, 299]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Sim Mux1"
	  Ports			  [2, 1]
	  Position		  [470, 576, 510, 614]
	  NamePlacement		  "alternate"
	  SourceBlock		  "xbsIndex_r4/Simulation Multiplexer"
	  SourceType		  "Xilinx Simulation Multiplexer Block"
	  infoedit		  "Distinguish input subsystems as \"simulation only\" and \"generation only\".  The input specified For Simulation will be used during Simulink simulation.  The input specified For Generation will be used during code generation.  This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem.<P><P>Hardware Notes: This block costs nothing."
	  sim_sel		  "1"
	  hw_sel		  "2"
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,336,197"
	  block_type		  "simmux"
	  block_version		  "10.1.3"
	  sg_icon_stat		  "40,38,2,1,white,blue,0,c4f98ccb,right"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');\ncolor('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In"
	  Ports			  [1, 1]
	  Position		  [305, 260, 350, 280]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In"
	    Location		    [269, 280, 494, 362]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [86, 85, 144, 143]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sim-only\nGateway In2"
	  Ports			  [1, 1]
	  Position		  [360, 575, 405, 595]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Sim-only\nGateway In2"
	    Location		    [214, 70, 1918, 1152]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "D"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Disregard Subsystem"
	      Tag		      "discardX"
	      Ports		      []
	      Position		      [71, 110, 129, 168]
	      ShowName		      off
	      AttributesFormatString  "Disregard Subsystem\\nFor Generation"
	      SourceBlock	      "xbsIndex_r4/Disregard Subsystem"
	      SourceType	      "Xilinx Disregard Subsystem For Generation Block"
	      infoedit		      "Place this block into a subsystem to have System Generator ignore the subsystem during code generation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulation model for another subsystem (e.g., to provide a simulation model for a black box)."
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "disregard"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "58,58,-1,-1,darkgray,black,0,0,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0.1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Gateway In"
	      Ports		      [1, 1]
	      Position		      [80, 30, 145, 50]
	      SourceBlock	      "xbsIndex_r4/Gateway In"
	      SourceType	      "Xilinx Gateway In Block"
	      infoedit		      "Gateway in block.  Converts inputs of type Simulink integer, double and fixed point to  Xilinx fixed point type.<P><P>Hardware notes:  In hardware these blocks become top level input ports."
	      arith_type	      "Boolean"
	      n_bits		      "1"
	      bin_pt		      "0"
	      quantization	      "Round  (unbiased: +/- Inf)"
	      overflow		      "Saturate"
	      period		      "1"
	      dbl_ovrd		      "off"
	      timing_constraint	      "None"
	      locs_specified	      "off"
	      LOCs		      "{}"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 1 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,348,406"
	      block_type	      "gatewayin"
	      block_version	      "10.1.3"
	      sg_icon_stat	      "65,20,1,1,white,yellow,0,bc55d28f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Q"
	      Position		      [170, 33, 200, 47]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "D"
	      SrcPort		      1
	      DstBlock		      "Gateway In"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Gateway In"
	      SrcPort		      1
	      DstBlock		      "Q"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "negedge"
	  Ports			  [1, 1]
	  Position		  [495, 288, 525, 302]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "negedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [170, 213, 200, 227]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [230, 247, 290, 303]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [290, 191, 345, 249]
	      NamePlacement	      "alternate"
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [410, 205, 465, 265]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [490, 228, 520, 242]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      DstBlock		      "Logical"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [90, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [5, 0]
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge"
	  Ports			  [1, 1]
	  Position		  [495, 273, 525, 287]
	  NamePlacement		  "alternate"
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "posedge2"
	  Ports			  [1, 1]
	  Position		  [495, 323, 525, 337]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "posedge2"
	    Location		    [459, 339, 854, 490]
	    Open		    off
	    ModelBrowserVisibility  on
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [20, 33, 50, 47]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Delay"
	      Ports		      [1, 1]
	      Position		      [80, 67, 140, 123]
	      SourceBlock	      "xbsIndex_r4/Delay"
	      SourceType	      "Xilinx Delay Block"
	      infoedit		      "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops."
	      en		      "off"
	      latency		      "1"
	      dbl_ovrd		      "off"
	      reg_retiming	      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 1 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "delay"
	      block_version	      "8.2"
	      sg_icon_stat	      "60,56,1,1,white,blue,0,fc531c0e,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Inverter"
	      Ports		      [1, 1]
	      Position		      [170, 66, 225, 124]
	      SourceBlock	      "xbsIndex_r4/Inverter"
	      SourceType	      "Xilinx Inverter Block"
	      infoedit		      "Bitwise logical negation (one's complement) operator."
	      en		      "off"
	      latency		      "0"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[0 0 0 0 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "inv"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,58,1,1,white,blue,0,1ab4a85f,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Logical"
	      Ports		      [2, 1]
	      Position		      [260, 25, 315, 85]
	      SourceBlock	      "xbsIndex_r4/Logical"
	      SourceType	      "Xilinx Logical Block Block"
	      logical_function	      "AND"
	      inputs		      "2"
	      en		      "off"
	      latency		      "0"
	      precision		      "Full"
	      arith_type	      "Unsigned"
	      n_bits		      "16"
	      bin_pt		      "0"
	      align_bp		      "on"
	      dbl_ovrd		      "off"
	      xl_use_area	      "off"
	      xl_area		      "[1 0 0 1 0 0 0]"
	      has_advanced_control    "0"
	      sggui_pos		      "-1,-1,-1,-1"
	      block_type	      "logical"
	      block_version	      "8.2"
	      sg_icon_stat	      "55,60,1,1,white,blue,0,087b5522,right"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out"
	      Position		      [340, 48, 370, 62]
	      IconDisplay	      "Port number"
	      OutDataType	      "sfix(16)"
	      OutScaling	      "2^0"
	    }
	    Line {
	      SrcBlock		      "Logical"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Out"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      Points		      [0, 0; 5, 0]
	      Branch {
		Points			[0, 55]
		DstBlock		"Delay"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Logical"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Inverter"
	      SrcPort		      1
	      Points		      [5, 0; 0, -25]
	      DstBlock		      "Logical"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Delay"
	      SrcPort		      1
	      Points		      [0, 0]
	      DstBlock		      "Inverter"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "done"
	  Position		  [1350, 268, 1380, 282]
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "running"
	  Position		  [1245, 518, 1275, 532]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "paused"
	  Position		  [1240, 463, 1270, 477]
	  Port			  "3"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Block {
	  BlockType		  Outport
	  Name			  "timeLeft"
	  Position		  [1285, 358, 1315, 372]
	  Port			  "4"
	  IconDisplay		  "Port number"
	  OutDataType		  "sfix(16)"
	  OutScaling		  "2^0"
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  Points		  [195, 0; 0, -75]
	  DstBlock		  "Logical7"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "S-R_Latch3"
	  SrcPort		  1
	  Points		  [70, 0; 0, -50; 350, 0; 0, 95]
	  DstBlock		  "Logical7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical7"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In2"
	  SrcPort		  1
	  DstBlock		  "Sim Mux1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical2"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "posedge2"
	  SrcPort		  1
	  Points		  [25, 0; 0, -15]
	  DstBlock		  "Logical2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "Sim-only\nGateway In"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim Mux1"
	  SrcPort		  1
	  Points		  [60, 0]
	  Branch {
	    Points		    [260, 0; 0, -250]
	    Branch {
	      DstBlock		      "Delay"
	      DstPort		      1
	    }
	    Branch {
	      DstBlock		      "Logical6"
	      DstPort		      3
	    }
	  }
	  Branch {
	    DstBlock		    "Inverter1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Convert1"
	  SrcPort		  1
	  Points		  [25, 0; 0, -75]
	  DstBlock		  "Sim Mux1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical6"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Inverter1"
	  SrcPort		  1
	  DstBlock		  "Logical5"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational2"
	  SrcPort		  1
	  Points		  [20, 0; 0, -60]
	  Branch {
	    Points		    [380, 0; 0, -265]
	    DstBlock		    "Scope"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [-295, 0]
	    Branch {
	      Points		      [0, -320]
	      DstBlock		      "Logical6"
	      DstPort		      2
	    }
	    Branch {
	      DstBlock		      "Logical5"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical5"
	  SrcPort		  1
	  DstBlock		  "Counter1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    Points		    [0, 35; 505, 0; 0, -340]
	    DstBlock		    "Scope"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "Relational2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "slotTime"
	  SrcPort		  1
	  DstBlock		  "Relational2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim-only\nGateway In"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "pause"
	  SrcPort		  1
	  Points		  [115, 0]
	  Branch {
	    Points		    [0, -35]
	    DstBlock		    "negedge"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "posedge2"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "negedge"
	  SrcPort		  1
	  DstBlock		  "Logical3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical3"
	  SrcPort		  1
	  DstBlock		  "S-R_Latch1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "posedge"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -25]
	    Branch {
	      Points		      [0, -70]
	      DstBlock		      "S-R_Latch3"
	      DstPort		      1
	    }
	    Branch {
	      DstBlock		      "Logical1"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Points		    [0, 400]
	    DstBlock		    "Logical5"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "Logical3"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "done_reset"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -145; -625, 0; 0, 75]
	    DstBlock		    "S-R_Latch3"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "S-R_Latch2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Relational"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    DstBlock		    "Logical7"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, -80; -290, 0; 0, 60]
	    DstBlock		    "Logical1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110; -550, 0; 0, -40]
	    DstBlock		    "Logical2"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "S-R_Latch2"
	  SrcPort		  1
	  DstBlock		  "done"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical1"
	  SrcPort		  1
	  DstBlock		  "Counter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Counter"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Points		    [0, 100]
	    Branch {
	      Points		      [0, 30]
	      Branch {
		Points			[445, 0; 0, -85]
		DstBlock		"Scope"
		DstPort			1
	      }
	      Branch {
		Points			[0, 35]
		DstBlock		"Relational1"
		DstPort			1
	      }
	    }
	    Branch {
	      DstBlock		      "AddSub"
	      DstPort		      2
	    }
	  }
	  Branch {
	    Labels		    [1, 0]
	    DstBlock		    "Relational"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "slotCount"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    DstBlock		    "Relational"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 105]
	    DstBlock		    "AddSub"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "S-R_Latch1"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    Points		    [0, -20]
	    DstBlock		    "Logical6"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 175]
	    Branch {
	      Points		      [290, 0]
	      Branch {
		Points			[0, 40]
		DstBlock		"running"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Inverter"
		DstPort			1
	      }
	    }
	    Branch {
	      Points		      [0, 235]
	      DstBlock		      "Counter1"
	      DstPort		      2
	    }
	  }
	}
	Line {
	  SrcBlock		  "Inverter"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational1"
	  SrcPort		  1
	  DstBlock		  "Logical4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "Relational1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "AddSub"
	  SrcPort		  1
	  DstBlock		  "timeLeft"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sim Mux"
	  SrcPort		  1
	  DstBlock		  "posedge"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "start"
	  SrcPort		  1
	  DstBlock		  "Sim Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical4"
	  SrcPort		  1
	  DstBlock		  "paused"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "Convert1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Medium Idle"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "mode"
	  SrcPort		  1
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Annotation {
	  Name			  "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount to 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until the next user-initiated start."
	  Position		  [697, 92]
	}
      }
    }
    Line {
      SrcBlock		      "Constant"
      SrcPort		      1
      DstBlock		      "IDLEFORDIFS"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From"
      SrcPort		      1
      DstBlock		      "Timer 0"
      DstPort		      4
    }
    Line {
      SrcBlock		      "From1"
      SrcPort		      1
      DstBlock		      "Timer 0"
      DstPort		      3
    }
    Line {
      SrcBlock		      "From2"
      SrcPort		      1
      DstBlock		      "Timer 0"
      DstPort		      2
    }
    Line {
      SrcBlock		      "From3"
      SrcPort		      1
      DstBlock		      "Timer 0"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From4"
      SrcPort		      1
      DstBlock		      "Timer 0"
      DstPort		      5
    }
    Line {
      SrcBlock		      "From5"
      SrcPort		      1
      DstBlock		      "Timer 0"
      DstPort		      6
    }
    Line {
      SrcBlock		      "From6"
      SrcPort		      1
      DstBlock		      "Timer 1"
      DstPort		      4
    }
    Line {
      SrcBlock		      "From7"
      SrcPort		      1
      DstBlock		      "Timer 1"
      DstPort		      3
    }
    Line {
      SrcBlock		      "From8"
      SrcPort		      1
      DstBlock		      "Timer 1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "From9"
      SrcPort		      1
      DstBlock		      "Timer 1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From10"
      SrcPort		      1
      DstBlock		      "Timer 1"
      DstPort		      5
    }
    Line {
      SrcBlock		      "From11"
      SrcPort		      1
      DstBlock		      "Timer 1"
      DstPort		      6
    }
    Line {
      SrcBlock		      "From14"
      SrcPort		      1
      DstBlock		      "Timer 2"
      DstPort		      4
    }
    Line {
      SrcBlock		      "From15"
      SrcPort		      1
      DstBlock		      "Timer 2"
      DstPort		      3
    }
    Line {
      SrcBlock		      "From16"
      SrcPort		      1
      DstBlock		      "Timer 2"
      DstPort		      2
    }
    Line {
      SrcBlock		      "From17"
      SrcPort		      1
      DstBlock		      "Timer 2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From12"
      SrcPort		      1
      DstBlock		      "Timer 2"
      DstPort		      5
    }
    Line {
      SrcBlock		      "From13"
      SrcPort		      1
      DstBlock		      "Timer 2"
      DstPort		      6
    }
    Line {
      SrcBlock		      "From20"
      SrcPort		      1
      DstBlock		      "Timer 3"
      DstPort		      4
    }
    Line {
      SrcBlock		      "From21"
      SrcPort		      1
      DstBlock		      "Timer 3"
      DstPort		      3
    }
    Line {
      SrcBlock		      "From22"
      SrcPort		      1
      DstBlock		      "Timer 3"
      DstPort		      2
    }
    Line {
      SrcBlock		      "From23"
      SrcPort		      1
      DstBlock		      "Timer 3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From18"
      SrcPort		      1
      DstBlock		      "Timer 3"
      DstPort		      5
    }
    Line {
      SrcBlock		      "From19"
      SrcPort		      1
      DstBlock		      "Timer 3"
      DstPort		      6
    }
    Line {
      SrcBlock		      "From24"
      SrcPort		      1
      DstBlock		      "Timer 4"
      DstPort		      4
    }
    Line {
      SrcBlock		      "From25"
      SrcPort		      1
      DstBlock		      "Timer 4"
      DstPort		      3
    }
    Line {
      SrcBlock		      "From36"
      SrcPort		      1
      DstBlock		      "Timer 4"
      DstPort		      2
    }
    Line {
      SrcBlock		      "From41"
      SrcPort		      1
      DstBlock		      "Timer 4"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From42"
      SrcPort		      1
      DstBlock		      "Timer 4"
      DstPort		      5
    }
    Line {
      SrcBlock		      "From43"
      SrcPort		      1
      DstBlock		      "Timer 4"
      DstPort		      6
    }
    Line {
      SrcBlock		      "From44"
      SrcPort		      1
      DstBlock		      "Timer 5"
      DstPort		      4
    }
    Line {
      SrcBlock		      "From45"
      SrcPort		      1
      DstBlock		      "Timer 5"
      DstPort		      3
    }
    Line {
      SrcBlock		      "From46"
      SrcPort		      1
      DstBlock		      "Timer 5"
      DstPort		      2
    }
    Line {
      SrcBlock		      "From47"
      SrcPort		      1
      DstBlock		      "Timer 5"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From26"
      SrcPort		      1
      DstBlock		      "Timer 5"
      DstPort		      5
    }
    Line {
      SrcBlock		      "From27"
      SrcPort		      1
      DstBlock		      "Timer 5"
      DstPort		      6
    }
    Line {
      SrcBlock		      "From30"
      SrcPort		      1
      DstBlock		      "Timer 6"
      DstPort		      4
    }
    Line {
      SrcBlock		      "From31"
      SrcPort		      1
      DstBlock		      "Timer 6"
      DstPort		      3
    }
    Line {
      SrcBlock		      "From32"
      SrcPort		      1
      DstBlock		      "Timer 6"
      DstPort		      2
    }
    Line {
      SrcBlock		      "From33"
      SrcPort		      1
      DstBlock		      "Timer 6"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From28"
      SrcPort		      1
      DstBlock		      "Timer 6"
      DstPort		      5
    }
    Line {
      SrcBlock		      "From29"
      SrcPort		      1
      DstBlock		      "Timer 6"
      DstPort		      6
    }
    Line {
      SrcBlock		      "From37"
      SrcPort		      1
      DstBlock		      "Timer 7"
      DstPort		      4
    }
    Line {
      SrcBlock		      "From38"
      SrcPort		      1
      DstBlock		      "Timer 7"
      DstPort		      3
    }
    Line {
      SrcBlock		      "From39"
      SrcPort		      1
      DstBlock		      "Timer 7"
      DstPort		      2
    }
    Line {
      SrcBlock		      "From40"
      SrcPort		      1
      DstBlock		      "Timer 7"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From34"
      SrcPort		      1
      DstBlock		      "Timer 7"
      DstPort		      5
    }
    Line {
      SrcBlock		      "From35"
      SrcPort		      1
      DstBlock		      "Timer 7"
      DstPort		      6
    }
    Line {
      SrcBlock		      "Timer 0"
      SrcPort		      1
      DstBlock		      "BitBasher"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Timer 0"
      SrcPort		      2
      DstBlock		      "BitBasher"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Timer 0"
      SrcPort		      3
      DstBlock		      "BitBasher"
      DstPort		      3
    }
    Line {
      SrcBlock		      "IDLEFORDIFS"
      SrcPort		      1
      Points		      [155, 0]
      Branch {
	DstBlock		"Timer 0"
	DstPort			7
      }
      Branch {
	Points			[0, 135]
	Branch {
	  Points		  [0, 135]
	  Branch {
	    Points		    [0, 140]
	    Branch {
	      Points		      [0, 30; 520, 0; 0, -40]
	      Branch {
		Points			[0, -140]
		Branch {
		  Points		  [0, -135]
		  Branch {
		    Points		    [0, -135]
		    DstBlock		    "Timer 4"
		    DstPort		    7
		  }
		  Branch {
		    DstBlock		    "Timer 5"
		    DstPort		    7
		  }
		}
		Branch {
		  DstBlock		  "Timer 6"
		  DstPort		  7
		}
	      }
	      Branch {
		DstBlock		"Timer 7"
		DstPort			7
	      }
	    }
	    Branch {
	      DstBlock		      "Timer 3"
	      DstPort		      7
	    }
	  }
	  Branch {
	    DstBlock		    "Timer 2"
	    DstPort		    7
	  }
	}
	Branch {
	  DstBlock		  "Timer 1"
	  DstPort		  7
	}
      }
    }
    Line {
      SrcBlock		      "Timer 1"
      SrcPort		      1
      DstBlock		      "BitBasher1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Timer 1"
      SrcPort		      2
      DstBlock		      "BitBasher1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Timer 1"
      SrcPort		      3
      DstBlock		      "BitBasher1"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Timer 2"
      SrcPort		      1
      DstBlock		      "BitBasher2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Timer 2"
      SrcPort		      2
      DstBlock		      "BitBasher2"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Timer 2"
      SrcPort		      3
      DstBlock		      "BitBasher2"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Timer 3"
      SrcPort		      1
      DstBlock		      "BitBasher3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Timer 3"
      SrcPort		      2
      DstBlock		      "BitBasher3"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Timer 3"
      SrcPort		      3
      DstBlock		      "BitBasher3"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Timer 4"
      SrcPort		      1
      DstBlock		      "BitBasher4"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Timer 4"
      SrcPort		      2
      DstBlock		      "BitBasher4"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Timer 4"
      SrcPort		      3
      DstBlock		      "BitBasher4"
      DstPort		      3
    }
    Line {
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