| 8 | |
| 9 | == 0.8 Beta Release == |
| 10 | '''Download: [http://warpproject.org/dl/refdes/802.11/Mango_802.11_RefDes_v0.9_beta.zip Mango_802.11_RefDes_v0.9_beta.zip]''' |
| 11 | |
| 12 | Release Details: |
| 13 | ||= Hardware =||= Release =||= Date Posted =||= SVN Rev. =||= ISE Ver. =||= Arch =|| |
| 14 | || WARP v3 || 0.9 Beta || 11-April-2014 || [browser:ReferenceDesigns/w3_802.11?rev=XXX XXX] || 14.4 || Dual MB/AXI || |
| 15 | |
| 16 | Changes in 0.9 Beta: |
| 17 | * Significantly expanded capabilities of [wiki:../wlan_exp experiments framework] |
| 18 | * Added new [wiki:../wlan_exp/examples wlan_exp examples] |
| 19 | * Detailed [wiki:../wlan_exp/log event log] at each node |
| 20 | * Includes every Tx/Rx event in CPU High and CPU Low |
| 21 | * Rx events capture OFDM channel estimates |
| 22 | * Tx Low events capture per-retransmission rate, contention window and backoff values |
| 23 | * Includes association state changes at AP and STA |
| 24 | * Python tools to retrieve log data, parse into numpy structured arrays |
| 25 | * New wlan_exp Python control of: |
| 26 | * Per-node, per-destination locally generated traffic (LTG) |
| 27 | * Tx rate and Tx power per-node, per-destination |
| 28 | * Retrieval / reset of Tx/Rx stats |
| 29 | * Node microsecond timestamp - node timers can be synchronized with broadcast Ethernet packet |
| 30 | * Added duration for LTG schedules; traffic flows can now auto-terminate |
| 31 | * Unified structures for all doubly-linked lists (LTG, scheduler, Tx queue, association table) |
| 32 | * Reserved 16MB of DRAM for user scratch space ({{{DDR3_SCRATCH_SIZE}}} bytes starting at {{{DDR3_SCRATCH_BASEADDR}}}) |
| 33 | * Updated to latest hardware support cores (radio_controller, w3_ad_controller) |
| 34 | * MAC/PHY core updates |
| 35 | * Added logic to MAC to capture timestamp of each Tx start |
| 36 | * Added logic to Tx to automatically insert current microsecond timestamp (for beacon frames) |
| 37 | * Added Tx gain param for MPDUO Tx and auto Tx control paths |
| 38 | * Added more pipeline registers to debug outputs in all cores, for easier timing closure |
| 39 | * Added basic floorplanning to UCF in XPS project, for more consistent timing closure |
| 40 | |
| 41 | ---- |