The 802.11 Reference Design and its documentation are under active development by the Mango team. The current release should be considered a beta- updates with bug fixes, API changes, new features and other refinements will be posted frequently. Please check the downloads page for the latest updates and post any questions about the design to the forums.

802.11 Reference Design: Lower-level MAC Description

The lower level MAC interfaces directly to the PHY Tx and Rx cores and handles all wireless transmissions and receptions. Minimizing processing latency in the lower level MAC is critical in order to meet the 802.11 channel access timing requirements.

Minimal state is maintained at this level. Only the contention window and station retry counters are stored across packet transmission events. All other state (AP vs. STA, association state, etc.) is maintained by the upper layer MAC.

Processing in the lower level MAC is divided across two resources:

• The C code in the CPU Low MicroBlaze core (wlan_mac_dcf.c)
• The wlan_mac_dcf_hw core in the FPGA fabric (wlan_mac_dcf_hw.mdl)

The C code interfaces with the upper layer MAC via the inter-processor mailbox and accesses the Tx/Rx PHY via the wlan_mac_dcf_hw core.

The wlan_mac_dcf_hw core connects directly to the Tx/Rx PHY control and status signals. It also implements the timers and state machines required to meet the 802.11 channel access timing requirements. The core is controlled from the lower level MAC C code.