Changes between Version 10 and Version 11 of 802.11/PHY
- Timestamp:
- Dec 2, 2013, 3:19:02 AM (10 years ago)
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802.11/PHY
v10 v11 17 17 * wlan_phy_agc: Automatic gain control (AGC) 18 18 19 [[Image(wiki:802.11/files /wlan_phy_cores_arch.png)]]19 [[Image(wiki:802.11/files:wlan_phy_cores_arch.png)]] 20 20 21 21 At one end the PHY cores interface directly to the ADCs and DACs on the WARP v3 hardware via the w3_ad_bridge core. These interfaces are complex sample streams running at 20MHz. At the other end the cores connect to the Tx and Rx packet buffers. The packet buffers are implemented as dual-port RAMs, each with one port dedicated to PHY access and the other port tied to the AXI interconnect for access by the CPUs.