Changes between Version 42 and Version 43 of 802.11/ResourceUsage
- Timestamp:
- Jan 18, 2018, 11:38:54 AM (6 years ago)
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802.11/ResourceUsage
v42 v43 5 5 [[TracNav(802.11/TOC)]] 6 6 7 = 802.11 Reference Design v1.7. 4: Resource Usage =7 = 802.11 Reference Design v1.7.5: Resource Usage = 8 8 9 9 The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. … … 13 13 14 14 ||= Resource =||= Used =|| 15 || Slice Registers || 80,5 60 out of 301,440 (26%) ||16 || LUTs || 71,036 out of 150,720 (47%) ||15 || Slice Registers || 80,590 out of 301,440 (26%) || 16 || LUTs || 69,847 out of 150,720 (46%) || 17 17 || Block RAMs (see note 1) || 272 of 416 (65%) || 18 18 || DSP48 (multipliers) || 194 of 768 (23%) || … … 48 48 Number of warnings: 354 49 49 Slice Logic Utilization: 50 Number of Slice Registers: 80,5 60 out of 301,440 26%51 Number used as Flip Flops: 80, 39850 Number of Slice Registers: 80,590 out of 301,440 26% 51 Number used as Flip Flops: 80,428 52 52 Number used as Latches: 4 53 53 Number used as Latch-thrus: 0 54 54 Number used as AND/OR logics: 158 55 Number of Slice LUTs: 71,036 out of 150,720 47%56 Number used as logic: 57,52 0out of 150,720 38%57 Number using O6 output only: 43,46 258 Number using O5 output only: 1,5 4459 Number using O5 and O6: 12,5 1455 Number of Slice LUTs: 69,847 out of 150,720 46% 56 Number used as logic: 57,521 out of 150,720 38% 57 Number using O6 output only: 43,463 58 Number using O5 output only: 1,536 59 Number using O5 and O6: 12,522 60 60 Number used as ROM: 0 61 Number used as Memory: 8,34 9out of 58,400 14%61 Number used as Memory: 8,348 out of 58,400 14% 62 62 Number used as Dual Port RAM: 2,522 63 63 Number using O6 output only: 1,546 … … 68 68 Number using O5 output only: 0 69 69 Number using O5 and O6: 12 70 Number used as Shift Register: 5,79 671 Number using O6 output only: 5,0 8472 Number using O5 output only: 1773 Number using O5 and O6: 69 574 Number used exclusively as route-thrus: 5,16775 Number with same-slice register load: 4,20570 Number used as Shift Register: 5,795 71 Number using O6 output only: 5,077 72 Number using O5 output only: 20 73 Number using O5 and O6: 698 74 Number used exclusively as route-thrus: 3,978 75 Number with same-slice register load: 3,013 76 76 Number with same-slice carry load: 489 77 Number with other load: 47 377 Number with other load: 476 78 78 79 79 Slice Logic Distribution: 80 Number of occupied Slices: 28,613 out of 37,680 75%81 Number of LUT Flip Flop pairs used: 9 1,54982 Number with an unused Flip Flop: 2 1,879 out of 91,54923%83 Number with an unused LUT: 2 0,513 out of 91,549 22%84 Number of fully used LUT-FF pairs: 4 9,157 out of 91,549 53%85 Number of unique control sets: 2,8 3080 Number of occupied Slices: 30,018 out of 37,680 79% 81 Number of LUT Flip Flop pairs used: 93,258 82 Number with an unused Flip Flop: 22,164 out of 93,258 23% 83 Number with an unused LUT: 23,411 out of 93,258 25% 84 Number of fully used LUT-FF pairs: 47,683 out of 93,258 51% 85 Number of unique control sets: 2,847 86 86 Number of slice register sites lost 87 to control set restrictions: 10, 577out of 301,440 3%87 to control set restrictions: 10,633 out of 301,440 3% 88 88 89 89 A LUT Flip Flop pair for this architecture represents one LUT paired with … … 140 140 141 141 Number of RPM macros: 15 142 Average Fanout of Non-Clock Nets: 3. 50142 Average Fanout of Non-Clock Nets: 3.49 143 143 }}} 144 144