| | 1 | [[TracNav(802.11/TOC)]] |
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| | 3 | = Using the 802.11 Reference Design: Clock Connections = |
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| | 5 | The 802.11 Reference Design does not require any external clock connections. By default the reference design will use the oscillators on the WARP v3 board for all system and RF clocking. |
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| | 7 | The reference design does support sourcing and sinking external clocks for synchronization of multiple nodes. There are two hardware options for this synchronization: the [wiki:HardwareUsersGuides/CM-MMCX CM-MMCX Clock Module] and the [wiki:HardwareUsersGuides/CM-PLL CM-PLL Clock Module] |
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| | 9 | '''Important''': the interpretation of switches on clock modules changed in 802.11 Reference Design v1.5. The guide below describes the current (v1.5 and later) configuration options for clock modules in the reference design. The interpretation of clock module switches here matches those in the WARPLab Reference Design v7.6 and later. |
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| | 11 | For more details about clocking on WARP v3 hardware, refer to the [wiki:HardwareUsersGuides/WARPv3/Clocking WARP v3 user guide] and [wiki:cores/w3_clock_controller w3_clock_controller guide]. |
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| | 13 | == CM-MMCX Clock Module == |
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| | 15 | The CM-MMCX is capable of sourcing and/or sinking RF and sampling clocks. This clock module can be used in a daisy chain configuration, where a single primary node shares its internal clocks with a chain of secondary nodes that adopt and forward the clocks. The role of each node is configured via the 2-position SIP switch on the CM-MMCX, according to the figure below. |
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| | 17 | * Detailed information on the WARP v3 Clocking configuration can be found [wiki:HardwareUsersGuides/WARPv3/Clocking here]. |
| | 18 | * To adjust the functionality, please use the following SIP switch settings: |
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| | 20 | [[Image(MMCX_v1_labelled.png)]] |
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| | 22 | == CM-PLL Clock Module == |
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| | 24 | The CM-PLL is capable of sourcing and/or sinking a clock referenced used to discipline a PLL on each node. This clock module can be used in a daisy chain configuration, where a single primary node shares its clock reference with a chain of secondary nodes that adopt and forward the clock reference. The role of each node is configured via the 6-position SIP switch on the CM-PLL, according to the figure below. |
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| | 26 | The 802.11 Reference Design does not use the gpio signals routed to the CM-PLL headers. User applications can use these signals if needed. |
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| | 28 | [[Image(PLL_v1_labelled.png)]] |
