wiki:802.11/wlan_exp/app_notes/four_radio

Modifying the 802.11 Reference Design for 4 Radios

The 802.11 Reference Design Tx and Rx PHY cores implement ports for 4 RF interfaces. The reference hardware project only connects RF A and RF B in order to maintain compatibility with WARP v3 nodes using third-party FMC modules. In order to use the reference design with 4 RF interfaces (2 WARP v3 on-board, 2 on FMC-RF-2X245 module) the following changes must be made to the XPS project's system.mhs and data/system.ucf files. The changes below are based on 802.11 Reference Design v1.5.

Rx PHY Changes

The Rx PHY core must be modified to include packet detection blocks for the RF C and RF D interfaces. There are placeholders for these blocks in the default Rx PHY core. You can duplicate the packet detection subsystem for RF A to create the subsystems for RF C and RF D. After adding the packet detection blocks for the RF C and D interfaces, you must increment the pcore version (System Generator token -> Settings), export the pcore to the XPS project, then update the HW_VER parameter for the Rx PHY core in the system.mhs file.

MHS Changes

The changes below apply to the XPS project's system.mhs file.

Add new top-level ports:

  ...
# RFC AD pins (FMC RFA)
 PORT RFC_AD_TRXD = RFC_trxd, DIR = I, VEC = [11:0]
 PORT RFC_AD_TRXCLK = RFC_trxclk, DIR = I
 PORT RFC_AD_TRXIQ = RFC_trxiq, DIR = I
 PORT RFC_AD_TXD = RFC_txd, DIR = O, VEC = [11:0]
 PORT RFC_AD_TXIQ = RFC_txiq, DIR = O
 PORT RFC_AD_TXCLK = RFC_txclk, DIR = O
# RFD AD pins (FMC RFB)
 PORT RFD_AD_TRXD = RFD_trxd, DIR = I, VEC = [11:0]
 PORT RFD_AD_TRXCLK = RFD_trxclk, DIR = I
 PORT RFD_AD_TRXIQ = RFD_trxiq, DIR = I
 PORT RFD_AD_TXD = RFD_txd, DIR = O, VEC = [11:0]
 PORT RFD_AD_TXIQ = RFD_txiq, DIR = O
 PORT RFD_AD_TXCLK = RFD_txclk, DIR = O
# FMC RSSI ADC pins
 PORT RFC_RSSI_D = RFC_RSSI_D, DIR = I, VEC = [9:0]
 PORT RFD_RSSI_D = RFD_RSSI_D, DIR = I, VEC = [9:0]
 PORT FMC_RF_RSSI_CLK = wlan_rssi_clk, DIR = O
 PORT FMC_RF_RSSI_PD = net_gnd, DIR = O
# RFC transceiver and front-end (FMC RFA)
 PORT RFC_TxEn_pin = RFC_TxEn, DIR = O
 PORT RFC_RxEn_pin = RFC_RxEn, DIR = O
 PORT RFC_RxHP_pin = RFC_RxHP, DIR = O
 PORT RFC_SHDN_pin = RFC_SHDN, DIR = O
 PORT RFC_SPI_SCLK_pin = RFC_SPI_SCLK, DIR = O
 PORT RFC_SPI_MOSI_pin = RFC_SPI_MOSI, DIR = O
 PORT RFC_SPI_CSn_pin = RFC_SPI_CSn, DIR = O
 PORT RFC_B_pin = RFC_B, DIR = O, VEC = [0:6]
 PORT RFC_LD_pin = RFC_LD, DIR = I
 PORT RFC_PAEn_24_pin = RFC_PAEn_24, DIR = O
 PORT RFC_PAEn_5_pin = RFC_PAEn_5, DIR = O
 PORT RFC_AntSw_pin = RFC_AntSw, DIR = O, VEC = [0:1]
# RFD transceiver and front-end (FMC RFB)
 PORT RFD_TxEn_pin = RFD_TxEn, DIR = O
 PORT RFD_RxEn_pin = RFD_RxEn, DIR = O
 PORT RFD_RxHP_pin = RFD_RxHP, DIR = O
 PORT RFD_SHDN_pin = RFD_SHDN, DIR = O
 PORT RFD_SPI_SCLK_pin = RFD_SPI_SCLK, DIR = O
 PORT RFD_SPI_MOSI_pin = RFD_SPI_MOSI, DIR = O
 PORT RFD_SPI_CSn_pin = RFD_SPI_CSn, DIR = O
 PORT RFD_B_pin = RFD_B, DIR = O, VEC = [0:6]
 PORT RFD_LD_pin = RFD_LD, DIR = I
 PORT RFD_PAEn_24_pin = RFD_PAEn_24, DIR = O
 PORT RFD_PAEn_5_pin = RFD_PAEn_5, DIR = O
 PORT RFD_AntSw_pin = RFD_AntSw, DIR = O, VEC = [0:1]
# AD9963 ADC/DAC control pins (RFC & RFD = FMC RFA & RFB))
 PORT RFC_AD_spi_cs_n_pin = RFC_AD_spi_cs_n, DIR = O
 PORT RFC_AD_spi_sdio = RFC_AD_spi_sdio, DIR = IO
 PORT RFC_AD_spi_sclk_pin = RFC_AD_spi_sclk, DIR = O
 PORT RFC_AD_reset_n_pin = RFC_AD_reset_n, DIR = O
 PORT RFD_AD_spi_cs_n_pin = RFD_AD_spi_cs_n, DIR = O
 PORT RFD_AD_spi_sdio = RFD_AD_spi_sdio, DIR = IO
 PORT RFD_AD_spi_sclk_pin = RFD_AD_spi_sclk, DIR = O
 PORT RFD_AD_reset_n_pin = RFD_AD_reset_n, DIR = O
# FMC user LEDs (tied directly to radio_controller, not w3_uesrio)
 PORT RFC_led_g = RFC_led_g, DIR = O
 PORT RFC_led_r = RFC_led_r, DIR = O
 PORT RFD_led_g = RFD_led_g, DIR = O
 PORT RFD_led_r = RFD_led_r, DIR = O
# IIC EEPROM pins FMC
 PORT iic_eeprom_fmc_scl_pin = iic_eeprom_fmc_scl_pin, DIR = IO
 PORT iic_eeprom_fmc_sda_pin = iic_eeprom_fmc_sda_pin, DIR = IO
  ...

Add new instances of w3_ad_bridge and w3_iic_eeprom_axi cores:

# samp_ce  unused in FMC ad_bridge; on-board ad_bridge drives PHY's ce ports
BEGIN w3_ad_bridge
 PARAMETER INSTANCE = ad_bridge_FMC
 PARAMETER HW_VER = 3.03.a
# Clock ports (inputs to w3_ad_bridge)
 PORT sys_clk = clk_160MHz
 PORT ad_TXCLK_out_en = RF_AD_TXCLK_out_en
# Top-level AD9963 ports
 PORT ad_RFA_TXD = rfc_txd
 PORT ad_RFA_TXCLK = rfc_txclk
 PORT ad_RFA_TXIQ = rfc_txiq
 PORT ad_RFA_TRXD = rfc_trxd
 PORT ad_RFA_TRXCLK = rfc_trxclk
 PORT ad_RFA_TRXIQ = rfc_trxiq
 PORT ad_RFB_TXD = rfd_txd
 PORT ad_RFB_TXCLK = rfd_txclk
 PORT ad_RFB_TXIQ = rfd_txiq
 PORT ad_RFB_TRXD = rfd_trxd
 PORT ad_RFB_TRXCLK = rfd_trxclk
 PORT ad_RFB_TRXIQ = rfd_trxiq
 PORT user_RFA_TXD_I = RFC_TX_I
 PORT user_RFA_TXD_Q = RFC_TX_Q
 PORT user_RFA_RXD_I = RFC_RX_I
 PORT user_RFA_RXD_Q = RFC_RX_Q
 PORT user_RFB_TXD_I = RFD_TX_I
 PORT user_RFB_TXD_Q = RFD_TX_Q
 PORT user_RFB_RXD_I = RFD_RX_I
 PORT user_RFB_RXD_Q = RFD_RX_Q
END

BEGIN w3_iic_eeprom_axi
 PARAMETER INSTANCE = w3_iic_eeprom_FMC
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x82010000
 PARAMETER C_HIGHADDR = 0x8201FFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7
 BUS_INTERFACE S_AXI = mb_shared_axi_periph
 PORT S_AXI_ACLK = clk_160MHz
 PORT iic_scl_io= iic_eeprom_fmc_scl_pin
 PORT iic_sda_io= iic_eeprom_fmc_sda_pin
END

Add port connections to radio_controller_axi instance:

BEGIN radio_controller_axi
  ...
 PORT RFC_TxEn = RFC_TxEn
 PORT RFC_RxEn = RFC_RxEn
 PORT RFC_RxHP = RFC_RxHP
 PORT RFC_SHDN = RFC_SHDN
 PORT RFC_SPI_SCLK = RFC_SPI_SCLK
 PORT RFC_SPI_MOSI = RFC_SPI_MOSI
 PORT RFC_SPI_CSn = RFC_SPI_CSn
 PORT RFC_B = RFC_B
 PORT RFC_LD = RFC_LD
 PORT RFC_PAEn_24 = RFC_PAEn_24
 PORT RFC_PAEn_5 = RFC_PAEn_5
 PORT RFC_AntSw = RFC_AntSw
 PORT RFD_TxEn = RFD_TxEn
 PORT RFD_RxEn = RFD_RxEn
 PORT RFD_RxHP = RFD_RxHP
 PORT RFD_SHDN = RFD_SHDN
 PORT RFD_SPI_SCLK = RFD_SPI_SCLK
 PORT RFD_SPI_MOSI = RFD_SPI_MOSI
 PORT RFD_SPI_CSn = RFD_SPI_CSn
 PORT RFD_B = RFD_B
 PORT RFD_LD = RFD_LD
 PORT RFD_PAEn_24 = RFD_PAEn_24
 PORT RFD_PAEn_5 = RFD_PAEn_5
 PORT RFD_AntSw = RFD_AntSw
  ....
 PORT usr_RFC_statLED_Tx = RFC_led_g
 PORT usr_RFC_statLED_Rx = RFC_led_r
 PORT usr_RFD_statLED_Tx = RFD_led_g
 PORT usr_RFD_statLED_Rx = RFD_led_r
  ....
 PORT usr_RFC_TxEn = phy_rc_txen_c
 PORT usr_RFC_RxEn = rc_usr_rxen
 PORT usr_RFC_RxHP = agc_rfc_rxhp
 PORT usr_RFC_RxGainBB = agc_rfc_g_bb
 PORT usr_RFC_RxGainRF = agc_rfc_g_rf
 PORT usr_RFC_TxGain = phy_rc_tx_gain_c
 PORT usr_RFD_TxEn = phy_rc_txen_d
 PORT usr_RFD_RxEn = rc_usr_rxen
 PORT usr_RFD_RxHP = agc_rfd_rxhp
 PORT usr_RFD_RxGainBB = agc_rfd_g_bb
 PORT usr_RFD_RxGainRF = agc_rfd_g_rf
 PORT usr_RFD_TxGain = phy_rc_tx_gain_d
  ....
END

Add parameter and port connections to the existing w3_ad_controller_axi instance:

BEGIN w3_ad_controller_axi
  ...
 PARAMETER INCLUDE_RFC_RFD_IO = 1
  ...
 PORT RFC_AD_spi_cs_n = RFC_AD_spi_cs_n
 PORT RFC_AD_spi_sdio = RFC_AD_spi_sdio
 PORT RFC_AD_spi_sclk = RFC_AD_spi_sclk
 PORT RFC_AD_reset_n = RFC_AD_reset_n
 PORT RFD_AD_spi_cs_n = RFD_AD_spi_cs_n
 PORT RFD_AD_spi_sdio = RFD_AD_spi_sdio
 PORT RFD_AD_spi_sclk = RFD_AD_spi_sclk
 PORT RFD_AD_reset_n = RFD_AD_reset_n
  ...
END

Add port connections to the existing wlan_mac_hw instance:

BEGIN wlan_mac_hw
  ...
 PORT phy_tx_gain_c = mac_phy_tx_gain_c
 PORT phy_tx_gain_d = mac_phy_tx_gain_d
  ...
END

Add port connections to the existing wlan_phy_tx_pmd_axiw instance:

BEGIN wlan_phy_tx_pmd_axiw
  ...
 PORT rfc_dac_i = RFC_TX_I
 PORT rfc_dac_q = RFC_TX_Q
 PORT rfd_dac_i = RFD_TX_I
 PORT rfd_dac_q = RFD_TX_Q
  ...
 PORT rc_usr_txen_c = phy_rc_txen_c
 PORT rc_usr_txen_d = phy_rc_txen_d
  ...
 PORT rc_tx_gain_c = phy_rc_tx_gain_c
 PORT rc_tx_gain_d = phy_rc_tx_gain_d
  ...
 PORT phy_tx_gain_c = mac_phy_tx_gain_c
 PORT phy_tx_gain_d = mac_phy_tx_gain_d
  ...
END

Add port connections to the existing wlan_phy_rx_pmd_axiw instance:

BEGIN wlan_phy_rx_pmd_axiw
  ...
 PORT rfc_rx_i = agc_rfc_i
 PORT rfc_rx_q = agc_rfc_q
 PORT rfc_rssi = RFC_RSSI_D
 PORT rfd_rx_i = agc_rfd_i
 PORT rfd_rx_q = agc_rfd_q
 PORT rfd_rssi = RFD_RSSI_D
  ...
 PORT rfc_g_rf = agc_rfc_g_rf
 PORT rfc_g_bb = agc_rfc_g_bb
 PORT rfd_g_rf = agc_rfd_g_rf
 PORT rfd_g_bb = agc_rfd_g_bb
  ...
END

Add port connections to the existing wlan_agc_axiw instance:

BEGIN wlan_agc_axiw
  ...
 PORT rfc_rssi = RFC_RSSI_D
 PORT rfc_rx_i_in = RFC_RX_I
 PORT rfc_rx_q_in = RFC_RX_Q
 PORT rfd_rssi = RFD_RSSI_D
 PORT rfd_rx_i_in = RFD_RX_I
 PORT rfd_rx_q_in = RFD_RX_Q
  ...
 PORT rfc_rx_i_out = agc_rfc_i
 PORT rfc_rx_q_out = agc_rfc_q
 PORT rfd_rx_i_out = agc_rfd_i
 PORT rfd_rx_q_out = agc_rfd_q
  ...
 PORT rfc_agc_g_bb = agc_rfc_g_bb
 PORT rfc_agc_g_rf = agc_rfc_g_rf
 PORT rfc_agc_rxhp = agc_rfc_rxhp
 PORT rfd_agc_g_bb = agc_rfd_g_bb
 PORT rfd_agc_g_rf = agc_rfd_g_rf
 PORT rfd_agc_rxhp = agc_rfd_rxhp
  ...
END

UCF Changes

Add LOC and timing constraints for FMC-RF-2X245 signals to data/system.ucf:

#############################
# FMC-RF-2X245 RF Interfaces
#############################

#User LEDs
NET "RFC_LED_G" LOC = L19 | IOSTANDARD = LVCMOS25;
NET "RFC_LED_R" LOC = L18 | IOSTANDARD = LVCMOS25;

NET "RFD_LED_G" LOC = D16 | IOSTANDARD = LVCMOS25;
NET "RFD_LED_R" LOC = A15 | IOSTANDARD = LVCMOS25;

#FMC module I2C EEPROM
NET "iic_eeprom_fmc_scl_pin" LOC = F23 | IOSTANDARD = LVCMOS25;
NET "iic_eeprom_fmc_sda_pin" LOC = F24 | IOSTANDARD = LVCMOS25;

#RSSI ADC
NET "RFC_RSSI_D<0>" LOC = D21 | IOSTANDARD = LVCMOS25;
NET "RFC_RSSI_D<1>" LOC = E19 | IOSTANDARD = LVCMOS25;
NET "RFC_RSSI_D<2>" LOC = G20 | IOSTANDARD = LVCMOS25;
NET "RFC_RSSI_D<3>" LOC = E22 | IOSTANDARD = LVCMOS25;
NET "RFC_RSSI_D<4>" LOC = E23 | IOSTANDARD = LVCMOS25;
NET "RFC_RSSI_D<5>" LOC = F21 | IOSTANDARD = LVCMOS25;
NET "RFC_RSSI_D<6>" LOC = B20 | IOSTANDARD = LVCMOS25;
NET "RFC_RSSI_D<7>" LOC = B23 | IOSTANDARD = LVCMOS25;
NET "RFC_RSSI_D<8>" LOC = C19 | IOSTANDARD = LVCMOS25;
NET "RFC_RSSI_D<9>" LOC = C23 | IOSTANDARD = LVCMOS25;

NET "RFD_RSSI_D<0>" LOC = D19 | IOSTANDARD = LVCMOS25;
NET "RFD_RSSI_D<1>" LOC = E21 | IOSTANDARD = LVCMOS25;
NET "RFD_RSSI_D<2>" LOC = A23 | IOSTANDARD = LVCMOS25;
NET "RFD_RSSI_D<3>" LOC = A24 | IOSTANDARD = LVCMOS25;
NET "RFD_RSSI_D<4>" LOC = F19 | IOSTANDARD = LVCMOS25;
NET "RFD_RSSI_D<5>" LOC = H19 | IOSTANDARD = LVCMOS25;
NET "RFD_RSSI_D<6>" LOC = F20 | IOSTANDARD = LVCMOS25;
NET "RFD_RSSI_D<7>" LOC = H20 | IOSTANDARD = LVCMOS25;
NET "RFD_RSSI_D<8>" LOC = C20 | IOSTANDARD = LVCMOS25;
NET "RFD_RSSI_D<9>" LOC = J20 | IOSTANDARD = LVCMOS25;

NET "FMC_RF_RSSI_CLK" LOC = G13 | IOSTANDARD = LVCMOS25;
NET "FMC_RF_RSSI_PD" LOC = A21 | IOSTANDARD = LVCMOS25;

#FMC module RF A pins (probably renamed RF C in user project)

#ADC/DAC
NET "RFC_AD_spi_sclk_pin" LOC = B25 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_SPI_SDIO" LOC = D26 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "RFC_AD_spi_cs_n_pin" LOC = D27 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_reset_n_pin" LOC = B27 | IOSTANDARD = LVCMOS25;

NET "RFC_AD_TRXCLK" LOC = C28 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXIQ" LOC = D29 | IOSTANDARD = LVCMOS25;

NET "RFC_AD_TRXD<0>" LOC = C29 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<1>" LOC = C24 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<2>" LOC = C22 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<3>" LOC = G27 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<4>" LOC = G28 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<5>" LOC = D22 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<6>" LOC = G26 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<7>" LOC = A25 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<8>" LOC = A26 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<9>" LOC = H27 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<10>" LOC = E27 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TRXD<11>" LOC = B26 | IOSTANDARD = LVCMOS25;

NET "RFC_AD_TXCLK" LOC = C27 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXIQ" LOC = C30 | IOSTANDARD = LVCMOS25;

NET "RFC_AD_TXD<0>" LOC = F26 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<1>" LOC = K21 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<2>" LOC = E24 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<3>" LOC = G25 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<4>" LOC = F25 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<5>" LOC = E26 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<6>" LOC = A19 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<7>" LOC = D24 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<8>" LOC = A18 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<9>" LOC = L21 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<10>" LOC = L20 | IOSTANDARD = LVCMOS25;
NET "RFC_AD_TXD<11>" LOC = D30 | IOSTANDARD = LVCMOS25;

#Front end
NET "RFC_PAEn_24_pin" LOC = D14 | IOSTANDARD = LVCMOS25;
NET "RFC_PAEn_5_pin" LOC = M12 | IOSTANDARD = LVCMOS25;
NET "RFC_AntSw_pin<0>" LOC = M11 | IOSTANDARD = LVCMOS25;
NET "RFC_AntSw_pin<1>" LOC = A13 | IOSTANDARD = LVCMOS25;

#Transceiver
NET "RFC_B_pin<0>" LOC = B30 | IOSTANDARD = LVCMOS25;
NET "RFC_B_pin<1>" LOC = F28 | IOSTANDARD = LVCMOS25;
NET "RFC_B_pin<2>" LOC = B31 | IOSTANDARD = LVCMOS25;
NET "RFC_B_pin<3>" LOC = E28 | IOSTANDARD = LVCMOS25;
NET "RFC_B_pin<4>" LOC = D25 | IOSTANDARD = LVCMOS25;
NET "RFC_B_pin<5>" LOC = A30 | IOSTANDARD = LVCMOS25;
NET "RFC_B_pin<6>" LOC = A31 | IOSTANDARD = LVCMOS25;

NET "RFC_SPI_SCLK_pin" LOC = A29 | IOSTANDARD = LVCMOS25;
NET "RFC_SPI_CSn_pin" LOC = B18 | IOSTANDARD = LVCMOS25;
NET "RFC_SPI_MOSI_pin" LOC = J22 | IOSTANDARD = LVCMOS25;
NET "RFC_RXEN_pin" LOC = H22 | IOSTANDARD = LVCMOS25;
NET "RFC_RXHP_pin" LOC = B28 | IOSTANDARD = LVCMOS25;
NET "RFC_SHDN_pin" LOC = K22 | IOSTANDARD = LVCMOS25;
NET "RFC_TXEN_pin" LOC = C18 | IOSTANDARD = LVCMOS25;
NET "RFC_LD_pin" LOC = A28 | IOSTANDARD = LVCMOS25;

#FMC module RF B pins (probably renamed RF D in user project)

#ADC/DAC
NET "RFD_AD_spi_sclk_pin" LOC = K17 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_SPI_SDIO" LOC = B17 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "RFD_AD_spi_cs_n_pin" LOC = D15 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_reset_n_pin" LOC = G15 | IOSTANDARD = LVCMOS25;

NET "RFD_AD_TRXCLK" LOC = L15 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXIQ" LOC = K18 | IOSTANDARD = LVCMOS25;

NET "RFD_AD_TRXD<0>" LOC = J16 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<1>" LOC = H17 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<2>" LOC = J17 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<3>" LOC = L16 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<4>" LOC = G18 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<5>" LOC = M18 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<6>" LOC = H18 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<7>" LOC = M17 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<8>" LOC = D17 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<9>" LOC = J19 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<10>" LOC = K19 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TRXD<11>" LOC = E18 | IOSTANDARD = LVCMOS25;

NET "RFD_AD_TXCLK" LOC = C17 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXIQ" LOC = E17 | IOSTANDARD = LVCMOS25;

NET "RFD_AD_TXD<0>" LOC = B16 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<1>" LOC = J15 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<2>" LOC = A16 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<3>" LOC = H15 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<4>" LOC = M15 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<5>" LOC = F15 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<6>" LOC = C15 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<7>" LOC = M16 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<8>" LOC = B15 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<9>" LOC = G16 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<10>" LOC = F18 | IOSTANDARD = LVCMOS25;
NET "RFD_AD_TXD<11>" LOC = F16 | IOSTANDARD = LVCMOS25;

#Front end
NET "RFD_PAEn_24_pin" LOC = A14 | IOSTANDARD = LVCMOS25;
NET "RFD_PAEn_5_pin" LOC = B13 | IOSTANDARD = LVCMOS25;
NET "RFD_AntSw_pin<0>" LOC = C14 | IOSTANDARD = LVCMOS25;
NET "RFD_AntSw_pin<1>" LOC = B12 | IOSTANDARD = LVCMOS25;

#Transceiver
NET "RFD_B_pin<0>" LOC = H12 | IOSTANDARD = LVCMOS25;
NET "RFD_B_pin<1>" LOC = H13 | IOSTANDARD = LVCMOS25;
NET "RFD_B_pin<2>" LOC = M13 | IOSTANDARD = LVCMOS25;
NET "RFD_B_pin<3>" LOC = G12 | IOSTANDARD = LVCMOS25;
NET "RFD_B_pin<4>" LOC = F14 | IOSTANDARD = LVCMOS25;
NET "RFD_B_pin<5>" LOC = H14 | IOSTANDARD = LVCMOS25;
NET "RFD_B_pin<6>" LOC = J12 | IOSTANDARD = LVCMOS25;
NET "RFD_SPI_SCLK_pin" LOC = G10 | IOSTANDARD = LVCMOS25;
NET "RFD_SPI_CSn_pin" LOC = K13 | IOSTANDARD = LVCMOS25;
NET "RFD_SPI_MOSI_pin" LOC = F11 | IOSTANDARD = LVCMOS25;
NET "RFD_RXEN_pin" LOC = K12 | IOSTANDARD = LVCMOS25;
NET "RFD_RXHP_pin" LOC = L13 | IOSTANDARD = LVCMOS25;
NET "RFD_SHDN_pin" LOC = K11 | IOSTANDARD = LVCMOS25;
NET "RFD_TXEN_pin" LOC = H10 | IOSTANDARD = LVCMOS25;
NET "RFD_LD_pin" LOC = L11 | IOSTANDARD = LVCMOS25;

#Timing
#AD9963 data interface clock constraints
Net RFC_AD_TRXCLK TNM_NET = TNM_RFC_AD_TRXCLK;
Net RFD_AD_TRXCLK TNM_NET = TNM_RFD_AD_TRXCLK;

#TRXCLK runs up to 40MHz (no decimation in AD9963s)
TIMESPEC TS_RFC_AD_TRXCLK = PERIOD TNM_RFC_AD_TRXCLK TS_samp_clk*2;
TIMESPEC TS_RFD_AD_TRXCLK = PERIOD TNM_RFD_AD_TRXCLK TS_samp_clk*2;

#Define relationship of TRXD and TRXCLK, based on AD9963 specs
# Using worst-case output delay from AD9963 datasheet table 23
# TRXCLK leads TRXD transition by t_OD2; ad_bridge uses IDELAY to shift this to mid valid window
# VALID window below assumes DDR interleaved I/Q at 20MSps rate (25nsec / half sample)
INST "RFC_AD_TRXD<*>" TNM = RFC_AD_TRXD_group;
NET "RFC_AD_TRXCLK" TNM_NET = RFC_AD_TRXCLK;
TIMEGRP "RFC_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFC_AD_TRXCLK" RISING;
TIMEGRP "RFC_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFC_AD_TRXCLK" FALLING;

INST "RFD_AD_TRXD<*>" TNM = RFD_AD_TRXD_group;
NET "RFD_AD_TRXCLK" TNM_NET = RFD_AD_TRXCLK;
TIMEGRP "RFD_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFD_AD_TRXCLK" RISING;
TIMEGRP "RFD_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFD_AD_TRXCLK" FALLING;
Last modified 2 years ago Last modified on Dec 9, 2017, 12:39:20 PM