Please visit WARP platform support cores for the latest documentation. The links below are out of date but preserved for reference.

Interface Cores

• Radio Controller - Utilizes the SPI registers on the Radio Board and other pins to directly control the Radio Board. It connects through the Radio Bridge.
• Radio Bridge - Maps all the pins of the Radio Board to user ports and to connect to the Radio Controller.
• Analog Bridge - Maps the pins of the Analog Board to user ports.
• User I/O Board Controller - Provides drivers and hardware to control the LCD, Buzzer, LEDs etc. on the User I/O Board.
• EEPROM - Core used to access the EEPROM devices located on the WARP FPGA and WARP radio boards.
• SISO Automatic Gain Control - Automatic Gain Control
• Browse All Peripherals in the WARP Repository

Board Support

• XBD - Describes the WARP FPGA Board to the Xilinx tools for Base System Builder use.

System Generator Tools

• WARP Blockset - Additional blocks over System Generator that enable the use of the Radio Boards from user designs.

Note: The following tools are used only for Xilinx versions 9.1 and lower. As of version 10.1.02, Xilinx has added a stable EDK export flow to System Generator. The new flow creates a PLB46 slave interface with access to registers, FIFOs and shared memory blocks in the user design. This flow completely replaces sysgen2opb and the OPB Export Tool. As a result, these tools are no longer maintained.

• sysgen2opb - Adds the OPB interface to custom sysgen cores.
• WARP OPB Export Tool - Export custom Sysgen cores to EDK.