== WARP Daughtercard Specification ==

=== Schematic ===

[[Image(WARPImages:DaughtercardSlotSchematic.png)]]

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=== Mechanical ===

[[Image(WARPImages:Daughtercard_Mech_Drawing.png)]]

 * A = 1.471"; vertical distance from center of pin 1 to center of pin 81
 * B1 = 1.923"; horizontal distance from left edge to pin 1/81 vertical
 * B2 = 1.005"; horizontal distance from right edge to pin 1/81 vertical
 * C = 0.735"; vertical distance from mounting hole center to pin 1
 * D = 0.883"; horizontal distance from mounting hole center to pin 1/81 vertical
 * E = 2.928"; horizontal edge to edge
 * F = 1.780"; vertical edge to edge
 * øG = 0.1" (diameter before plating); plated mounting hole (connected to ground)

A PDF version of this drawing is also available: [attachment:wiki:WARPFiles:Daughtercard_Mech_Drawing.pdf?format=raw Daughtercard Mechanical Drawing PDF].

WARP daughtercards use two 80 pin headers per daughtercard slot. The connectors are 0.5mm pitch, 4mm height headers with metal fittings from the Hirose DF17 series of connectors. The Hirose part number is DF17(4.0)-80DP-0.5V(57). See the [attachment:wiki:WARPFiles:Hirose_DF17_Connectors_Datasheet.pdf?format=raw Hirose DF17 Connectors Datasheet] for the full mechanical details (pg 6) and recommended PCB footprint (pg 8). 

The parts are available from [http://www.digikey.com Digikey]; search for Digikey part number [http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?Ref=13424&Row=476393&Site=US H11148CT-ND].

=== Reference Designs ===
[attachment:wiki:WARPFiles:Daughtercard_Template_Schematic.zip?format=raw Daughtercard_Template_Schematic.zip]
  Cadence Capture CIS 15.7 project, schematic design and parts library.

[attachment:wiki:WARPFiles:Daughtercard_Template_Board.zip?format=raw Daughtercard_Template_Board.zip]
  Cadence Allegro PCB Editor 15.7 padstacks, package symbols and sample board.