Changes between Version 20 and Version 21 of Exercises/13_4/IntroToXPS


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Timestamp:
Aug 20, 2012, 1:43:59 PM (12 years ago)
Author:
chunter
Comment:

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  • Exercises/13_4/IntroToXPS

    v20 v21  
    3333* Captured Output Register: This register attaches to the bus and allows C-code executing inside the MicroBlaze to read the current latched output of the LFSR.
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    35 For the purpose of this exercise, we have provided this pcore as an example of a hardware peripheral you may want to integrate into your design. The [wiki:Exercises/13_4/SysgenExportPcore Exporting pcores from System Generator] exercise covers how this pcore was created.
     35You will also notice in the diagram the green "FPGA Pins" ports. These are top-level ports that are routed out to physical pins on the FPGA. These pins are connected to other components on the WARP board. For the purpose of this exercise, we have provided this pcore as an example of a hardware peripheral you may want to integrate into your design. The [wiki:Exercises/13_4/SysgenExportPcore Exporting pcores from System Generator] exercise covers how this pcore was created.
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