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IntroToXPS

v43	v44
32	32	* Captured Output Register: This register attaches to the bus and allows C-code executing inside the MicroBlaze to read the current latched output of the LFSR.
33	33
34		You will also notice in the diagram the green "FPGA Pins" ports. These are top-level ports that are routed out to physical pins on the FPGA. These pins are connected to other components on the WARP board. For the purpose of this exercise, we have provided this pcore as an example of a hardware peripheral you may want to integrate into your design. The [wiki:Exercises/13_4/Sys~~genExportPcore~~ Exporting pcores from System Generator] exercise covers how this pcore was created.
	34	You will also notice in the diagram the green "FPGA Pins" ports. These are top-level ports that are routed out to physical pins on the FPGA. These pins are connected to other components on the WARP board. For the purpose of this exercise, we have provided this pcore as an example of a hardware peripheral you may want to integrate into your design. The [wiki:Exercises/13_4/SysGenExport Exporting pcores from System Generator] exercise covers how this pcore was created.
35	35
36	36