Changes between Version 6 and Version 7 of Exercises/13_4/SysGenExport
- Timestamp:
- Aug 23, 2012, 9:25:04 AM (12 years ago)
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Exercises/13_4/SysGenExport
v6 v7 2 2 ''(compatible with WARP v2 and WARP v3)'' 3 3 4 In the [wiki:Exercises/13_4/IntroToXPS Introduction to XPS] project, a peripheral core is provided and users connect it to the rest of the system specified in a WARP template XPS design. In this exercise, users will learn how to create this peripheral core from a tool known as Xilinx System Generator (SysGen).4 In the [wiki:Exercises/13_4/IntroToXPS Introduction to XPS] exercise, a peripheral core is provided and users connect it to the rest of the system specified in a WARP template XPS design. In this exercise, users will learn how to create this peripheral core from a tool known as Xilinx System Generator (SysGen). 5 5 6 6 == Prerequisites == … … 10 10 * WARP v3: External USB JTAG cable and a micro USB cable for UART 11 11 * Complete installation of ISE System Edition 13.4 12 * Installation of Matlab 2011a or 2011b 12 13 * Set up a terminal on your computer using PuTTY or an alternative. Instructions to do this are available [wiki:HowTo/SetUpPuTTY instructions here]. 13 14 … … 15 16 [[Image(overview.png)]] 16 17 17 In this exercise, we provide users with a custom design with a Linear Feedback Shift Register ([http://en.wikipedia.org/wiki/Linear_feedback_shift_register LFSR]) that produces a sequence of pseudorandom values. These values are then latched by a counter circuit to slow them down and make their changes visible to the naked eye when observing a board. The output of this latch is sliced up and connected to output ports. 18 18 In this exercise, we provide users with a custom design that uses a Linear Feedback Shift Register ([http://en.wikipedia.org/wiki/Linear_feedback_shift_register LFSR]) to produce a sequence of pseudorandom values. These values are then latched by a counter circuit to slow them down and make their changes visible to the naked eye when observing a board. The output of this latch is sliced up and connected to output ports. This design is provided as a Xilinx System Generator model. In this exercise, users will export this model to create the pcore that was provided in the [wiki:Exercises/13_4/IntroToXPS Introduction to XPS] exercise. 19 19 20 20 21 21 == Instructions == 22 22 23 [raw-attachment:prng_useriosrc.mdl Test2] 23 1. Download the [raw-attachment:prng_useriosrc.mdl System Generator Model] and open it in Matlab 24 1. 24 25 25 26 = Additional Questions and Feedback =