= Exporting a Peripheral Core from System Generator =
''(compatible with WARP v2 and WARP v3)''

In the [wiki:Exercises/13_4/IntroToXPS Introduction to XPS] project, a peripheral core is provided and users connect it to the rest of the system specified in a WARP template XPS design. In this exercise, users will learn how to create this peripheral core from a tool known as Xilinx System Generator (SysGen).

== Prerequisites ==
 * You have a WARP v2 or WARP v3 board
 * ESD protection for the WARP board (wrist strap, etc)
 * WARP v2: USB cable for programming and USB cable for UART
 * WARP v3: External USB JTAG cable and a micro USB cable for UART
 * Complete installation of ISE System Edition 13.4
 * Set up a terminal on your computer using PuTTY or an alternative. Instructions to do this are available [wiki:HowTo/SetUpPuTTY instructions here].

== Overview ==
[[Image(overview.png)]]

In this exercise, we provide users with a custom design with a Linear Feedback Shift Register ([http://en.wikipedia.org/wiki/Linear_feedback_shift_register LFSR]) that produces a sequence of pseudorandom values. These values are then latched by a counter circuit to slow them down and make their changes visible to the naked eye when observing a board. The output of this latch is sliced up and connected to output ports.



== Instructions ==

[raw-attachment:prng_useriosrc.mdl Test2]

= Additional Questions and Feedback = 
If you have any additional questions about this exercise or other feedback, please post to the [http://warp.rice.edu/forums/ WARP Forums].