Changes between Initial Version and Version 1 of Exercises/XPSIntro/BSBWizard

Timestamp:

Mar 20, 2007, 11:22:56 AM (17 years ago)

Author:

cjcamp

Comment:

--

Exercises/XPSIntro/BSBWizard

@@ +1 @@
+Open the Xilinx Platform Studio application.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_01a.jpg)]]
+
+A window will appear for selecting the type of project to be opened - new or existing.  New projects may be created either manually (Blank XPS Project) or with the assistance of the Base System Builder Wizard.  Select the Base System Builder option and click OK.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_02a.jpg)]]
+
+The next window specfies the complete path to the project file that the wizard will create.  Click BROWSE to browse for the the directory in which the project will be created.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_03a.jpg)]]
+
+Navigate to the directory in which you would like the wizard to create the project file.  Specify a name for the file, typically system.xmp, then click SAVE.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_04a.jpg)]]
+
+The preceding window will again appear, this time displaying the complete project file name (including its directory path).  Click OK.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_05a.jpg)]]
+
+In the next window, select the option for creation of a new design, then click NEXT.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_06a.jpg)]]
+
+For the target development board, select Rice University's WARP FPGA and radio boards (versions 1.2 and 1.4, respectively).  Click NEXT.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_07a.jpg)]]
+
+The Rice University WARP FPGA board utilizes a Virtex-2 Pro FPGA.  This device contains an embedded PowerPC processor, so select PowerPC as the processor to be used in this design.  Click NEXT.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_08a.jpg)]]
+
+In the next window...
+
+   - Choose 100 MHz for the processor clock frequency.
+
+   - Choose 50 MHz for the bus clock frequency.
+
+   - Choose FPJA JTAG for the debug interface.
+
+   - Choose 64 KBytes of on-chip BRAM-based data memory.
+
+   - Choose 128 KBytes of on-chip BRAM-based instruction memory.
+
+Click NEXT.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_09a.jpg)]]
+
+IO devices in the system consist of IP modules that reside on the FPGA's internal system buses.  These IP modules connect to external (off-chip) hardware devices through the FPGA's IO pins, and are controlled by processors (or other "intelligent" devices) in the system.  Select the following IO devices to be added to your system...
+
+   - Both 7-segment LED devices.
+
+   - The 4-bit discrete LED device.
+
+   - The 4-bit pushbutton device.
+
+   - The 4-bit DIP switch device.
+
+Click NEXT.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_10a.jpg)]]
+
+Select the RS232 device, specifying a buad rate of 9600, 8 data bits, and no parity.  Select the Clock Board Configurator (CLKBRDCONFIG_0).  Do not select the SysACE Compact Flash device.  Do not select EEPROM_0.  Click NEXT.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_11a.jpg)]]
+
+Do not select the Ethernet MAC device, the radio controller device, any radio bridge devices, or any SRAM devices.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_12a.jpg)]]
+
+[[Image(Exercises/XPSIntro/Files:xps_development_13a.jpg)]]
+
+The PLB Block RAM Interface Controller allows for system memory expansion through the instantiation of Block RAM devices within the FPGA.  Since this exercise is fairly small in size, the additional storage capacity is not needed.  Click REMOVE.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_14a.jpg)]]
+
+The PLB Block RAM Interface Controller should no longer be visible in the current peripheral list.  Click NEXT.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_15a.jpg)]]
+
+Select RS232 for both standard input and standard output.  Do not select any sample applications.  Click NEXT.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_16a.jpg)]]
+
+The next window to appear shows a summary of the system that will be created, including the address range of each system resource.  These resources include on-chip instruction memory (isbram_if_cntlr), on-chip data memory (dsbram_if_cntlr), a PLB-to-OPB bus bridge (plb2opb_bridge), and various peripherals that were selected in the preceding windows.  The PLB (Processor Local Bus) and the OPB (On-Chip Peripheral Bus) are two different buses that interconnect various resources within the system.  The PLB is a higher-performing and more complicated bus.  The OPB provides slightly lower performance, but with lower complexity.  Click GENERATE to generate the hardware system defined by this summary.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_17a.jpg)]]
+
+The next window provides a summary of all generated files, including the name and location of a BSB file.  This BSB file contains a record of all selections made in the Base System Builder Wizard, and may be used as a starting point for future sessions of Base System Builder.  Click FINISH.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_18a.jpg)]]
+
+Select the option to start using Platform Studio, and click OK.
+
+[[Image(Exercises/XPSIntro/Files:xps_development_19a.jpg)]]