wiki:FAQ/Hardware

FAQ/Hardware


How do I format CompactFlash cards for use with the SystemACE controller?

The SystemACE controller can only use CompactFlash cards formatted as FAT12 or FAT16 drives. Starting with XP, Windows will only format drives as FAT32 or NTFS. Instead, you can use an open-source command line tool, mkdosfs, to format cards.

  1. Download mkdosfs.zip. You can read more about mkdosfs and download the source from the author's site.
  2. Unzip the program, open a Windows command prompt and change to the mkdosfs directory.
  3. Mount your CompactFlash card and look for the drive letter Windows assigns it in My Computer.
  4. Run the following command, replacing "X" with the drive letter of your CompactFlash card:
       mkdosfs -v -F 16 X:
    

How do I use ACE files?

The SystemACE controller on the FPGA Board is capable of many features including downloading files from the CompactFlash card. More details on using ACE files and the SystemACE controller are available here.


I'm not getting any serial port interaction.

There are several problems that could cause this:

  1. Incorrect cable type (this is most common): the WARP FPGA board's RS-232 interface is configured exactly like a PC. In order to connect it directly to another PC, you need a null modem cable or adapter (i.e. one which cross the Tx and Rx signals).
  2. A system with a different hardware configuration has been redownloaded to WARP. In rare cases, the program running in the FPGA's PowerPC can lock up if a new system has been downloaded that has a different hardware configuration. The solution to this is to simply power cycle the board; be sure to leave the board off for a few seconds to allow the capacitors to discharge.

The serial port only shows random characters.

Make sure the Baud Rate set in Tera Term Pro is the same as that in the XPS project. To check the Baud Rate in a XPS project is go to System Assembly View -> Right-click "RS232" -> Configure IP. If you do change the Baud Rate in XPS the bitstream will have to be regenerated. We suggest using 56700 bps; we have observed problems interacting with some PCs at the maximum speed of 115200 bps.


Why can't I configure the FPGA using the JTAG connector on the board?

The WARP FPGA board supports downloading bitstreams by two methods.

The recommended method is to use the built-in USB programming capability on the WARP FPGA Board. Simply connect a USB cable to the USB port on the bottom of the board (component J52). The first time you connect this to your PC, Windows will install the appropriate drivers. This process usually takes a few minutes. Wait until Windows notifies you that "Your new hardware is installed and ready for use" before trying to configure the FPGA. Once the drivers are installed, any Xilinx configuration tool (iMPACT, ChipScope, XPS) will see a standard JTAG cable attached to your PC.

The alternate method is to use a Xilinx programming cable like the Parallel IV or Platform USB cables. These cables connect to the standard 14-pin programming header on the FPGA board. The header is labeled 'SysACE' and is component J49. If your FPGA board has previously been configured via the USB port, this connector will *not* work until you disable the USB port. Follow the directions below to accomplish this.


How do I bypass the FPGA board's USB configuration interface?

In some cases, it is necessary to bypass the WARP FPGA board's built-in USB configuration circuit. You will need an external Xilinx programming cable to do this.

  1. Locate the 14-pin programming header (component J51) on the back of the FPGA board that is labaled 'CPLD'. Of the two programming headers, this one is nearer the center of the board.
  2. Connect the programming cable's JTAG cable to this header.
  3. Run Xilinx iMPACT (Start->Programs->Xilinx ISE->Accessories->iMPACT)
  4. Initialize the boundary-scan chain. A single CPLD device should be located.
  5. Right-click on the CPLD (probably labeled XC2C256) and choose Erase.

iMPACT should then display a blue notice that the erasing process was successful. If so, the USB circuit is now bypassed and the FPGA can be configured by its own JTAG header (J49). The USB circuit will be automatically re-enabled the next time it is used in iMPACT.

Last modified 9 years ago Last modified on Dec 10, 2009, 3:20:59 PM