Changes between Version 2 and Version 3 of FPGA Board


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Timestamp:
Nov 12, 2005, 10:01:12 PM (19 years ago)
Author:
murphpo
Comment:

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  • FPGA Board

    v2 v3  
    11= WARP FPGA Board =
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    3 See also: [wiki:"FPGA Board Design Files"].
    42
    53The WARP hardware must provide substantial processing resources to meet the computational needs of wireless systems operating at 100s of Mb/sec. Wireless algorithms require a large number of DSP-centric computations, yet DSPs and other similarly structured processors do not provide nearly enough processing power. We chose FPGAs as the WARP processor. Large FPGAs provide tremendous processing resources composed largely of parallel, programmable logic blocks which can be interconnected to form complex functional units. FPGAs are also extremely well suited for DSP-intensive operations, especially in applications where algorithms can be parallelized. For example, the front-end processing for many wireless applications requires high-throughput operations like filters and correlators replicated for each wireless interface. Implementations of these operations can exploit parallel structures in hardware to improve performance. Further, each instance of a functional unit operates in parallel with all others. Such multi-level parallelism is a key way FPGAs provide performance far beyond the capabilities of even the most powerful DSP.
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    1715
    1816This presents the challenge of connecting multiple FPGAs together when the need arises. We address this scalability requirement by utilizing the multi-gigabit transceivers built into Virtex-4 FPGAs. Each MGT provides a full duplex 3+ Gb/sec connection between two FPGAs; multiple MGTs can be used in parallel to provide even more throughput between two boards. Eight MGTs will be routed to off-board connectors on each WARP FPGA board, providing substantial (24 Gb/s) inter-FPGA communications capabilities. A frequently cited drawback to MGTs is their relatively high latency. These delays are imposed by the transceivers in order to combat reference clock frequency offsets. The WARP hardware will bypass this limitation by providing flexible clock resources which can be shared among multiple FPGA boards. Transceivers which share a reference clock can communicate with significantly lower latencies, usually on the order of a few cycles. Independent clocking will also be supported for situations where MGTs are used to interface with non-WARP hardware.
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     18== WARP FPGA Board Design Files ==
     19The FPGA board design files are available in the WARP [source:"/trunk/Hardware/FPGA Board/" repository].