Changes between Version 4 and Version 5 of FPGA Board

Timestamp:

Dec 28, 2006, 3:37:51 AM (17 years ago)

Author:

murphpo

Comment:

--

FPGA Board

@@ -3 +3 @@
 The WARP hardware must provide substantial processing resources to meet the computational needs of wireless systems operating at 100s of Mb/sec. Wireless algorithms require a large number of DSP-centric computations, yet DSPs and other similarly structured processors do not provide nearly enough processing power. We chose FPGAs as the WARP processor. Large FPGAs provide tremendous processing resources composed largely of parallel, programmable logic blocks which can be interconnected to form complex functional units. FPGAs are also extremely well suited for DSP-intensive operations, especially in applications where algorithms can be parallelized. For example, the front-end processing for many wireless applications requires high-throughput operations like filters and correlators replicated for each wireless interface. Implementations of these operations can exploit parallel structures in hardware to improve performance. Further, each instance of a functional unit operates in parallel with all others. Such multi-level parallelism is a key way FPGAs provide performance far beyond the capabilities of even the most powerful DSP.
 
-[[Image(WARPImages:FPGABoard.png)]]
+[[Image(WARPImages:WARP_FPGABoard_Photo_sm.jpg)]]
 
-The main board in the platform is the WARP FPGA board. At the heart of this design will be a Xilinx Virtex-4 FPGA, the latest and most powerful available. These FPGAs are very well suited for the kinds of DSP-intensive operations which the various applications for WARP will require. For example, the Virtex-4 provides dedicated DSP slices, hardware blocks designed specifically for high speed multiply-accumulate and other DSP operations. These slices are a feature not available in the FPGA used by the TAP platform and will play a major role in implementing computationally intensive wireless algorithms on WARP. Virtex-4 FPGAs also provide flexible and fast interconnect options for interfacing peripherals and creating multi-processor systems, two primary requirements of the platform design. Some versions of Virtex-4 also include embedded PowerPC processor cores, providing an ideal resource for implementing higher layer algorithms better suited for general purpose processors than programmable logic.
+The main board in the platform is the WARP FPGA board. At the heart of this design will be a Xilinx Virtex-4 FPGA. These FPGAs are very well suited for the kinds of DSP-intensive operations which the various applications for WARP will require. For example, the Virtex-4 provides dedicated DSP slices, hardware blocks designed specifically for high speed multiply-accumulate and other DSP operations. These slices are a feature not available in the FPGA used by the TAP platform and will play a major role in implementing computationally intensive wireless algorithms on WARP. Virtex-4 FPGAs also provide flexible and fast interconnect options for interfacing peripherals and creating multi-processor systems, two primary requirements of the platform design. Some versions of Virtex-4 also include embedded PowerPC processor cores, providing an ideal resource for implementing higher layer algorithms better suited for general purpose processors than programmable logic.
 
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