Physical Layer Development on WARP

The Xilinx Virtex-II Pro on the FPGA board is well-suited to the DSP heavy-lifting required by modern physical layer designs. This page is intended to outline some basic requirements that users' PHYs must meet in order to interface with the WARP Platform Support Packages.

What we provide

• WARPLab - Over-the-air physical layer prototyping inside MATLAB
• WARP FPGA Board XBD - WARP FPGA Board description file for Xilinx Platform Studio
• sysgen2opb - Matlab script to convert System Generator hardware co-simulation models into OPB peripherals
• Custom Peripherals
  • Radio Controller - core and driver for controlling the WARP radio board
  • Radio Bridge - core used to interface the radio controller to the underlying hardware
  • EEPROM - core used to access the EEPROM devices located on the WARP FPGA and WARP radio boards.
  • SISO Automatic Gain Control - Automatic Gain Control
  • Browse All Peripherals in the WARP Repository

Requirements for PHY

In general, it is impossible to specify in full generality the information that must be shared between any possible MAC layer with any possible PHY. For example, novel cross-layer designs will require much more sharing of state information than present in the reference design. However, a large class of PHY-MAC interfaces will share certain behaviors like triggers to begin transmission and header copy commands. With that in mind, we have created WARPPHY as an additional layer of abstraction to the drivers of our custom peripherals. New PHYs need to recreate this to provide a common interface to existing MAC layers.

Exercises

• Introduction to sysgen2opb​ (0.1MB PDF) Lab Files​ (4.5MB ZIP)
• Building a Simple Transmitter​ (0.1MB PDF) Lab Files​ (7.6MB ZIP)

Reference Design

The primary reference design uses an OFDM PHY and CSMA MAC.