Changes between Version 12 and Version 13 of GettingStarted/WARPv3/IntroToTools
- Timestamp:
- Aug 20, 2012, 3:02:08 PM (12 years ago)
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GettingStarted/WARPv3/IntroToTools
v12 v13 4 4 5 5 Developing custom applications on WARP requires using design tools from Xilinx. These tools are sophisticated (i.e. they're complicated) and can be daunting to a new user. We've created some simple exercises that introduce the core tools most WARP users will use. 6 7 6 8 7 == Basic Design Structure == … … 24 23 * Off-chip resources: these blocks represent the other hardware on WARP v3 besides the FPGA, like the radio interfaces, FTDI USB-UART transceiver and Marvell Ethernet PHYs 25 24 26 The MicroBlaze processor and connected cores are all implemented in the FPGA fabric using XPS. The output of the XPS flow is a "bitstream" with the fully synthesized and implemented hardware design. This bitstream integrates the MicroBlaze, the standard peripheral cores, your custom cores, I/O assignments , clock configurations and timing constraints. However the MicroBlaze instruction and data memories are blank in this bitstream.25 The MicroBlaze processor and connected cores are all implemented in the FPGA fabric using XPS. The output of the XPS flow is a "bitstream" with the fully synthesized and implemented hardware design. This bitstream integrates the MicroBlaze, the standard peripheral cores, your custom cores, I/O assignments and clock configurations. However the MicroBlaze instruction and data memories are blank in this bitstream. 27 26 28 27 The XPS-generated bitstream (and its associated hardware specification) is the starting point for an SDK project. The SDK compiles custom code for the MicroBlaze, along with drivers for the various cores included in the XPS hardware design. The output of this process is an "elf" file, the software binary ready for execution by the MicroBlaze. The elf binary is combined with the XPS-generated bitstream to program the FPGA with the final hardware+software design. … … 30 29 == Exercises == 31 30 32 '''[wiki:Exercises/HelloWorld SDK Intro:]''' This is the classic "hello world" project for WARP v3 using the Xilinx SDK. We provide an already-built bitstream with a MicroBlaze and some basic peripheral cores. This exercise uses the SDK to write some simple C code, compile it for the template hardware project and download the harware+software design to the WARP v3 board. At the end of this exercise you should be comfortable with the basic software design flow using the SDK.31 We have designed the exercises below to introduce the Xilinx tools we use for building designs on WARP v3. We recommend working through the exercises in order. 33 32 34 '''[wiki:Exercises/SysGenExport XPS Intro:]''' This exercise introduces 33 '''[wiki:Exercises/13_4/IntroToSDK SDK Intro:]''' This is the classic "hello world" project for WARP v3 using the Xilinx SDK. This exercise show: 34 * How to create a Xilinx SDK workspace and import existing hardware, bsp and software projects 35 * How to update C code and compile the software project 36 * How to download and execute a software project on WARP v3 35 37 36 * [wiki:Exercises/SysGenExport] - In this exercise, users will instead control the LEDs on the board with an FPGA design constructed in Xilinx System Generator. The process this exercise takes you through mirrors the steps that would occur if this peripheral core were a new physical layer. 38 '''[wiki:Exercises/13_4/IntroToXPS XPS Intro:]''' This exercise introduces Xilinx Platform Studio (XPS). This exercise shows: 39 * How to open and navigate one of the WARP v3 template projects 40 * How to instantiate a custom peripheral core in XPS 41 * How to access the custom core's registers from a software project in the SDK 42 43 '''[wiki:Exercises/SysGenExport:]''' In this exercise, you will create a custom peripheral using Xilinx System Generator (an FPGA design tool integrated with MATLAB/Simulink). This custom peripheral can then be used in an XPS project, using the procedure introduced in the XPS Intro exercise above. 37 44 38 In addition to being well-suited for real-time physical layer implementations, WARP also allows physical layers to be rapidly prototyped through the [wiki:WARPLab] design flow. WARPLab allows physical layers to be designed directly in Matlab and prototyped through actual over-the-channel transmissions while processing occurs offline on your computer. 45 == Reference Designs == 46 Once you're comfortable with the design flows introduced by the exercises above, we recommend getting started with one of our reference designs. 47 * [wiki:WARPLab WARPLab]: A framework for rapid prototyping of physical layer algorithms in MATLAB, using real signals transmitted/received via WARP hardware. 48 * [wiki:OFDMReferenceDesign OFDM Reference Design]: Implements an OFDM physical layer transceiver and CSMA MAC protocol, both of which operate in real-time in the FPGA 39 49 40 = I Want to Study the Higher Networking Layers = #mac41 42 One of the most common networking applications for WARP is the study of novel medium access control (MAC) protocols. Typically, MACs are implemented as software written in C and run on a MicroBlaze processor core in the FPGA. As such, the best example to start with is:43 44 * [wiki:Exercises/HelloWorld] - The Hello World exercise is what we recommend all new users of WARP start with. By the end of it, users will use C-code to control LEDs on the board as well as print messages over UART.45 46 After that, it is best to jump to the [wiki:OFDM OFDM Reference Design] and set up a link using the CSMA MAC code included in the design. This serves as a good example on how to write custom MAC software for WARP.
