CM-PLL Clock Module: Configuration

The CM-PLL board includes a 6-position DIP switch to configure various functions.

Reference Clock Output

Switch 1 controls the reference clock output pin on the external header:

Switches	Configuration
	Disables the reference clock output. Use this configuration when no cable is connected to the OUT external header.
	Enables the reference clock output. Use this configuration when a cable is connected to the OUT external header and the downstream CM-PLL has selected its external header reference clock input.

Reference Clock Source

Switches 2 and 3 control the reference clock mux:

Switches	Configuration
	Selects the MMCX Jack reference clock input. Use this configuration when driving the reference clock from external equipment or from a CM-MMCX clock module on another WARP v3 kit.
	Selects the External Header reference clock input. Use this configuration when driving the reference clock from another CM-PLL clock module on another WARP v3 kit via the board-to-board headers.
	Selects the Local WARP v3 Oscillator reference clock input. Use this configuration when no external reference clock is required. This configuration should be used at the first node in a daisy chain of WARP v3 kits with CM-PLL modules.

Reference Clock Source

Switches 4-6 are connected to FPGA I/O. The FPGA design should read these switch values to configure clock modes at boot. Refer to the w3_clock_controller documentation for details on the default use of these switches in the reference designs for WARP v3.