Changes between Version 2 and Version 3 of HardwareUsersGuides/CM-PLL/FPGA_IO

Timestamp:

Mar 2, 2015, 10:47:25 AM (9 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/CM-PLL/FPGA_IO

@@ -40 +40 @@
 Eight FPGA I/O are tied directly to the [wiki:../Connectors#Board-to-BoardHeaders board-to-board headers]. While these headers are labeled "In" and "Out" (indicating the role of the reference clock pin in each header), these 8 FPGA I/O can be used as any mix of inputs and outputs.
 
-Two additional FPGA I/O are connected to the CM-PLL reference clock buffer. This connection allows the FPGA design to monitor the status of the PLL reference clock, independent of the PLL status. The [wiki:cores/w3_clock_controller w3_clock_controller core] uses this connection to delay configuration of the PLL until a valid reference clock is observed. This simplifies the boot process for nodes connected in a daisy chain configuration. The reference clock buffer output uses LVDS signaling. The FPGA pins must implement LVDS termination to receive this clock signal. Use the {{{IOSTANDARD = LVDS_25}} and {{{DIFF_TERM = TRUE}}} constraints to enable LVDS termination in the FPGA IOBs.
+Two additional FPGA I/O are connected to the CM-PLL reference clock buffer. This connection allows the FPGA design to monitor the status of the PLL reference clock, independent of the PLL status. The [wiki:cores/w3_clock_controller w3_clock_controller core] uses this connection to delay configuration of the PLL until a valid reference clock is observed. This simplifies the boot process for nodes connected in a daisy chain configuration. The reference clock buffer output uses LVDS signaling. The FPGA pins must implement LVDS termination to receive this clock signal. Use the {{{IOSTANDARD = LVDS_25}}} and {{{DIFF_TERM = TRUE}}} constraints to enable LVDS termination in the FPGA IOBs.
 
 == WARP v3 Clock Buffer I/O ==