Changes between Version 3 and Version 4 of HardwareUsersGuides/CM-PLL/FPGA_IO

Timestamp:

Mar 2, 2015, 8:51:44 PM (9 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/CM-PLL/FPGA_IO

@@ -44 +44 @@
 == WARP v3 Clock Buffer I/O ==
 
+The CM-PLL circuits connect to the WARP v3 clock buffers. Specifically:
+ 1. The WARP v3 RF Reference Clock buffer output can be selected as a PLL reference clock on the CM-PLL module
+ 1. The WARP v3 RF Reference Clock and Sampling Clock buffers can be driven by the CM-PLL VCXO
+
+The first connection allows a WARP v3 node equipped with a CM-PLL module to use its on-board TCXO as the frequency reference for the PLL, and to forward the reference to other CM-PLL via the board-to-board headers.
+
+The second connection allows the CM-PLL to drive all the clock signals on the host WARP v3 board, enabling full synchronization of the sampling and RF reference clocks across multiple WARP v3 nodes.
+