Changes between Version 4 and Version 5 of HardwareUsersGuides/CM-PLL/FPGA_IO


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Timestamp:
Mar 2, 2015, 8:53:05 PM (9 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/CM-PLL/FPGA_IO

    v4 v5  
    5252The second connection allows the CM-PLL to drive all the clock signals on the host WARP v3 board, enabling full synchronization of the sampling and RF reference clocks across multiple WARP v3 nodes.
    5353
     54The AD9511 PLL on the CM-PLL and the two AD9512 buffers on WARP v3 must be configured jointly to realize these configurations. Refer to the [wiki:cores/w3_clock_controller w3_clock_controller] documentation for details on the standard configurations we use in the reference designs.