Changes between Version 4 and Version 5 of HardwareUsersGuides/CM-PLL


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Timestamp:
Feb 5, 2015, 3:20:10 PM (10 years ago)
Author:
chunter
Comment:

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  • HardwareUsersGuides/CM-PLL

    v4 v5  
    33
    44= CM-PLL Clock Module User Guide =
    5 [[Image(wiki:HardwareUsersGuides/CM-PLL/files:CM-PLL_angle_sm.jpg, nolink)]]
     5
     6[[Image(wiki:HardwareUsersGuides/CM-PLL/files:CM-PLL_angle_sm.png, nolink,width=400)]]
    67
    78The CM-PLL is a clock module for [wiki:HardwareUsersGuides/WARPv3 WARP v3] which generates a low-noise 80MHz clock synchronized to an off-board reference. The reference clock can be derived from the WARP v3 main oscillator, from external equipment connected to the board's MMCX jack or from another CM-PLL via the external board-to-board header. A block diagram of the CM-PLL circuits is shown below.