WARP Clock Board Configuration

The AD9510 clock buffers have serial interfaces for configuring their internal register banks. We provide a custom hardware core which implements the necessary logic to drive these interfaces. The clock_board_config core automatically configures the clock board when included in an FPGA design. This core requires a clock input which does not come from the clock board; the FPGA board's 100 MHz oscillator works well. Most of the core's other ports must be tied to the clock board connector's data pins, according to the following table. This assignment is handled automatically if you build your project using Base System Builder and the WARP FPGA Board's XBD.

clock_board_config Port	Clock Board Header Pin	FPGA Pin
cfg_radio_dat_out	13	AN25
cfg_radio_csb_out	12	AK26
cfg_radio_en_out	11	AJ25
cfg_radio_clk_out	15	AL26
cfg_logic_dat_out	19	AT27
cfg_logic_csb_out	18	AR27
cfg_logic_en_out	16	AN27
cfg_logic_clk_out	20	AM27

Selecting the Clock Sources

By default, the clock_board_config core selects the on-board oscillators as the clock sources for both AD9510 buffers. It is possible to select the off-board connectors as the source for each buffer. In this configuration, the clock board will be frequency-locked to the source clock board. The clock source for each buffer can be selected independently.

The clock source is configured via a combination of top-level parameters and ports on the clock_board_config core.

Radio reference clock source selection:

radio_clk_source_sel_mode parameter	fpga_radio_clk_source parameter	radio_clk_src_sel port	Clk Source
0	0	X	20MHz Oscillator
0	1	X	MMCX jack J2
1	X	0	20MHz Oscillator
1	X	1	MMCX jack J2

Sampling clock source selection:

logic_clk_source_sel_mode parameter	fpga_logic_clk_source parameter	logic_clk_src_sel port	Clk Source
0	0	X	40MHz Oscillator
0	1	X	MMCX jack J3
1	X	0	40MHz Oscillator
1	X	1	MMCX jack J3

If you want to control the clock source at run-time (i.e. without having to re-build hardware after changing a core parameter), you can connect the two control ports to DIP switches on the FPGA board. The OFDM Reference Design does this, using two positions on the DIP switch on the radio board in slot 2 to control the sampling and logic clock sources at boot.