FMC-BB-4DA User Guide: DACs

The FMC-BB-4DA is built around two Analog Devices AD9116 devices. Each AD9116 provides two 12-bit, 125MSps DACs.

All digital signals from both AD9116 are tied to FMC I/O pins. The user's FPGA design is responsible for all control, clocking and data input to the DACs.

Note: The FMC-BB-4DA PCB is designed to support all of the AD9114/AD9115/AD9116/AD9117 pin-compatible DACs. The schematics refer to the 14-bit AD9117. The PCB connects all 14 bits of the AD9117 data bus to the FMC header. The two LSB (DB[1:0], AD9117 pins [14,15]) are unused on boards assembled with the 12-bit AD0116.


The digital sample interface for each AD9116 is a 12-bit DDR bus, with samples for the two DACs presented on alternating clock edges. Refer to the AD9116 datasheet for timing specifications of the DDR interface. The fmc_bb_4da_bridge core demonstrates how to use ODDR primitives in a Virtex-6 FPGA to interface two 12-bit signals in the FPGA to one 12-bit DDR output.


Each AD9116 has one clock input. The input clock is used by both DACs in the IC. The digital and analog sample rates of the two DACs in each AD9116 are equal to the input clock frequency. The two AD9116's on the FMC-BB-4DA can be clocked at different frequencies, if desired. In order to meet setup/hold requirements at the AD9116 the user FPGA design should shift the clock signal (ideally by 90 degrees) away from transitions in the data signals.


The AD9116 has four digital control signals. These signals operate either as direct control lines or as an SPI interface. We use these signals in direct control mode (called "pin mode" in the AD9116 datasheet). User applications can instantiate an SPI controller and use this interface in SPI mode, if desired.

The function of the four control signals are listed in the table below. The default values listed here match those implemented in the fmc_bb_4da_bridge core.

Signal AD9116 Pin Default Function
PINMD 35 1 Enables "pin mode" for the control interface, disables SPI register access
CLKMD 36 0 Determines phase relationship of data and DAC clocks
FORMAT 37 1 Sets data format (0: offset binary, 1: two's complement)
PWRDN 38 0 Powers down control (1: power off all circuits (except SPI) in the AD9116)
Last modified 6 years ago Last modified on Feb 18, 2013, 1:43:31 PM