Changes between Version 2 and Version 3 of HardwareUsersGuides/FMC-BB-4DA/DACs
- Timestamp:
- Feb 18, 2013, 1:43:24 PM (11 years ago)
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HardwareUsersGuides/FMC-BB-4DA/DACs
v2 v3 6 6 All digital signals from both AD9116 are tied to FMC I/O pins. The user's FPGA design is responsible for all control, clocking and data input to the DACs. 7 7 8 Note: The FMC-BB-4DA PCB is designed to support all of the AD9114/AD9115/AD9116/AD9117 pin-compatible DACs. The schematics refer to the 14-bit AD9117. The PCB connects all 14 bits of the AD9117 data bus to the FMC header. The two LSB (DB [1:0], AD9117 pins[14,15]) are unused on boards assembled with the 12-bit AD0116.8 Note: The FMC-BB-4DA PCB is designed to support all of the AD9114/AD9115/AD9116/AD9117 pin-compatible DACs. The schematics refer to the 14-bit AD9117. The PCB connects all 14 bits of the AD9117 data bus to the FMC header. The two LSB (DB![1:0], AD9117 pins ![14,15]) are unused on boards assembled with the 12-bit AD0116. 9 9 10 10 == Data == … … 20 20 21 21 ||= Signal =||= AD9116 Pin =||= Default =||= Function =|| 22 || PINMD || 35 || 1|| Enables "pin mode" for the control interface, disables SPI register access ||23 || CLKMD || 36 || 0|| Determines phase relationship of data and DAC clocks ||24 || FORMAT || 37 || 1|| Sets data format (0: offset binary, 1: two's complement) ||25 || PWRDN || 38 || 0|| Powers down control (1: power off all circuits (except SPI) in the AD9116) ||22 || PINMD || 35 || 1 || Enables "pin mode" for the control interface, disables SPI register access || 23 || CLKMD || 36 || 0 || Determines phase relationship of data and DAC clocks || 24 || FORMAT || 37 || 1 || Sets data format (0: offset binary, 1: two's complement) || 25 || PWRDN || 38 || 0 || Powers down control (1: power off all circuits (except SPI) in the AD9116) || 26 26 27 27