Changes between Version 5 and Version 6 of HardwareUsersGuides/FMC-RF-2X245/Clocking


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Timestamp:
Sep 7, 2013, 3:09:03 PM (11 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/FMC-RF-2X245/Clocking

    v5 v6  
    2626The DIP switch has six separate switches, labeled 1-6 on the component itself. Each switch is On or Off, where the On position is labeled on the switch. See the figure below for details.
    2727
    28 [[Image(wiki:HardwareUsersGuides/FMC-RF-2X245/files:FMC-RF-2X245_dipsw.jpg, nolink)]]
     28[[Image(wiki:HardwareUsersGuides/FMC-RF-2X245/files:2X245_clocking_DIPSW.png, nolink, width=200)]]
    2929
    3030The DIP switch settings should only be changed when the module is unpowered. Some combinations of switch states are invalid- always ensure switch settings using the tables below.
    3131
    32 '''The default setting is switches 3 and 5 ON, switches 1,2,5,6 OFF.''' These settings enable both clock buffers and set all dividers to 1.
     32'''The default setting is switches 3 and 5 ON, switches 1, 2, 5, 6 OFF.''' These settings enable both clock buffers and set all dividers to 1.
     33
     34'''The tables below list all valid switch settings. Any other switch setting is invalid and will result in unpredictable clock behavior.'''
    3335
    3436=== Sampling Clock Buffer ===
    … …  
    3941
    4042The divider for OUT0/OUT1 can be configured to 1, 2 or 4 via the DIP switch:
    41 ||= Divider =||= SW1.x =||= SW1.y =||
    42 || 1 || x || x ||
    43 || 2 || x || x ||
    44 || 4 || x || x ||
     43||= AD Clock[[BR]]Divider =||= SW![3] =||= SW![4] =||
     44||  1  ||  ON  ||  OFF ||
     45||  2  ||  OFF  ||  OFF ||
     46||  4  ||  OFF  ||  ON ||
    4547
    46 The output to the FMC header (OUT2) can be en/disabled via the DIP switch:
    47 ||= OUT2 =||= SW1.x =||
    48 || Off || x ||
    49 || On || x ||
     48The clock output to the FPGA via the FMC header (OUT2) can be en/disabled via the DIP switch:
     49||= Clock to[[BR]]FPGA =||= SW![1] =||= SW![2] =||
     50|| Enabled ||  OFF  ||  OFF ||
     51|| Disabled ||  ON  ||  ON ||
    5052
    51 The output to the FMC header (OUT2) should only be enabled when the FMC-RF-2X245 module is built for on-board clocking. When using the FMC-RF-2X245 module on a WARP v3 kit the FPGA receives the sampling clock directly and does not require another copy be driven to the FMC slot.
     53The output to the FMC header (OUT2) is provided for use when the FMC-RF-2X245 module is built for on-board clocking. When using the FMC-RF-2X245 module on a WARP v3 kit the FPGA receives the sampling clock directly and does not require another copy be driven via the FMC slot.
    5254
    5355=== RF Reference Clock Buffer ===
    … …  
    5658The divider should be chosen to comply with the MAX2829 reference clock frequency requirements. Typically the MAX2829 requires a 20MHz or 40MHz reference clock input.
    5759
    58 ||= Divider =||= SW1.1 =||= SW1.2 =||
    59 || 1 || x || x ||
    60 || 2 || x || x ||
    61 || 4 || x || x ||
     60||= RF Ref Clock[[BR]]Divider =||= SW![5] =||= SW![6] =||
     61||  1  ||  ON  ||  OFF ||
     62||  2  ||  OFF  ||  OFF ||
     63||  4  ||  OFF  ||  ON ||