WARP FPGA Board Clocking
On-board Oscillators
The FPGA board has two oscillator footprints for general clocks. By default, one 100MHz oscillator is mounted (component Y5) and one footprint is left empty (component Y6) for future customization. Both oscillator footprints are connected to global clock (GCLK) pins on the FPGA.
The Virtex-II Pro FPGA contains 8 Digital Clock Managers (DCM) which can synthesize a wide range of clock signals given the 100MHz oscillator input.
| Clock | Component | FPGA Pin |
| 100MHz | Y5 | AH21 |
| NM | Y6 | AH20 |
Off-board Clock Sources
The FPGA board has a header dedicated to off-board clocks. This header (component J29) is used by the WARP Clock Board. The header connects to four global clock (GCLK) pins on the FPGA, the 3.3v power plane and 8 general FPGA I/O.
| Header Pin | FPGA GCLK | FPGA Pin |
| 3 | GCLK0P | AK20 |
| 4 | GCLK1S | AL20 |
| 7 | GCLK6P | AT20 |
| 8 | GCLK7S | AR20 |
SystemACE CF Clocking
The SystemACE CF controller requires a 33MHz clock which runs at all times. The FPGA requires a copy of this clock in order to use the SystemACE controller's microprocessor interface. A dedicated 33MHz oscillator (component Y4) is used on the FPGA board to supply this clock. The oscillator's output is split and driven to both the FPGA and the SystemACE CF controller.
| Clock | Component | FPGA Pin |
| 33MHz | Y4 | N20 |
MGT Clocking
Please see MGTs for details on clocking the FPGA's multi-gigabit transceivers.
Other References
- Xilinx Virtex-II Pro Datasheet (Module 3: DC & Switching Characteristics)
- Xilinx Virtex-II Pro Users Guide (Chapter 2: Timing Models and Chapter 3: Digital Clock Managers)
- WARP FPGA Board Schematics (pg. 2)
