| | 4 | |
| | 5 | The [wiki:"FPGA Board" WARP FPGA Board] has four daughtercard slots. The four slots are electrically and mechanically identical. A daughtercard designed to meet the specifications below can be used in any of these slots. |
| | 6 | |
| | 7 | === Electrical Details === |
| | 8 | |
| | 9 | Each daughtercard slot consists of two 80-pin connectors on the FPGA board. 124 pins are routed to dedicated I/O on the FPGA. The remaining 36 signals are used for power and ground connections. On the Virtex-II Pro WARP FPGA board, each daughtercard slot is routed to a dedicated I/O bank on the FPGA. These I/O banks are configured for 3.3v single-eneded I/O and support 50Ω digitallly controlled impedence. The 36 power pins are split between ground (20 pins), +5v (12 pins) and -5v (4 pins). The ground pins are connected directly to the ground planes on the FPGA board. The +5v pins are connected to a dedicated 18A switching supply on the FPGA board. The -5v pins are connected to a header on the FPGA board which can be populated with an isolated supply when needed. The power pins on the four daughtercard slots are all connected together on the FPGA board. |
| | 10 | |
| | 11 | See the [source:"/Hardware/FPGA_Board" WARP FPGA Board Schematics] for the actual circuits implemented on the FPGA board. |
| | 12 | |
| | 13 | === Schematic === |
| | 14 | |
| | 15 | This is a schematic view of the 160-pin daughtercard slot. The connectors are represented by a heterogeneous part, each containing 80 pins. The 36 power pins are connected to ground, +5v and -5v (EXT_DGND, EXT_5v, EXT_-5v in the schematic). The source file for this schematic is available [wiki:DaughtercardSpec#ReferenceDesigns below]. |
| | 16 | |
| | 17 | [[Image(WARPImages:DaughtercardSlotSchematic.png)]] |
| | 18 | |
| | 19 | === Mechanical === |
| | 20 | WARP daughtercards must meet certain mechanical requirements. First, the two 80-pin connectors must be oriented, aligned and spaced to match the placement of the mating connectors on the FPGA board. Second, a mounting hole should be included to secure daughtercards to their slots. Finally, the PCB must not extend beyond certain dimensions in order to fit in the space allowed by the FPGA's heat sink and adjascent daughtercards. |
| | 21 | |
| | 22 | The drawing below is a daughtercard viewed from the top, oriented for slots !#1 and !#2 (with the FPGA board's left-edge at the left and the FPGA itself to the right). The connectors are mounted on the bottom of the daughtercard; the footprint included in this drawing is viewed from the top (i.e. through the board) as it is in PCB design tools. |
| | 23 | |
| | 24 | [[Image(WARPImages:Daughtercard_Mech_Drawing.png)]] |
| | 25 | |
| | 26 | * A = 1.471"; vertical distance from center of pin 1 to center of pin 81 |
| | 27 | * B1 = 1.923"; horizontal distance from left edge to pin 1/81 vertical |
| | 28 | * B2 = 1.005"; horizontal distance from right edge to pin 1/81 vertical |
| | 29 | * C = 0.735"; vertical distance from mounting hole center to pin 1 |
| | 30 | * D = 0.883"; horizontal distance from mounting hole center to pin 1/81 vertical |
| | 31 | * E = 2.928"; horizontal edge to edge |
| | 32 | * F = 1.780"; vertical edge to edge |
| | 33 | * øG = 0.1" (diameter before plating); plated mounting hole (connected to ground) |
| | 34 | |
| | 35 | A vector PDF version of this drawing is also available: [attachment:wiki:WARPFiles:Daughtercard_Mech_Drawing.pdf?format=raw Daughtercard Mechanical Drawing PDF]. |
| | 36 | |
| | 37 | WARP daughtercards use two 80 pin headers per daughtercard slot. The connectors are 0.5mm pitch, 4mm height headers with metal fittings from the Hirose DF17 series of connectors. The Hirose part number is DF17(4.0)-80DP-0.5V(57). See the [attachment:wiki:WARPFiles:Hirose_DF17_Connectors_Datasheet.pdf?format=raw Hirose DF17 Connectors Datasheet] for the full mechanical details (pg 6) and recommended PCB footprint (pg 8). |
| | 38 | |
| | 39 | The parts are available from [http://www.digikey.com Digikey]; search for Digikey part number H11148CT-ND. |
| | 40 | |
| | 41 | === Reference Designs === |
| | 42 | [attachment:wiki:WARPFiles:Daughtercard_Template_Schematic.zip?format=raw Daughtercard_Template_Schematic.zip] |
| | 43 | Cadence Capture CIS 15.7 project, schematic design and parts library. |
| | 44 | |
| | 45 | [attachment:wiki:WARPFiles:Daughtercard_Template_Board.zip?format=raw Daughtercard_Template_Board.zip] |
| | 46 | Cadence Allegro PCB Editor 15.7 padstacks, package symbols and sample board. |
