| 1 | == WARP FPGA Board Multi-Gigabit Transceivers == |
| 2 | [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTs.jpg)]] |
| 3 | |
| 4 | === VTRX Configuration === |
| 5 | Short bottom pins for 2.5v (required for WARP board-to-board links), top pins for 1.8v (for connections to AC-coupled transmitters). |
| 6 | |
| 7 | [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTVTRX.jpg)]] |
| 8 | |
| 9 | === Clocking === |
| 10 | |
| 11 | Left-oscillator connects to BREFCLK, right-oscillator connects to BREFCLK2, mount shunts to disable oscillators |
| 12 | |
| 13 | [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTCLK1.jpg)]] |
| 14 | |
| 15 | [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTCLK2.jpg)]] |
| 16 | |
| 17 | === Cables === |
| 18 | [http://www.molex.com/cgi-bin/bv/molex/jsp/products/datasheet.jsp?productid=83666 Molex HSSDC2 Jack] |
| 19 | [[BR]] |
| 20 | [http://www.molex.com/cgi-bin/bv/molex/jsp/products/datasheet.jsp?productid=35277 Molex HSDDC2 Cables] |