| 10 | The SRAM requires a memory controller in the FPGA. For EDK projects, use the Xilinx PLB External Memory Controller ([http://www.xilinx.com/bvdocs/ipcenter/data_sheet/plb_emc.pdf plb_emc.pdf]). This core is included with the EDK. One core is required per SRAM bank. Each should be configured with the following paramters: |
| 11 | {{{ |
| 12 | PARAMETER C_NUM_BANKS_MEM = 1 |
| 13 | PARAMETER C_MAX_MEM_WIDTH = 32 |
| 14 | PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1 |
| 15 | PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 |
| 16 | PARAMETER C_MEM0_WIDTH = 32 |
| 17 | PARAMETER C_SYNCH_MEM_0 = 1 |
| 18 | PARAMETER C_TCEDV_PS_MEM_0 = 0 |
| 19 | PARAMETER C_TWC_PS_MEM_0 = 0 |
| 20 | PARAMETER C_TAVDV_PS_MEM_0 = 0 |
| 21 | PARAMETER C_TWP_PS_MEM_0 = 0 |
| 22 | PARAMETER C_THZCE_PS_MEM_0 = 0 |
| 23 | PARAMETER C_TLZWE_PS_MEM_0 = 0 |
| 24 | }}} |
| 25 | |
| 26 | For projects built using Base System Builder and the WARP FPGA Board [source:/PlatformSupport/XBD/boards/Rice_University_WARP_FGPA_V2P70/data/Rice_University_WARP_FGPA_V2P70_v2_2_0.xbd XBD], this configured is automatic. |
| 27 | |
| 28 | The SRAM chips used in the current version of the board are Cypress [http://www.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=209&PageID=259&fid=39&rpn=CY7C1370D&ref=pfm CY7C1307D]. |