| | 1 | [[TracNav(HardwareUsersGuides/FPGABoard_v1.2/TOC)]] |
| | 2 | |
| | 3 | == WARP FPGA Board I/O == |
| | 4 | |
| | 5 | === 10/100 Ethernet === |
| | 6 | [http://www.intel.com/design/network/products/lan/PHYs/lxt971a-972a.htm Intel LXT972A] physical layer Ethernet transceiver |
| | 7 | |
| | 8 | [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_Ethernet.jpg)]] |
| | 9 | |
| | 10 | Three status LEDs. LEDs only work after the PHY is initialized by a MAC in the FPGA. |
| | 11 | |
| | 12 | ||'''LED'''||'''Color'''||'''Component'''|| |
| | 13 | ||Activity||Green||D3||Blinks with network activity|| |
| | 14 | ||Speed||Amber||D6||Glows for 100Mbit links|| |
| | 15 | ||Link ||Green||D7||Glows with valid PHY link|| |
| | 16 | |
| | 17 | === RS-232 UART === |
| | 18 | MAX3221 (from [http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1069 Maxim] or [http://focus.ti.com/lit/ds/symlink/max3221.pdf TI]). |
| | 19 | |
| | 20 | FPGA board configured just like a PC- male DB9 connector, Tx on 3, Rx on 2, GND on 5. Null-modem (crossover) female-female cable required to connect to PC's serial port. |
| | 21 | |
| | 22 | === Digital I/O === |
| | 23 | 16-bits of unbuffered 3.3v I/O connected directly to FPGA I/O pins. 4 ground pins. |
| | 24 | [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_DebugIO.jpg)]] |
