Changes between Version 6 and Version 7 of HardwareUsersGuides/FPGABoard_v1.2/OtherIO

Timestamp:

Jul 9, 2007, 10:27:57 AM (17 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/FPGABoard_v1.2/OtherIO

@@ -23 +23 @@
 [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_DebugIO.jpg)]]
 
-There are 16-bits of unbuffered 3.3v I/O connected directly to FPGA I/O pins, routed to standard male 100mil header. The header has four ground pins in the corner positions.
+There are 16-bits of unbuffered 3.3v I/O connected directly to FPGA I/O pins, routed to standard male 100mil header. The header has four ground pins in the corner positions. The 16 I/O signals are labeled at the header. Bits 0-7 are in the top row, bits 8-15 in the bottom, both arranged right-to-left. The FPGA pin mapping is below.
 
 || '''Signal''' || '''FPGA Pin''' ||