Changes between Version 7 and Version 8 of HardwareUsersGuides/FPGABoard_v1.2/OtherIO


Ignore:
Timestamp:
Jul 9, 2007, 10:48:15 AM (17 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/FPGABoard_v1.2/OtherIO

    v7 v8  
    44
    55=== 10/100 Ethernet ===
    6 [http://www.intel.com/design/network/products/lan/PHYs/lxt971a-972a.htm Intel LXT972A] physical layer Ethernet transceiver
     6[[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_Ethernet.jpg, right)]]
    77
    8 [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_Ethernet.jpg)]]
    9 
    10 Three status LEDs. LEDs only work after the PHY is initialized by a MAC in the FPGA.
     8The FPGA board has a 10/100 Ethernet port. This interface uses the [http://www.intel.com/design/network/products/lan/PHYs/lxt971a-972a.htm Intel LXT972A] physical layer Ethernet transceiver. The Ethernet MAC is instantiated in the FPGA. There are three Ethernet status LEDs, described below. These LEDs are only active after the PHY is initialized by a MAC in the FPGA.
    119
    1210||'''Label'''||'''Color'''||'''Component'''||'''Function'''||
    … …  
    1513||Link ||Green||D7||Glows with valid PHY link||
    1614
     15Xilinx provides a core which implements the 10/100 Ethernet MAC and attaches to the PLB ([http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?iLanguageID=1&sSecondaryNavPick=&key=PLB_EMAC&sGlobalNavPick= plb_emac]). An evaluation verison of this core is included with the EDK. The evaluation version functions normally in hardware for a fixed time period (around 7 hours) before disabling itself. The full version can be purchased from Xilinx. Universities can also request a donation of the core.
     16
     17The pin mapping for the FPGA-PHY interface is listed below. For projects built using Base System Builder and the WARP FPGA Board [source:/PlatformSupport/XBD/boards/Rice_University_WARP_FGPA_V2P70/data/Rice_University_WARP_FGPA_V2P70_v2_2_0.xbd XBD], this interface is constructed automatically.
     18
     19|| '''MII Signal''' || '''FPGA Pin''' ||
     20|| COL || J26 ||
     21|| CRS || D29 ||
     22|| MDC || J24 ||
     23|| MDINT || G27 ||
     24|| MDIO || C23 ||
     25|| PAUSE || H27 ||
     26|| RESET || J27 ||
     27|| RX_CLK || E24 ||
     28|| RX_D<0> || C22 ||
     29|| RX_D<1> || E21 ||
     30|| RX_D<2> || C21 ||
     31|| RX_D<3> || D23 ||
     32|| RX_DV || F22 ||
     33|| RX_ER || F21 ||
     34|| TX_CLK || F20 ||
     35|| TX_D<0> || D22 ||
     36|| TX_D<1> || H23 ||
     37|| TX_D<2> || D26 ||
     38|| TX_D<3> || G26 ||
     39|| TX_EN || H22 ||
     40|| TX_ER || H26 ||
     41|| TXSLEW0 || H20 ||
     42|| TXSLEW1 || J22 ||
     43
    1744=== RS-232 UART ===
    18 MAX3221 (from [http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1069 Maxim] or [http://focus.ti.com/lit/ds/symlink/max3221.pdf TI]).
     45The FPGA includes a standard RS-232 serial port. The board's female DB9 port is configured just like a PC, with Tx on pin 3, Rx on pin 2 and GND on pin 5. The rest of the signals are unconnected. You must use a null-model (i.e. crossover) cable to connect this port directly to a PC.
    1946
    20 FPGA board configured just like a PC- male DB9 connector, Tx on 3, Rx on 2, GND on 5. Null-modem (crossover) female-female cable required to connect to PC's serial port.
     47The LVTTL-RS232 level shifting is handled on the FPGA board by a MAX3221 (from [http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1069 Maxim] or [http://focus.ti.com/lit/ds/symlink/max3221.pdf TI]).
     48
     49The two UART signals are mapped to two FPGA pins:
     50|| '''Signal''' || '''FPGA Pin''' ||
     51||UART Tx       ||      AA28||
     52||UART Tx       ||      AA29||
    2153
    2254=== Digital I/O ===