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== WARP FPGA Board I/O ==

=== 10/100 Ethernet ===
[http://www.intel.com/design/network/products/lan/PHYs/lxt971a-972a.htm Intel LXT972A] physical layer Ethernet transceiver

[[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_Ethernet.jpg)]]

Three status LEDs. LEDs only work after the PHY is initialized by a MAC in the FPGA.

||'''LED'''||'''Color'''||'''Component'''||
||Activity||Green||D3||Blinks with network activity||
||Speed||Amber||D6||Glows for 100Mbit links||
||Link ||Green||D7||Glows with valid PHY link||

=== RS-232 UART ===
MAX3221 (from [http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1069 Maxim] or [http://focus.ti.com/lit/ds/symlink/max3221.pdf TI]).

FPGA board configured just like a PC- male DB9 connector, Tx on 3, Rx on 2, GND on 5. Null-modem (crossover) female-female cable required to connect to PC's serial port.

=== Digital I/O ===
16-bits of unbuffered 3.3v I/O connected directly to FPGA I/O pins. 4 ground pins.
[[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_DebugIO.jpg)]]