WARP FPGA Board User I/O

Push Buttons

Five push buttons are connected to dedicated FPGA inputs and are arranged in a cross. They are generally referred as up, down, left, right and center. The buttons are normally open connections with external pull down resistors. Thus, the FPGA will observe logic high when a button is depressed, logic low otherwise. The switches are debounced by a simple low pass filter on the board, but user applications which are sensitive to accidental or repeated rising edges should further debounce the input digitally.

In most FPGA designs, the down button is assigned to the PowerPC's soft reset input. When pushed and released, the PowerPC will reset and re-enter the user's main() function. If desired, the choice of the reset button can be changed in an EDK project's UCF file.

DIP Switch

The 4-position DIP switch drives four dedicated inputs on the FPGA. Sliding a switch to the left drives the input to logic low; to the right drives the input to logic high.

LEDs

Four discrete LEDs are connected to four FPGA outputs. A logic high output will cause a LED to glow.

Seven Segment Displays

Two 7-segment LED displays are connected to 14 dedicated FPGA outputs, where each segment is driven by an separate FPGA output. The segments are mapped as shown in the image below. The decimal point LEDs on the displays are not used.